TTL Logic Family

Introduction — Logic IC
 Logic Family : A collection of different IC’s that have similar
circuit characteristics
 A circuit configuration or approach used to produce a type of
digital integrated circuit.
 Consequence: different logic functions, when fabricated in the
form of an IC with the same approach, or in other words
belonging to the same logic family, will have identical electrical
characteristics.
 the set of digital ICs belonging to the same logic family are
electrically compatible with each other
 Common Characteristics of the Same
Logic Family

 Supply voltage range, speed of response, power dissipation,

input and output logic levels, current sourcing and sinking
capability, fan-out, noise margin, etc.
 Consequence: choosing digital ICs from the same logic
family guarantees that these ICs are compatible with
respect to each other and that the system as a whole
performs the intended logic function.

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 Integration Levels

• Gate/transistor ratio is roughly 1/10

– SSI < 12 gates/chip
– MSI < 100 gates/chip
– LSI …1K gates/chip
– VLSI …10K gates/chip
– ULSI …100K gates/chip
– GSI …1Meg gates/chip

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 Moore’s Law

 In 1965, Gordon Moore predicted that the number of

transistors that can be integrated on a die would double
every 18 to 14 months
 i.e., grow exponentially with time
 Considered a visionary – million transistor/chip barrier
was crossed in the 1980’s
 2300 transistors, 1 MHz clock (Intel 4004/4040) - 1971
 42 Million transistors, 2 GHz clock (Intel P4) - 2001
 140 Million transistors, (HP PA-8500)
IC digital logic families
 RTL （Resistor-transistor logic）
 DTL （Diode-transistor logic）
 TTL （Transistor -transistor logic）
 ECL （Emitter-coupled logic）
 MOS （Metal-oxide semiconductor）
 CMOS （Complementary Metal-oxide semiconductor）
Fan-In
 Number of input signals to a gate
 Not an electrical property
 Function of the manufacturing process

NAND gate with a

Fan-in of 8
 Fan-Out
 A measure of the ability of the output of one gate to drive the
input(s) of subsequent gates
 Usually specified as standard loads within a single family
 e.g., an input to an inverter in the same family
 The maximum number of logic inputs (of the same logic
family) that an output can drive reliably is called the fan-
out.
Logic Level and Voltage Range
 Typical acceptable voltage ranges for positive logic 1 and logic 0 are
shown below
 A logic gate with an input at a voltage level within the
‘indeterminate’ range will produce an unpredictable output level.

5.0V
Logic 1

2.5V
Indeterminate
0.8V
Logic 0
0V
TTL
 Noise Margin
Noise margin:The unwanted signals are referred to as noise
 It is the limit of a noise voltage which may be present without impairing the
proper operation of the circuit.
 Manufacturers specify voltage limits to represent the logical 0 or 1.
 These limits are not the same at the input and output sides.
 For example, a particular Gate A may output a voltage of 4.8V when it is
supposed to output a HIGH but, at its input side, it can take a voltage of 3V
as HIGH.
 In this way, if any noise should corrupt the signal, there is some margin for
error.
 Noise margin is the maximum noise added to an input signal of a digital circuit
that does not cause an undesirable change in the circuit output
Speed: Rise & Fall Times
 Rise Time
 Time from 10% to 90% of signal, Low to High
 Fall Time
 Time from 90% to 10% of signal, High to Low

rise time fall time

10% 90% 90% 10%

  The average transition-delay time for the signal to propagate from
input to output when the binary signal changes in value
 It is the time delay between the specified voltage points
on the input and output waveforms.
 Propagation delays are separately defined for LOW-to-
HIGH and HIGH-to-LOW transitions at the output. In
addition, we also define enable and disable time delays
that occur during transition between the high-impedance
state and defined logic LOW or HIGH states.

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 TPD,HL TPD,LH

TPD,HL – input-to-output propagation delay from HI to LO output

TPD,LH – input-to-output propagation delay from LO to HI output

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 The power dissipation parameter for a logic family is
specified in terms of power consumption per gate and is
the product of supply voltage VCC and supply current
ICC
 The power needed by the gate, Expressed in mW
Power Dissipation
 Static
 I2R losses due to passive components, no input signal
 Dynamic
 I2R losses due to charging and discharging capacitances through
resistances, due to input signal
Power dissipation
I CCH + I CCL
I CC (avg ) =
2
PD (avg ) = I CC (avg ) × VCC
Feature of BJT
 BJT
 npn or pnp
 Si or Ge
 Si is used mainly
 npn is most popular
Typical npn Transistor Parameters

Region VBE (V) VCE (V) Current

Relation
Cutoff < 0.6 Open IB=IC=0
circuit
Active 0.6-0.7 > 0.8 IC =hFEIB

Saturation 0.7-0.8 0.2 IB ≥IC/hFE

Transistor-Transistor Logic (TTL)
 The original basic TTL gate was a slight improvement over the
DTL gate.
 There are several TTL subfamilies or series of the TTL technology.
 Has a number start with 74 and follows with a suffix that
identifies the series type, e.g 7404, 74S86, 74ALS161.
 There are many versions or families of TTL

 Standard TTL.

 High Speed TTL

 Low Power TTL.

 Schhottky TTL.
 As such all the families of TTL have three configuration for outputs.

 Totem - Pole output.

 Open Collector Output.

 Tristate Output.
 TTL is slight improvement over the DTL.
 The standard TTL gate was constructed with different resistor
values to produce gates with lower dissipation or higher speed.
 The propagation delay of a saturated logic family depends on
largely two factors: Storage Time and RC time constants.
 Reducing the ST decreases the PD.
 Reducing resistor values in the circuit reduces the RC time
constants and decreases PD.
 The trade off is a higher power dissipation because lower
resistances draw more current from the power supply.
 Speed of gate is inversely proportional to PD.
 In the low power TTL gate the resistor values are higher than in
the standard gate to reduce the Power dissipation, but PD is
increased.
 In the high-speed TTL gate, resistor values are lowered to reduce
the PD, but the power dissipation is increased.
 The Schottky TTL removes the storage time of transistor by
preventing them from going into saturation, which increases the
speed without increasing the power dissipation .
 The low-power Schottky TTL scarifies some speed for reduced
power dissipation.
 It is about equal to standard TTL in PD but has only one-fifth
the power dissipation.
 It has the best speed-power product.
Open-collector TTL Gate
 Modified circuit of DTL gate.
 Multiple emitters in transistor Q1 are connected to the
inputs.
 The voltage levels for the circuit are 0.2 V for the low
level and from 2.4 to 5 V for the high level.
 The basic circuit is a NAND gate.
Wired-AND of Two Open-Collector
TTL Gate with Totem-Pole Output
Schottky TTL Gate
Three-state TTL Gate
Transistor-Transistor Logic Families
 Transistor-Transistor Logic Families:
 74L Low power
 74H High speed
 74S Schottky
 74LS Low power Schottky
 74AS Advanced Schottky
 74ALS Advance Low power Schottky
 TTL Subfamilies

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Comparison of Logic Families