R
DCM Primitive
Table 3-7: DCM Attributes (Cont’d)
Attribute Allowable Settings and Description
DESKEW_ADJUST Controls the clock delay alignment between the FPGA clock input pin and the
DCM output clocks. See “Skew Adjustment.”
SYSTEM_SYNCHRONOUS Default. All devices clocked by a common,
system-wide clock source.
SOURCE_SYNCHRONOUS Clock is provided by the data source, i.e.,
source-synchronous applications.
Do not use this setting to phase shift DCM clock outputs. Instead, use the
CLKOUT_PHASE_SHIFT and PHASE_SHIFT constraints to achieve accurate
phase shifting.
DFS_FREQUENCY_MODE Spartan-3 FPGA Family Only. Specifies the allowable frequency range for the
CLKFX and CLKFX180 output clocks from the DCM’s Digital Frequency
Synthesizer (DFS). If any DLL clock outputs are used, then the more restrictive
DLL_FREQUENCY_MODE limits the CLKIN input frequency.
LOW Default. The DFS function unit operates in its low-frequency mode.
The frequency for the CLKFX and CLKFX180 outputs must fall
within the low-frequency DFS limits specified in the Spartan-3
FPGA Data Sheet. The frequency limits for the CLKIN input
depend on if any DLL clock outputs are used.
HIGH The DFS function unit operates in its high-frequency mode. The
frequency for the CLKFX and CLKFX180 outputs must fall within
the high-frequency DFS limits specified in the Spartan-3 FPGA Data
Sheet. The frequency limits for the CLKIN input depend on if any
DLL clock outputs are used.
STARTUP_WAIT Controls whether the FPGA configuration signal DONE waits for the DCM to
assert its LOCKED signal before going High.
FALSE Default. DONE is asserted at the end of configuration without
waiting for the DCM to assert LOCKED.
TRUE The DONE signal does not go High until the LOCKED signal goes
HIGH on the associated DCM. STARTUP_WAIT does not prevent
LOCKED from going High. The FPGA startup sequence must also
be modified to insert a LCK (lock) cycle before the postponed cycle
(see “Bitstream Generation Settings”). Either the DONE cycle or
GWE cycle are typical choices.
If more than one DCM is so configured, the FPGA waits until all DCMs are
locked.
Spartan-3 Generation FPGA User Guide www.xilinx.com 79
UG331 (v1.8) June 13, 2011
