R
Clock Buffers/Multiplexers
• The current clock is CLK0.
• S is activated High.
• If CLK0 is currently High, the multiplexer waits for CLK0 to go Low.
• Once CLK0 is Low, the multiplexer output stays Low until CLK1 transitions High to
Low.
• When CLK1 transitions from High to Low, the output switches to CLK1.
• No glitches or short pulses can appear on the output.
Using Clock Buffers/Multiplexers in a Design
Most synthesis tools infer clock buffers on the highest fanout clock nets, especially if they
have inputs in the top-level design. If there are more clocks than buffers, the most-utilized
clocks get priority for the buffers. The library components are used to specify the buffers
explicitly or to use the multiplexer functionality.
BUFGMUX and BUFGMUX_1
BUFGMUX and BUFGMUX_1 are distinguished by which state the output assumes when
it switches between clocks in response to a change in its select input. BUFGMUX assumes
output state 0 and BUFGMUX_1 assumes output state 1.
BUFG
The BUFGMUX is the physical clock buffer in the device, but it can be used as a simple
single-input clock buffer. The BUFG clock buffer primitive (see Figure 2-7) drives a single
clock signal onto the clock network and is essentially the same element as a BUFGMUX,
just without the clock select mechanism. BUFG is the generic primitive for clock buffers
across multiple architectures.
BUFG
I O
UG331_c4_06_080906
Figure 2-7: BUFG Component
The BUFG is built from the BUFGMUX as shown in Figure 2-8.
I0
O
I1
S
UG331_c4_07_011008
Figure 2-8: BUFG Built from BUFGMUX
The dedicated zero on the select line is actually implemented with a dedicated VCC source
and using the programmable polarity on the S input.
Spartan-3 Generation FPGA User Guide www.xilinx.com 55
UG331 (v1.8) June 13, 2011
