1 /**

2 * @file xmc1_eru_map.h
3 * @date 2015-02-20
4 *
5 * @cond
6
*************************************************************************************
********************************
7 * XMClib v2.0.0 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list
of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the
distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be
used to endorse or promote
22 * products derived from this software without specific prior written
permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share
modifications, enhancements or bug fixes with
33 * Infineon Technologies AG
dave@infineon.com).
34
*************************************************************************************
********************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial version
41 *
42 * @endcond
43 */
44 #ifndef XMC1_ERU_MAP_H
45 #define XMC1_ERU_MAP_H
46
47 /*************************************************************************************
********************************
48 * MACROS
49
*************************************************************************************
********************************/
50 #define ERU0_ETL0 XMC_ERU0, 0
51 #define ERU0_ETL1 XMC_ERU0, 1
 52 #define ERU0_ETL2 XMC_ERU0, 2
53 #define ERU0_ETL3 XMC_ERU0, 3
54
55 #define ERU0_OGU0 XMC_ERU0, 0
56 #define ERU0_OGU1 XMC_ERU0, 1
57 #define ERU0_OGU2 XMC_ERU0, 2
58 #define ERU0_OGU3 XMC_ERU0, 3
59
60 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN24)
61 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
62 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
63 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
64 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
65 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
66 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
67 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
68 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
69 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
70
71 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
72 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
73 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
74 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
75 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
76 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
77 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
78 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
79 #endif
80
81
82 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == VQFN40)
83 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
84 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
85 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
86 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
87 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
88 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
89 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
90 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
91 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
92 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
93 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
94 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
95
96 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
97 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
98 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
99 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
100 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
101 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
102 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
103 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
104 #endif
105
106
107 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP16)
108 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
109 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
110 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
111 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
112 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
113 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
114 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
115
116 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
117 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
118 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
119 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
120 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
121 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
122 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
123 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
124 #endif
125
126
127 #if (UC_DEVICE == XMC1100) && (UC_PACKAGE == TSSOP38)
128 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
129 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
130 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
131 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
132 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
133 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
134 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
135 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
136 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
137 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
138 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
139 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
140
141 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
142 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
143 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
144 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
145 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
146 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
147 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
148 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
149 #endif
150
151
152 #if (UC_DEVICE == XMC1200) && (UC_PACKAGE == TSSOP38)
153 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
154 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
155 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
156 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
157 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
158 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
159 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
160 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
161 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
162 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
163 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
164 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
165 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
166 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
167 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
168 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
169 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
170 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
171 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
172 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
173 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
174 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
175 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
176 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
177 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
178 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
179 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
180 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
181 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
182 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
183 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
184 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
185
186 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
187 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
188 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
189 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
190 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
191 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
192 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
193 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
194 #endif
195
196
197 #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == VQFN40)
198 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
199 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
200 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
201 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
202 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
203 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
204 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
205 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
206 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
207 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
208 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
209 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
210 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
211 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
212 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
213 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
214 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
215 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
216 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
217 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
218 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
219 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
220 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
221 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
222 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
223 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
224 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
225 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
226 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
227
228 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
229 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
230 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
231 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
232 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
233 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
234 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
235 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
236 #endif
237
238
239 #if (UC_DEVICE == XMC1201) && (UC_PACKAGE == TSSOP38)
240 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
241 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
242 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
243 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
244 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
245 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
246 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
247 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
248 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
249 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
250 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
251 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
252 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
253 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
254 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
255 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
256 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
257 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
258 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
259 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
260 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
261 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
262 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
263 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
264 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
265 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
266 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
267 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
268 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
269
270 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
271 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
272 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
273 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
274 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
275 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
276 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
277 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
278 #endif
279
280
281 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN24)
282 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
283 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
284 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
285 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
286 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
287 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
288 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
289 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
290 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
291 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
292 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
293 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
294 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
295 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
296 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
297 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
298 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
299 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
300 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
301 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
302 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
303 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
304 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
305 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
306 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
307 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
308 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
309 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
310 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
311
312 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
313 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
314 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
315 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
316 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
317 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
318 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
319 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
320 #endif
321
322
323 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == VQFN40)
324 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
325 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
326 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
327 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
328 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
329 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
330 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
331 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
332 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
333 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
334 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
335 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
336 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
337 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
338 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
339 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
340 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
341 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
342 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
343 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
344 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
345 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
346 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
347 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
348 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
349 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
350 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
351 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
352 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
353 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
354 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
355 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
356
357 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
358 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
359 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
360 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
361 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
362 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
363 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
364 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
365 #endif
366
367
368 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP16)
369 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
370 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
371 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
372 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
373 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
374 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
375 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
376 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
377 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
378 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
379 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
380 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
381 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
382 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
383 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
384 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
385 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
386 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
387 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
388 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
389 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
390 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
391 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
392 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
393 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
394 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
395
396 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
397 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
398 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
399 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
400 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
401 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
402 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
403 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
404 #endif
405
406
407 #if (UC_DEVICE == XMC1202) && (UC_PACKAGE == TSSOP28)
408 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
409 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
410 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
411 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
412 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
413 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
414 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
415 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
416 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
417 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
418 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
419 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
420 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
421 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
422 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
423 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
424 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
425 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
426 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
427 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
428 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
429 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
430 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
431 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
432 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
433 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
434 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
435 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
436 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
437 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
438
439 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
440 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
441 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
442 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
443 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
444 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
445 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
446 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
447 #endif
448
449
450 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN24)
451 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
452 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
453 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
454 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
455 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
456 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
457 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
458 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
459 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
460 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
461 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
462 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
463 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
464 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
465 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
466 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
467 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
468 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
469 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
470 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
471 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
472 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
473 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
474 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
475 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
476 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
477 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
478 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
479 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
480
481 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
482 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
483 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
484 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
485 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
486 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
487 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
488 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
489 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
490 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
491 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
492 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
493 #endif
494
495
496 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == VQFN40)
497 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
498 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
499 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
500 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
501 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
502 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
503 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
504 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
505 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
506 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
507 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
508 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
509 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
510 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
511 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
512 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
513 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
514 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
515 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
516 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
517 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
518 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
519 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
520 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
521 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
522 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
523 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
524 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
525 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
526 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
527 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
528 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
529
530 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
531 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
532 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
533 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
534 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
535 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
536 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
537 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
538 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
539 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
540 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
541 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
542 #endif
543
544
545 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP16)
546 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
547 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
548 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
549 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
550 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
551 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
552 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
553 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
554 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
555 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
556 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
557 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
558 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
559 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
560 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
561 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
562 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
563 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
564 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
565 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
566 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
567 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
568 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
569 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
570 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
571 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
572
573 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
574 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
575 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
576 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
577 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
578 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
579 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
580 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
581 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
582 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
583 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
584 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
585 #endif
586
587
588 #if (UC_DEVICE == XMC1301) && (UC_PACKAGE == TSSOP38)
589 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
590 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
591 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
592 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
593 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
594 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
595 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
596 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
597 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
598 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
599 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
600 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
601 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
602 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
603 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
604 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
605 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
606 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
607 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
608 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
609 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
610 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
611 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
612 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
613 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
614 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
615 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
616 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
617 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
618 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
619 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
620 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
621
622 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
623 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
624 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
625 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
626 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
627 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
628 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
629 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
630 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
631 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
632 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
633 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
634 #endif
635
636
637 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN24)
638 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
639 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
640 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
641 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
642 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
643 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
644 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
645 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
646 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
647 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
648 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
649 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
650 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
651 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
652 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
653 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
654 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
655 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
656 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
657 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
658 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
659 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
660 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
661 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
662 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
663 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
664 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
665 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
666 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
667
668 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
669 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
670 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
671 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
672 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
673 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
674 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
675 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
676 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
677 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
678 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
679 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
680 #endif
681
682
683 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == VQFN40)
684 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
685 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
686 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
687 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
688 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
689 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
690 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
691 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
692 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
693 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
694 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
695 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
696 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
697 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
698 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
699 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
700 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
701 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
702 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
703 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
704 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
705 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
706 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
707 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
708 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
709 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
710 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
711 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
712 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
713 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
714 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
715 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
716
717 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
718 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
719 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
720 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
721 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
722 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
723 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
724 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
725 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
726 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
727 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
728 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
729 #endif
730
731
732 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP16)
733 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
734 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
735 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
736 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
737 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
738 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
739 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
740 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
741 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
742 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
743 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
744 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
745 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
746 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
747 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
748 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
749 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
750 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
751 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
752 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
753 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
754 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
755 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
756 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
757 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
758 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
759
760 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
761 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
762 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
763 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
764 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
765 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
766 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
767 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
768 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
769 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
770 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
771 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
772 #endif
773
774
775 #if (UC_DEVICE == XMC1302) && (UC_PACKAGE == TSSOP38)
776 #define ERU0_ETL0_INPUTA_ACMP0_OUT XMC_ERU_ETL_INPUT_A0
777 #define ERU0_ETL0_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A2
778 #define ERU0_ETL0_INPUTA_P2_4 XMC_ERU_ETL_INPUT_A1
779 #define ERU0_ETL0_INPUTA_VADC0_G0BFLOUT0 XMC_ERU_ETL_INPUT_A3
780 #define ERU0_ETL0_INPUTB_ACMP0_OUT XMC_ERU_ETL_INPUT_B2
781 #define ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B0
782 #define ERU0_ETL0_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B1
783 #define ERU0_ETL0_INPUTB_VADC0_G1BFLOUT0 XMC_ERU_ETL_INPUT_B3
784 #define ERU0_ETL1_INPUTA_ACMP1_OUT XMC_ERU_ETL_INPUT_A0
785 #define ERU0_ETL1_INPUTA_ACMP3_OUT XMC_ERU_ETL_INPUT_A2
786 #define ERU0_ETL1_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A1
787 #define ERU0_ETL1_INPUTA_VADC0_G0BFLOUT1 XMC_ERU_ETL_INPUT_A3
788 #define ERU0_ETL1_INPUTB_ACMP1_OUT XMC_ERU_ETL_INPUT_B2
789 #define ERU0_ETL1_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0
790 #define ERU0_ETL1_INPUTB_P2_3 XMC_ERU_ETL_INPUT_B1
791 #define ERU0_ETL1_INPUTB_VADC0_G1BFLOUT1 XMC_ERU_ETL_INPUT_B3
792 #define ERU0_ETL2_INPUTA_ACMP2_OUT XMC_ERU_ETL_INPUT_A0
793 #define ERU0_ETL2_INPUTA_ACMP4_OUT XMC_ERU_ETL_INPUT_A2
794 #define ERU0_ETL2_INPUTA_P2_6 XMC_ERU_ETL_INPUT_A1
795 #define ERU0_ETL2_INPUTA_VADC0_G0BFLOUT2 XMC_ERU_ETL_INPUT_A3
796 #define ERU0_ETL2_INPUTB_ACMP2_OUT XMC_ERU_ETL_INPUT_B2
797 #define ERU0_ETL2_INPUTB_P2_10 XMC_ERU_ETL_INPUT_B0
798 #define ERU0_ETL2_INPUTB_P2_11 XMC_ERU_ETL_INPUT_B1
799 #define ERU0_ETL2_INPUTB_VADC0_G1BFLOUT2 XMC_ERU_ETL_INPUT_B3
800 #define ERU0_ETL3_INPUTA_ACMP5_OUT XMC_ERU_ETL_INPUT_A2
801 #define ERU0_ETL3_INPUTA_ACMP7_OUT XMC_ERU_ETL_INPUT_A0
802 #define ERU0_ETL3_INPUTA_P2_7 XMC_ERU_ETL_INPUT_A1
803 #define ERU0_ETL3_INPUTA_VADC0_G0BFLOUT3 XMC_ERU_ETL_INPUT_A3
804 #define ERU0_ETL3_INPUTB_ACMP6_OUT XMC_ERU_ETL_INPUT_B2
805 #define ERU0_ETL3_INPUTB_P2_8 XMC_ERU_ETL_INPUT_B1
806 #define ERU0_ETL3_INPUTB_P2_9 XMC_ERU_ETL_INPUT_B0
807 #define ERU0_ETL3_INPUTB_VADC0_G1BFLOUT3 XMC_ERU_ETL_INPUT_B3
808
809 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
810 #define ERU0_OGU0_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
811 #define ERU0_OGU0_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
812 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU40_SR1 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
813 #define ERU0_OGU1_PERIPHERAL_TRIGGER_CCU80_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
814 #define ERU0_OGU1_PERIPHERAL_TRIGGER_VADC_C0SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
815 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU40_SR2 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
816 #define ERU0_OGU2_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
817 #define ERU0_OGU2_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
818 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU40_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER1
819 #define ERU0_OGU3_PERIPHERAL_TRIGGER_CCU80_SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER3
820 #define ERU0_OGU3_PERIPHERAL_TRIGGER_VADC_C0SR3 XMC_ERU_OGU_PERIPHERAL_TRIGGER2
821 #endif
822
823 #endif /* XMC1_ERU_MAP_H */
824