NATIONAL INSTITUTE OF TECHNOLOGY,
ROURKELA
            EMBEDDED SYSTEMS
              LABORATORY
                (EE3704)
  SUBMITTED BY:
  Group 6
 121EE0551 _Dharavath Bindu Sree
 121EE0553_Dinesh Kumar Sahu
 121EE0554_Tarini Prasad Sahu
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 Objective:
 Develop RTOS with FIFO structure for signal access to realize the filters in the circuit developed
 in Task-1-2
 Software used:
           Proteus 8 Professional
           Keil uVision
           MATLAB R2018a
 Theory:
 The most used IIR filter design method uses reference analog prototype filter. It is thebest
 method to use when designing standard filters such as low-pass, high-pass, bandpass and band-
 stop filters it is important class of linear time-invariant discrete-time systems characterized by the
 general linear constant-coefficient difference equation.
 By means of Z transform it is characterized by the rational system function,
                                          H(z)=
 The filter design process starts with specifications and requirements of the desirable IIR filter. A
 type of reference analog prototype filter to be used is specified according to the specifications
 and after that everything is ready for analog prototype filter design.
 The next step in the design process is scaling of the frequency range of analog prototype filter
 into desirable frequency range. This is how an analog prototype filter is converted into an analog
 filter.
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After the analog filter is designed, it is time to go through the last step in the digital IIR filter design
process. It is conversion from analog to digital filter. The most popular and most used converting
method is the bilinear transformation method. The resulting filter, obtained in this way, is always
stable. However, instability of the resulting filter, when bilineartransformation is used, may be
caused only by the finite word-length side-effect.
Circuit:
                                          Fig 9. Circuit Diagram.
  Procedure:
      1. Initially the filter coefficients were calculated using the MATLAB filter designer toolbox.
      2. The cut-off frequency is 553Hz and the sampling frequency must be greater than the
           twice of the cut-off frequency sampling frequency=3000Hz
 The circuit is the same as the one designed in Task 1. The code has been altered to implement the
 Low-pass FIR filter.
       Fig 1: Schematic Circuit diagram of interfacing ADC and DAC with 8051 Microcontroller
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The coefficients are in the range of 0-1 so they are converted 0.8 notation of fixed precision point,
and the samples are already in 0.8 notation, so the output which is:
  Is in the form of 0.8*0.8 = 0.16, lower 8 bits are ignored; hence we are left with 0.8 output which
  is sent to the DAC
  Code:
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 Observations:
    Table-3: Table showing the Output Amplitudes of IIR filter for various Input frequencies.
    Frequency      Input Amplitude      Output Amplitude                               Gain in
                                                             Latency (ms)     Gain
       (Hz)              (V)                   (V)                                       dB
         50                4                   3.8                1.3         0.95      -0.44
       100                 4                   3.8                1.15        0.95      -0.44
       200                 4                   3.7                1.3         0.925     -0.625
       300                 4                   2.4                1.2          0.6      -4.436
       334                 4                  2.275               1.2         0.568     -4.91
       500                 4                  0.975               2.05       0.2375     -12.48
       800                 4                  0.720                -          0.180     -14.89
      1000                 4                  0.185                -          0.046    -26.744
 Results:
      Fig 10. The output at 50Hz and 2.5V Amplitude (Input in Blue and Output in yellow)
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    Fig 11. The output at 200Hz and 2.5V Amplitude (Input in Blue and Output in yellow)
    Fig 12. The output at 500Hz and 2.5V Amplitude (Input in Blue and Output in yellow)
    Fig 13. The output at 1000Hz and 2.5V Amplitude (Input in Blue and Output in yellow)
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  Problems Faced
      1. Due to the higher number of coefficients and past values of input and output that had to
          be stored, a single register bank was not enough. We had to use a second bank as well.
          This led to increased complexity of the code.
      2. Distortions were higher as compared to the FIR filter, causing problems while taking
          readings. There were especially large distortions at f = 200 Hz. Even at the other
          frequencies, the distorted sinusoids were interspersed by flat lines in between.
      3. Selection of Fs.
      4. They are harder to implement using fixed-point arithmetic.
      5. Clock frequency of ADC0808 should not be less like 2KHz,instead it should be like
          640kHz or 1MHz.
  Conclusion:
  Output filtered signal was similar to the input signal for low frequency signals and for higher
  frequency signals output amplitude is attenuated according to the frequency response.
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