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The Journal of Supercomputing (2022) 78:8056–8080

https://doi.org/10.1007/s11227-021-04247-9

Design and implementation of efficient QCA full‑adders

using fault‑tolerant majority gates

J. A. Bravo‑Montes1 · A. Martín‑Toledano1 · A. Sánchez‑Macián1 · O. Ruano1 ·

F. Garcia‑Herrero1

Accepted: 19 October 2021 / Published online: 7 January 2022

© The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature
2021

Abstract
CMOS technology is facing physical limitations in scaling the manufacturing pro-
cess. Therefore, to deepen the development of better designs in a smaller area, it
is necessary to look for other alternatives. One of the most studied approaches is
Quantum Cellular Automata (QCA). However, it has the disadvantage of its reli-
ability during the manufacturing processes, with high error rates that are difficult to
improve. To contribute to the design of more reliable operators based on this tech-
nology, new fault-tolerant full-adders are presented in this paper. The proposed solu-
tions improve area up to 57.14%, total energy dissipation up to 36.27%, and average
energy dissipation per cycle up to 36.22% compared to those previously proposed.
This reduction in power consumption is especially important to make QCA more
competitive as it has to operate in low-temperature environments.

Keywords Design · Fault-tolerant · QCADesigner · Quantum cellular automata

* F. Garcia‑Herrero
fragarh2@gmail.com
J. A. Bravo‑Montes
jbravom1@alumnos.nebrija.es
A. Martín‑Toledano
amartintoledanog@alumnos.nebrija.es
A. Sánchez‑Macián
asanchep@nebrija.es
O. Ruano
oruano@nebrija.es
1
ARIES Research Center, Universidad Antonio de Nebrija, Madrid 28049, Spain

1Vol:.(1234567890)
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1 Introduction

Moore’s law describes an exponential growth in the number of transistors per area
unit over time. However, current Complementary Metal–Oxide–Semiconduc-
tor (CMOS) technology is encountering physical limitations such as lithography,
making it difficult to reduce the area and, therefore, continue this law [1]. At this
point, it is essential to find reliable alternatives for the construction of larger cir-
cuits in a smaller area that could replace or even improve CMOS manufacturing
processes. Currently, there are several technologies whose objective is to become an
alternative.
One possible solution is Nanomagnetic Logic (NML), based on the use of nano-
magnets for the construction of circuits, whose main advantage is their high-integra-
tion density and their ability to operate at room temperature [2, 3].
Another solution is Silicon Dangling Bonds (Si-DB) based upon quantum dots
that allow the creation of ultra-low energy schemes [4, 5].
Finally, Quantum Cellular Automata (QCA), the technology that we will focus on
in this work, is an efficient process studied for almost 30 years as a possible founda-
tion for a future generation of integrated circuits. It was proposed by Lent et al. in
1993 [6] and developed in 1997 [7], and it has grown to become a relevant alterna-
tive technology [8] due to the maturity of its development kits such as QCADesigner
[9], and QCADesigner-E [10].

1.1 Related works

Due to the QCA reliability disadvantage during the manufacturing process, a fault-
tolerant full-adder using QCA technology will be introduced in this work. The
full-adder is a fundamental piece for digital processing and, therefore, for elaborat-
ing more complex circuits. Some examples of this can be seen in the creation of a
microprocessor, whose Arithmetic Logic Unit (ALU) requires an adder [11], or in
other components such as a Digital Signal Processing (DSP) [12], which contains an
adder among its basic operations. Proof of this is the numerous works where adders
are used to develop more complex circuits [13, 14]. Regarding the creation of full-
adders in QCA, other approaches have been made prioritizing speed by creating a
three-layer full-adder [15] or sacrificing the circuit’s total area in search of fault tol-
erance, with the use of five-input majority gates [16].
One of the most used full-adder architectures in the literature is [17], which was
recently improved by [18] reducing the number of cells, area, and energy dissipa-
tion. However, this design is not fault-tolerant.
The current work shows a full-adder with different protection levels partially
based on the unprotected architecture from [18] compared to the fully protected one
from [19], trying, at the same time, to limit and reduce energy overheads to improve
cooling constraints. The main contribution of this work is the generation of a set of
full-adders with different layouts and levels of protections depending on the (normal
or fault-tolerant) configuration of their majority-logic gates, with a good trade-off in

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8058 J. A. Bravo‑Montes et al.

Table 1  Comparison to existing Work Fault- Area-Power figures Delay Fault-

works tolerant tolerant
adder config.

[15] − ++ + −
[16] + + + −
[17] − +++ + −
[18] − ++++ + −
[19] + + + −
This work + ++ + ++

terms of area, delay and power consumption when comparing to previous solutions.
To the authors’ knowledge, no previous work proposes these different options that
can be used in different applications depending on the level of reliability required
by the system, and the area and power restrictions. An example of application is
approximate adders [20], used in error-tolerant applications where some accuracy
can be sacrificed to provide better circuit-based metrics.
Table 1 shows a comparison with a set of previous works that implement full-
adders. Considering those that provide fault tolerance, the proposed adder delivers
better circuit-based metrics. Additionally, a set of partial fault tolerance configura-
tions is presented, optimizing the area and layout of each one based on the required
fault-tolerant majority gates, where “+” indicates higher optimization and “-” less
optimized.
The paper’s organization is the following: Sect. 2 describes the different elements
that make up the QCA technology, progressing from a basic circuit to a fault-toler-
ant full-adder. Section 3 shows the proposed solution for the fault-tolerant full-adder
explaining its architecture and the differences concerning the reference model [19].
Section 4 shows the results obtained and finally, Sect. 5 concludes the paper.

2 Background

To understand QCA technology, it is necessary to know the basic components: cells,

wires, inverters, majority gates, logic gates, clocks, full-adders, and fault-tolerant
design. These are detailed in the following subsections.

2.1 Cells

The main unit of this technology is the cell. Each one is made up of four quantum
dots (semiconductor nanostructure that confines the movement of electrons) and two
electrons that can be positioned on the two diagonals; thanks to the opening of the
existing potential barrier and the Coulomb repulsion between the electrons [21].
In this way, the cell is in the +1 or −1 polarization state, representing a logical 1
or 0, respectively, as shown in Fig. 1.

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Fig. 1  QCA Cells [22]

Fig. 2  Simple Wire [23]

Fig. 3  45o Wire [23]

Fig. 4  Inverter [23]

2.2 Wire

Thanks to the Coulomb repulsion, the proximity between cells causes them to be
affected by the other cells’ state. In this way, a cell could be set as input waiting
for a value, and that state could be transmitted to other areas of the circuit. This
can be done in two different ways due to the cells’ placement, showing two differ-
ent behaviors depending on whether the cells are positioned normally or rotated
45o.
This can be seen in Fig. 2, which shows a simple wire that would behave like
CMOS connections. Also, Fig. 3 shows how the quantum dots are rotated 45o ,
which causes the data transmission to vary. Due to Coulomb repulsion, the value
would change from 1 to 0 as it progresses through the wire. These changes could
result in the effect that, if the wire is composed of an input cell, an output cell,
and an intermediate n cells, if n is odd, the input and output will be the same,
while if it is even, the result will be the opposite of the input.

2.3 Inverter

Due to these characteristics, an inverter can be made very easily. Figure 4 shows
the simplest example to implement.
It has an input where the value to be inverted will be inserted and an output
where the operation’s result will be checked. However, instead of being a straight
wire, the last three cells are set down in one position. When reaching the point

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8060 J. A. Bravo‑Montes et al.

Fig. 5  Majority Gate [18]

Fig. 6  Logic gate AND [24]

where the third cell value must pass to the fourth, it changes the polarization to
the opposite, obtaining the expected result in the output cell.

2.4 Majority gate

The majority gate is one of the main tools for creating logic circuits [18]. Knowing
the properties of this element, it can be modified to achieve the basic logic gates,
i.e., AND, OR, etc. Given three inputs, these propagate to the central cell, which
will take the most repeated polarization and be transmitted to the output.
The example in Fig. 5 shows a majority gate with three inputs and one output,
in which the desired inputs (A, B, C) will be set, and the expected value will be
observed at the output. Following the majority gate function:
M(A, B, C) = AB + AC + BC.

2.5 Logic gates

Majority gate’s structure can be manipulated to create the AND and OR logic gates
[24].
Figure 6 shows how the AND logic gate is formed. To achieve this behavior,
one of the three entries of the majority gate would have to be set to −1. Due to

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Fig. 7  Logic gate OR [24]

this, we can alter the function described by the majority gate since the input pre-
viously called C would be replaced by −1. Applying Boolean logic, this logic
gate would be described by the following function M(A, B, -1) = AB . That is
the same as the AND logic gate. Similarly, in Fig. 7, the third input is set to
+1 to achieve an OR logic gate’s behavior. Resulting in the following equation:
M(A, B, 1) = A + B.

2.6 QCA clock

QCA has a multiphase clock [21]. This allows multi-stage synchronization to be per-
formed. It has four clocks, each one of them shifted in phase by 90o to the previous
one, giving the possibility of crossing wires in opposing clocks without influencing
each other.
In this way, if two wires are to be crossed, they are in zones 0 and 2 or 1 and 3, it
can be done without the values transmitted by one wire affecting those of the other
wire [25]. Due to this, it is possible to create larger circuits in a smaller area.
As can be seen in Figs. 8 and 9, there are two opposing phases, while one is in the
“release phase,” the other one is in the “switch phase,” and while the first one is in
the relax phase, the other one is in the hold phase, and vice versa. A clock cycle is
completed when a clock zone passes through four different phases.

2.7 Full‑adder

As can be seen in Fig. 10, the QCADesigner tool has been used for the implementa-
tion of a full-adder from [17].
The full-adder has A and B which are the two one-bit inputs and Cin is the carry
input. On the other hand, Sum and Cout correspond to the two outputs that provide
the result of the addition and the carry, respectively. This circuit consists of 44 QCA
cells. The circuit is delimited by clock zones that are reflected in the different colors
of the cells that make up the circuit.
For this full-adder, four clock zones have been used following a grayscale that
represents the clock zones from 0 to 3 as shown in Fig. 11.

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8062 J. A. Bravo‑Montes et al.

Fig. 8  Clock zones [21]

Fig. 9  Clock phases [21]

2.8 Fault‑tolerant design QCA

The majority gates are the critical points where a small error can produce erratic
behavior of the circuit as demonstrated in [19]. For this reason, it has been proposed
to replace all simple majority gates with others with a larger area but greater reli-
ability, exposed in the same reference document.
The structure implemented in the majority gate is equivalent to a traditional one
detailed in Sect. 2. For the fault tolerance analysis, different errors were taken into
account in [19], such as single-cell omission, extra-cell deposition, and cell mis-
alignment were investigated using QCADesigner 2.0.3. The results obtained were
100% tolerant against a single-cell omission defect and 90% fault-tolerant against an
extra-cell deposition defect [19].

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Fig. 10  Full-Adder from [17]

Fig. 11  Clock zones key

This fault-tolerant majority gate has a total of 10 cells (seven normal cells and
three rotated cells) and overcomes the error caused by cell omission, extra-cell dep-
osition, and cell displacement defects [19].
In particular, the proposal improved above the previous ones in single-cell omis-
sion, double-cell omission, triple-cell omission, quadruple-cell omission, extra-cell,
and deposition permissible cell displacement defects.
This structure has been chosen as a reference for this paper after evaluating differ-
ent majority gates [26–33] since it is optimal in terms of the number of cells, area,
latency, cell displacement defects, and energy consumption.
Table 21 shows a comparison between a majority gate [18] and a fault-tolerant
one such as the one in Fig. 12. As can be seen, the greater the number of cells used,
the higher the area and energy dissipation are.

1
To obtain the results, QCADesigner has been used. The QCADesigner-E (QD-E) is an extension of the
QCADesigner. It calculates the estimation of the power dissipation of QCA circuits. It is integrated as an
additional simulation module that is based on the Coherence Vector Simulation (CVSE) [9, 10]

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8064 J. A. Bravo‑Montes et al.

Fig. 12  Fault-Tolerant Majority

Gate [19]

Table 2  Majority Gate Majority Gate Fault-Tolerant

Comparison from [18] Majority Gate
from [19]

Num Cells 5 10
Area ( )
𝜇m2 0.01 0.02
Total Energy Dissipation (eV) 2.59−3 6.82−04
Average Energy Dissipation 2.36−04 6.20−05
per Cycle (eV)

Fig. 13  QCA design (left) vs architectural diagram (right)

3 Proposed solution

This work introduces a new fault-tolerant full-adder architecture. However, the solu-
tions provided in this section can be applied to any full-adder with a different degree
of protection against errors, obtaining improvements in area and power consumption
without raising latency compared to the state of the art. In Fig. 13, we include the

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architectural diagram of the proposal. As it can be seen, the full-adder is built of

inverters (NOT) and majority gates (MLG). As we explained, majority gates are the
main source of error, for this reason in this work, we will exchange the MLG blocks
by its fault-tolerant implementations and we will provide customized solutions for
different combinations of protected and unprotected MLG blocks, providing design-
ers with a wide and optimized catalog of adders with different levels of reliability,
area consumption, energy dissipation and latency, depending on their needs.
In the following subsections, the parameters that have been taken into account
for the proposed full-adder architecture design will be exposed. Later, the general
and specific differences between both the existing architectures and the full-adders
described here will be presented.

3.1 Architecture design criteria

For the proposed full-adders, parameters such as area, energy dissipation, latency,
and connection with external circuits have been considered. Next, a brief explana-
tion of each of these factors and how they directly affect the proposed full-adder
architecture is included.

3.1.1 Area

To optimize the area, it has been necessary to reduce the number of cells used in the
circuit, reducing the wires’ length. On the other hand, the crossover of wires imple-
mented within the circuit itself allows us to avoid using a large number of cells by
having to surround the entire circuit, especially when it is necessary to use the same
input of the full-adder proposed in different majority gates. With this idea in mind, it
has been possible to considerably reduce the number of cells used in the circuit and
thus reduce the proposed full-adder’s total area.

3.1.2 Energy dissipation

This parameter directly depends on the total area of the circuit. For this reason, by
reducing the size of the proposed full-adder, energy dissipation is improved as well.
However, it is also important to take into account the number of clocks implemented
in the circuit. Due to this, the transitions in a wire have been optimized using differ-
ent clocks, thus achieving a direct reduction in energy dissipation.

3.1.3 Latency

Another critical factor that has been taken into account is latency. One of the main
challenges in the design of the proposed full-adder is to maintain the same latency
as the original one. This has been achieved thanks to the wire crossover within the
proposed full-adder, obtaining a circuit of equal latency and area reduction.

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3.1.4 Input and output connection to external circuits

Finally, it has been taken into account that the inputs and outputs must be easy
to connect to other independent circuits. To achieve this, it was necessary to
consider that both the three inputs and the two outputs must be located in the
borders, thus providing the possibility of connection with the pinout of different
circuits.

3.2 Reference architectures

The reference architectures used in this paper are the unprotected full-adder of
[18] and the fault-tolerant full-adder of [19] in Fig. 16.
We define three different zones related to the three majority gates involved in
the design. To provide flexibility with the level of protection against errors, we
analyze all the possible comparisons using majority gates or fault-tolerant major-
ity gates.
The proposed full-adder offers a flexible implementation that allows configur-
ing the degree of protection to apply to a circuit. As it is demonstrated in [19], the
majority gates are the critical points and main source of errors in QCA designs,
where a small error can produce erratic behavior of the circuit. For this reason,
increasing the level of fault-tolerant majority gates increases the reliability of
the whole logic unit, at a cost of a larger area, compared to unprotected major-
ity gates. This proposal is intended for architectures that do not need total pro-
tection but where partial protection is enough to satisfy their goals, as there are
other secondary sources of error apart from the majority gates. An example is the
approximate adders that are architectures implemented for image processing [20].
To name the different architectures, a three-letter code is used, one letter for
each zone. If the majority gate of a specific zone is not protected is represented
with U (Unprotected) in the corresponding letter and with P (Protected) if it is
fault-tolerant. Hence, the unprotected full-adder will be represented by the code
UUU​, and PPP is the code for the fully protected circuit.
To compare the rest of the semi-protected architectures, despite not being
found in the original article [19], the circuits that would correspond to the litera-
ture (UUP in Fig. 18, UPU in Fig. 20, UPP in Fig. 14, PUU in Fig. 22, PUP in
Fig. 24, PPU in Fig. 26) have been generated.

3.3 Proposed architectures

The architectures proposed to compare with work [19] and its semi-protected rep-
resentations are UUP in Fig. 19, UPU in Fig. 21, UPP in Fig. 15, PUU in Fig. 23,
PUP in Fig. 25, PPU in Fig. 27, and PPP in Fig. 17.
The development of the UUP, UPU, and UPP designs has used the UUU circuit
of [18] as a reference. However, the rest of the circuits (PUU, PUP, PPU, PPP)

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Fig. 14  Full-Adder UPP from [19]

Fig. 15  Proposed Full-Adder UPP

have been created specifically for this paper to provide better results in terms of
overhead reduction.
Models are compared below to show the differences between the circuit from
[19] and the proposed architecture.

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8068 J. A. Bravo‑Montes et al.

Fig. 16  Full-Adder PPP from [19]

Fig. 17  Proposed Full-Adder

PPP

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Fig. 18  Full-Adder UUP from [19]

Fig. 19  Proposed Full-Adder

UUP

A particular focus has been set on UPP and PPP architectures due to UPP
being the circuit in which the highest percentage of energy dissipation improve-
ment has been achieved and PPP architecture being the design most protected
against failures.

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Fig. 20  Full-Adder UPU from [19]

Fig. 21  Proposed Full-Adder UPU

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Fig. 22  Full-Adder PUU from [19]

Fig. 23  Proposed Full-Adder

PUU

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8072 J. A. Bravo‑Montes et al.

Fig. 24  Full-Adder PUP from

[19]

Fig. 25  Proposed Full-Adder

PUP

3.3.1 Architecture UPP

Figure 14 corresponds to the full-adder from [19] with two fault-tolerant major-
ity gates implemented in zones 2 and 3. The proposed full-adder with the same
protection can be found in Fig. 15 where it can be seen that the inputs of the

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Fig. 26  Full-Adder PPU from [19]

Fig. 27  Proposed Full-Adder

PPU

majority gate of zone 2 have been redistributed to take advantage of the area in
an optimal way. It can also be seen that, by distributing the regions in which the
majority gates are found in a descending way, it is possible to reduce the total

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8074 J. A. Bravo‑Montes et al.

Table 3  fault-tolerant full-adders with different protection levels compared to full-adder from [19] and
[32]
Faul-Tolerant Protection UUP UPU UPP PUU PUP PPU PPP

Num cells [19] 87 90 90 102 102 102 102

[32] 72 73 78 80 85 91 92
Proposed 58 61 63 66 76 69 72
Area (𝜇m2) [19] 0.11 0.11 0.11 0.14 0.14 0.14 0.13
[32] 0.06 0.06 0.07 0.08 0.08 0.09 0.08
Proposed 0.07 0.06 0.07 0.06 0.08 0.07 0.08
Total Energy [19] 2.2−2 2.6−2 2.0−2 2.8−2 2.2−2 2.6−2 1.9−2
Dissipation (eV) [32] 2.4−2 2.3−2 2.2−2 2.8−2 2.9−2 2.9−2 2.9−2
Proposed 2.0−2 1.7−2 1.3−2 2.4−2 2.1−2 2.4−2 1.6−2
Average Energy [19] 2.0−3 2.3−3 1.8−3 2.5−3 2.0−3 2.3−3 1.7−3
Dissipation (eV) [32] 2.2−3 2.1−3 2.0−3 2.5−3 2.6−3 2.6−3 2.6−3
Proposed 1.8−3 1.5−3 1.1−3 2.1−3 1.9−3 2.2−3 1.5−3

area of the circuit even more, resulting in a more compact full-adder with a cer-
tain level of protection.

3.3.2 Architecture PPP

To make a comparison of the fully protected version of the full-adder from [19] and
the proposed protected full-adder, the fault-tolerant majority gates have been imple-
mented in all the three zones, as can be seen in Figs. 16 and 17, respectively.
The main difference between both approaches is the distribution of the majority
gates. The majority gates in zones 1 and 2 are redistributed in Fig. 17, reducing the
number of cells in the circuit. In zone 3, the majority gate corresponding to Fig. 12
is also implemented in Fig. 17.
Finally, the clock zones in the full-adder from [19] are distributed as follows:
clock 1 (zone 1), clock 2 (zone 2) and clock 3 (zone 3), as can be seen in Fig. 16.
The proposed full-adder has the following distribution: clock 0 (zone 1), clock 2
(zone 2) and clock 3 (zone 3). This change allows clock 1 only to be used for clock
transitions in a wire, as shown in Fig. 17, impacting power consumption.

3.3.3 Semi‑protected architectures

The architectures that can be implemented according to the desired level of protec-
tion are described as follows. The following figures can be seen in the rest of the
designs: UUP, UPU, PUU, PUP, and PPU. First, it was necessary to modify the ref-
erence architecture (PPP) from [19] to create and simulate the different partially pro-
tected reference designs. Subsequently, an architecture with partial protection was
designed for each of the cases mentioned above. Reference and proposed designs
have been compared to obtain the values in terms of number of cells, area, total
energy dissipation, and average energy dissipation per cycle, which can be seen in

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Table 4  improvement percentages of fault-tolerant full-adders with different protection levels compared
to full-adder from [19]
Faul-Tolerant Protection UUP UPU UPP PUU PUP PPU PPP

Reduction of num cells % 33.33 32.22 30.00 35.29 25.49 32.35 29.41
Reduction of area (𝜇m2) % 36.36 45.45 36.36 57.14 42.85 50.00 38.46
Reduction of total 6.36 33.33 36.27 15.79 7.05 6.54 14.36
energy dissipation (eV) %
Reduction of average 6.50 33.61 36.22 15.83 7.25 6.36 14.12
energy dissipation
per Cycle (eV) %

Table 5  Latency values of Faul-Tolerant Pro- UUP UPU UPP PUU PUP PPU PPP
fault-tolerant full-adders with tection
different protection levels
compared to full-adder from Latency [19] 4 4 4 4 4 4 4
[19]
This work 4 4 4 4 4 4 4

Table 3. In addition, the two architectures that can be found in the literature with a
better trade-off between the number of cells, area, and energy dissipation are also
included in the table for comparison purposes. For the sake of simplicity, we only
analyze in the text the metrics of [19], as it is the most efficient. Similar conclusions
can be reached with [32].

4 Results

The results obtained after simulating all the possible levels of protection against
errors allow us to observe that the proposed architectures improve in the number
of cells, area, total energy dissipation, and average energy dissipation per cycle,
compared to the protected full-added from [19] and the derived semi-protected
architectures.
To compare each combination’s values, it has been necessary to perform 14 simu-
lations (7 simulations with the adapted architectures from [19] and 7 simulations of
the proposed full-adders).2
Table 4 shows the percentage of improvement obtained with our proposal com-
pared to the fault-tolerant full-adder of [19]. The margin for improvement of each
parameter is as follows: the number of cells from 25.49% in version PUP to 35.29%
in version PUU, area from 36.36% in version UUP and UPP to 57.14% in PUU, total

2
Note that, comparisons to CMOS technology are omitted as it is outside of this work’s scope and is
already analyzed in the literature by other authors.

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8076 J. A. Bravo‑Montes et al.

Fig. 28  Thermal energy dis-

sipation maps for the full-adder
UUU from [19]

Fig. 29  Thermal energy dis-

sipation maps for the proposed
fault-tolerant full-adder PPP

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Design and implementation of efficient QCA full‑adders using… 8077

Fig. 30  Thermal energy dissipation maps for the fault-tolerant full-adder PPP from [19]

energy dissipation from 6.36% in version UUP to 36.27% in UPP and the average
energy dissipation per cycle from 6.36% in combination PPU to 36.22% in UPP.
Table 5 shows that latency is the same for all the designs, so the area and power
savings do not penalize speed.
Next, we include the thermal energy dissipation maps in Figs.28, 29 and 30,
obtained with QCADesigner for the standard full-adder (unprotected), the fault-tol-
erant proposal with complete protection (PPP), and the reference proposed in the
literature also for the fault-toleration version (PPP). As it can be seen for the regu-
lar full-adder, there are five critical cells from a thermal energy dissipation point of
view (red cells), for the fault-tolerant proposal with complete protection (PPP) the
number of critical cells (between red and dark orange cells) increase to eight, which
is coherent with the increase in cells. The same happens with the reference proposed
in the literature, as it has a larger number of cells, it has a larger number of critical
cells as well, about thirteen (between red and dark orange cells).

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8078 J. A. Bravo‑Montes et al.

Finally, to analyze the robustness of the proposed architectures, we simulated the

errors of single-cell omission, extra-cell deposition, and cell displacement defects in
the fault-tolerant majority gates integrated in the different designs obtaining: 100%
tolerance against the single-cell omission error, 100% tolerance against extra-cell
deposition error and 100% tolerance with cell displacement smaller than 7nm north,
5nm south, and 6nm east and west.

5 Conclusion

This paper introduces efficient full-adder architecture designs with different degrees
of fault-tolerant protection. The architectures described here go from a design in
which all the majority logic gates are fault-tolerant, which is the most robust solu-
tion, to a design in which just one gate is protected. This flexibility will allow other
designers to choose an adder based on the trade-off between reliability and area/
energy dissipation, which can be useful in larger QCA circuits that do not require
full accuracy in their results or need larger protection for certain bits. All the archi-
tectures included here are based on full-custom designs validated with QCADe-
signer. Results show an area improvement between 36.36% and 57.14%, with a total
energy dissipation between 6.36% and 36.27%, average energy dissipation per cycle
between 6.56% and 36.22% compared to previous works found in the literature. As
this circuit is widely used in digital processing, all the savings introduced here will
have a greater impact on other structures such as ALUs or DSPs designed with QCA
especially in applications that need different levels of reliability in their processing.

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Publisher’s Note Springer Nature remains neutral with regard to jurisdictional claims in published
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1264 Khajehnasir-Jahromi et al. / Front Inform Technol Electron Eng 2022 23(8):1264-1276

Frontiers of Information Technology & Electronic Engineering

www.jzus.zju.edu.cn; engineering.cae.cn; www.springerlink.com
ISSN 2095-9184 (print); ISSN 2095-9230 (online)
E-mail: jzus@zju.edu.cn

Introducing scalable 1-bit full adders for designing

quantum-dot cellular automata arithmetic circuits

Hamideh KHAJEHNASIR-JAHROMI, Pooya TORKZADEH‡, Massoud DOUSTI

Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran 1477893855, Iran
E-mail: h.khajehnasir@srbiau.ac.ir; p-torkzadeh@srbiau.ac.ir; m_dousti@srbiau.ac.ir
Received June 17, 2021; Revision accepted Sept. 30, 2021; Crosschecked Jan. 28, 2022

Abstract: Designing logic circuits using complementary metal-oxide-semiconductor (CMOS) technology at the nano scale has
been faced with various challenges recently. Undesirable leakage currents, the short-effect channel, and high energy dissipation
are some of the concerns. Quantum-dot cellular automata (QCA) represent an appropriate alternative for possible CMOS
replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS. The key point
of designing arithmetic circuits is based on the structure of a 1-bit full adder. A low-complexity full adder block is beneficial for
developing various intricate structures. This paper represents scalable 1-bit QCA full adder structures based on cell interaction.
Our proposed full adders encompass preference aspects of QCA design, such as a low number of cells used, low latency, and
small area occupation. Also, the proposed structures have been expanded to larger circuits, including a 4-bit ripple carry adder
(RCA), a 4-bit ripple borrow subtractor (RBS), an add/sub circuit, and a 2-bit array multiplier. All designs were simulated and
verified using QCA Designer-E version 2.2. This tool can estimate the energy dissipation as well as evaluate the performance of the
circuits. Simulation results showed that the proposed designs are efficient in complexity, area, latency, cost, and energy dissipation.

Key words: Quantum-dot cellular automata (QCA); Full adder; Ripple carry adder (RCA); Add/sub circuit; Multiplier
https://doi.org/10.1631/FITEE.2100287 CLC number: TN79

1 Introduction Quantum-dot cellular automata (QCA) are well-

known. Their remarkable energy consumption com‐
Nanotechnology has made a lot of progress in the pared to the standard CMOS is of great interest (Das
field of integrated circuit fabrication. Many innovative and De, 2017). QCA circuits consist of some cells
methods and technologies have been engendered. All containing four quantum dots with a pair of electrons
have specific advantages (Song et al., 2020). The pro‐ (Lent et al., 1993). The electrons in a single cell
cess of scaling down the feature size of transistors in circulate quickly through the dots. According to the
standard complementary metal-oxide-semiconductor Coulomb repulsion between these charges, the QCA
(CMOS) technology has become more arduous in the cell can be polarized to two values (P=+1 and P=−1).
last few years. Deep sub-micron undesirable responses The cell polarization P=+1 is encoded as binary 1
in CMOS make alternative solutions more attractive (logic 1) and P= − 1 is encoded as binary 0 (logic 0)
(Navidi et al., 2021). (Cesar et al., 2020).
Data transfer in QCA is the responsibility of the
‡
Corresponding author
clock. The clocking scheme includes four clock signals,
ORCID: Hamideh KHAJEHNASIR-JAHROMI, https://orcid.org/ and each consists of four phases, namely switch, hold,
0000-0003-3331-5693; Pooya TORKZADEH, https://orcid.org/0000- release, and relax (Singh et al., 2018). These four
0003-1646-7054; Massoud DOUSTI, https://orcid.org/0000-0003-2884-
7062 phases have a difference of 90° from each other. In
© Zhejiang University Press 2022 the switch phase, the potential barriers inside cells
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are raised. Thus, the cells become polarized. In the 2 Background

hold phase, the barriers are held high. Thereupon, the
cells get a determined polarization. In this case, each 2.1 QCA design basics
cell affects its neighborhoods ’ polarity. Unlike the The design of QCA circuits is based on several
switch phase, cell barriers are lowered in the release basic structures. The QCA wiring is a primary part of
phase. Therefore, in the fourth and final phase (relax), each design. By putting together multiple cells in the
the barriers are at their lowest possible level (Debnath horizontal/vertical direction, a wire will be formed.
et al., 2019). Fig. 1 shows a QCA clocking scheme. Data flows from the beginning of the wire to the end
by the interaction of adjacent cells. There are two
Hold
types of wiring, i.e., 90° and 45° (Xiao et al., 2012).
Re Clock 0
itc
h lea
se As shown in Fig. 2, the data flows the entire 90° wire
Sw Relax without changing the applied polarization at the
Hold beginning of the wire. However, the second type,
Re Clock 1
ch
Inter-dot barrier

le
Swit as
e which is known as the inverter chain, reverses the
Relax
input polarity in an even number of cells. Fig. 3 shows
Re Hold Clock 2 two ways of constructing an inverter gate.
lea ch
se
Swit
Relax

Hold P=+1 P=+1

P=+1
Re Clock 3
lea ch
se
S wit (a)
Relax (a)

Time
=+1 P=−1
Fig. 1 QCA clocking scheme P=+1 P=-1

(b)
The QCA’s superiorities are the operating speed Fig. 2 Two types of wire in QCA: (a) 90°; (b) 45°
at the order of THz, high device density, ultra-low
energy dissipation, and considerable flexibility for
scaling down the minimum cell size to the dimen‐
Output
sions of atoms (molecular implementation) (Blair,
2019).
A full adder is a rudimentary element of arith‐ Input
metic systems. Designing an optimized full adder
structure is essential for designing related intricate
circuits because full adders are used extensively in
larger circuits, such as multipliers. Also, adder and
Input Output
subtractor circuits with more entry bits need more
full adder blocks in their structures.
This paper illustrates 1-bit full adders based on
the interactions between QCA cells. The proposed Fig. 3 QCA inverter forms
full adders have low energy dissipation, low latency,
little area usage, and low complexity (small number The last basic structure is the majority gate that
of cells used) compared with existing ones. We have is indispensable in almost every QCA circuit design.
used these structures in larger circuits, including a The majority gate depicts the most applied input
4-bit ripple carry adder, a 4-bit ripple borrow sub‐ polarity in its output cell. The Boolean equation of
tractor, and an add/sub circuit. Finally, a 2-bit array the 3-input majority gate is
multiplier has been designed using the proposed adder
structure. M( A,B,C )= AB + BC + AC. (1)
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By applying a fixed polarization −1/+1 to one of 2.2 Overview of full adder designs
the majority gate ’ s inputs, the gate transforms to
The full adder is a digital arithmetic block with
AND/OR gates. Fig. 4 shows a 3-input majority gate.
three input variables (A, B, C in ) and two outputs
(Sum, Cout). The summation of input variables results
Input AA
in the outputs (Babaie et al., 2019). The Cin is quot‐
ing from the previous adder. The adder without Cin as
input is called a half adder. Output functions are
expressed by Eqs. (2) and (3), where M is the 3-input
Input BB Output majority gate. Fig. 6 shows the logical diagram of a
1-bit full adder block.

Sum = A⊕B⊕C in , (2)

Input C
C
C out = AB + C in ( A⊕B ) = M ( A,B,C in ). (3)
Fig. 4 The 3-input majority gate
A B Cinin

There are three ways to cross two separate wires. XOR Sum
The first way is to use 90° and 45° wires together,
which is called coplanar crossover. The second way
is to use more than a layer for crossing multiple Majority Cout
out
wires. This method is multi-layer crossover. The third
way is to pass two wires with a difference of two Fig. 6 Logical diagram of a 1-bit full adder block
clock zones from each other at the intersection (logical
crossover). Fig. 5 shows these three types of cross‐ A half subtractor can be constructed from a full
over in QCA designs. adder if the second operand (second input’s digits)
are inverted and the carry input is set to 1. Indeed,
the subtractor is the sum of the first operand and the
Input 2
1

Inp
second two’s-complement operand. The output func‐
t

ut
tpu

1
Ou

tion can be attained by Eq. (4):

Input 1 Output 1
-
F = A + B + 1. (4)

Ou
tpu
Various new QCA designs have been presented
t 2 for the 1-bit full adder. These designs can be classi‐
2

Output 2
ut
Inp

(a) (b) fied into single-layer and multi-layer types (Moham‐

(a) (b) madi et al., 2016; Seyedi and Navimipour, 2018;
Input 2 Input 4 Adelnia and Rezai, 2019; Heikalabad et al., 2020;
Hasani and Navimipour, 2021). Layouts are designed
in three QCA layers. Sasamal et al. (2018) and Erni‐
Input 1 Input 3 Output 3 yazov and Jeon (2019) used coplanar crossovers in
their designs plus shifted (translated) some cells hori‐
Output 1
Clock 0 Clock 1 zontally. In Ahmadpour et al. (2018) and Arani and
Clock 2 Clock 3 Rezai (2018)’ s layouts, some cells were also shifted.
Output 2 Output 4 Shifting cells horizontally/vertically in the QCA
(c) layout is not a recomended approach. It increases
Fig. 5 Three types of crossover in QCA: (a) coplanar the chance of a displacement fault. Gassoumi et al.
crossover; (b) multi-layer crossover; (c) logical crossing (2021) and Salimzadeh and Heikalabad (2021) have
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lowered the number of cells, but the simulation results electron charges of dots in a cell, and dij is the space
showed that their outputs-signal strength is weak. between these two dots. The energy must be calculated
Maharaj and Muthurathinam (2020) provided a novel for all adjacent cells. The stable state is then defined
design and used very few cells. However, the simula‐ clearly; i.e., it is the lowest summed energy obtained
tion results showed that its outputs unwantedly rise between the two output states. Fig. 8 shows two cases
and fall at some of the edges. for the output cell with different polarization. The
calculation of kink energies for both positions is tabu‐
lated in Table 1. By comparing the calculation results
3 Proposed QCA combinational logic circuits in these two cases, it can be concluded that the elec‐
trons inside the output cell will be located in position
In this section, the architecture of our proposed Fig. 8a because of the lower kink energy in contrast
structures will be clarified. All designs, including the with that of Fig. 8b. Therefore, the output cell shows
QCA layouts and inputs/outputs waveform, were vali‐ the binary value 1, which is the correct value.
dated by the QCA Designer-E version 2.2 (an exten‐ The first proposed full adder has low complexity
sion of the QCA Designer version 2.0.3 of Walus et al. and area usage. Although one of its inputs is located
(2004)). In the QCA Designer-E designs, green, purple, at the center of the circuit, it can be used in multi-layer
cyan, and white cells represent the clock zones 0, 1, 2, concepts with higher scalability and connectivity. The
and 3, respectively. The coherence vector (w/Energy) second and third proposed full adders are designed to
simulation engine was used to simulate the designs. be fully scalable. Their inputs and outputs are located
3.1 One-bit full adder around the circuit. The full adder 2 is built without
any crossover. In the following, we use these struc‐
Fig. 7 shows our low-complexity 1-bit full adder tures in more complicated circuits.
layouts. This structure is designed on a single layer.
To present a half adder using the proposed full adder, 3.2 Add/Sub circuit
the polarization of Cin must be set to −1. As Fig. 6 The add/sub circuit is a combinational logic
illustrates, our proposed full adder consists of two circuit that can sum or subtract two n-bit numbers by
gates, i.e., a majority and an XOR. Physical verifica‐ setting a value (0 or 1) for the selector pin. Fig. 9
tion has been performed to ensure the correct opera‐ shows our proposed add/sub QCA circuits. The circuit
tion of the XOR gate. For this purpose, the external is transformed to a half subtractor or a half adder by
electrostatic energies between the output cell and setting the mode (M) pin polarization to +1 or −1,
the others (kink energies) are calculated. It has been respectively.
done by applying all possible combinations of inputs
3.3 Four-bit ripple carry adder
for the XOR gate. Here, an example is offered to
illustrate that the gate works correctly. It has been The structure of the ripple carry adder is based
assumed that the polarization of inputs A, B, and Cin on cascading multiple 1-bit full adders. So, an adder
is −1, 1, and −1, respectively. The interaction between with a higher number of input bits will be acquired.
cells (kink energy) can be obtained from Eq. (5). The Cout of each full adder block is the Cin of the next
Then, the summation of kink energies (total electro‐ stage. If the Cin gets ignored at the first stage, the
static energy) UT can be achieved from Eq. (6). first full adder can be substituted with a half adder.
So, the circuit sums two 4-bit numbers and displays
1 q i q j kq i q j the summation in 5 bits. Fig. 10 shows our proposed
U ij = = , (5)
4πε 0 ε r d ij d ij 4-bit ripple carry adders.
U T = U Tx + U Ty = ∑U ix + ∑U iy .
n n
(6) 3.4 Four-bit ripple borrow subtractor
i=1 i=1
The structure base of the ripple borrow subtractor
ε0 and εr are vacuum and substance relative per‐ is the same as that of the ripple carry adder. As men‐
mittivity coefficients, respectively. qi and qj are the tioned above, a full adder block and a NOT gate are
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1268 Khajehnasir-Jahromi et al. / Front Inform Technol Electron Eng 2022 23(8):1264-1276

Fig. 7 Proposed 1-bit full adders: (a) full adder 1 QCA layout; (b) full adder 1 simulation results; (c) full adder 2 QCA
layout; (d) full adder 2 simulation results; (e) full adder 3 QCA layout; (f) full adder 3 simulation results
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(a)
(a) A=0
A=-1 its simulation results, respectively. This circuit was
e99 e10
10 e11 e12
12
designed on a single layer without any crossover.
11

e33 e44 e13

13 e14
14
4 Simulation and comparison results

B=1 e11 e55 x

e22 e66 y Out In this section, the simulation results and energy
dissipation for all proposed circuits are displayed.
e77 e88 e15
15 e16
16 Also, our proposed full adder structure is compared
with the most recent works.
e17 e18
18
4.1 Performance evaluation
17

e19
19
e20
20
Tables 2 and 3 show simulation setup parame‐
ters and performance evaluation of the proposed
Ciin=0
=-1
designs, respectively. The coherence vector (w/Energy)
(b)
(b) A=0
A=-1 simulation engine allows designers to consider their
e99 e10
10 e11
11
e12
12
system’s energy dissipation. In the software QCA
Designer-E version 2.2, Sum_bath and Avg_bath are
e33 e44 e13
the summation and average energies conceded to
13 e14
14
the bath within the complete simulation, respectively.
Sum_clk and Avg_clk are the summation and aver‐
B=1 e11 e22 e55 e66 x y Out
age energies moved to/from the clock within the
all-over simulation process, respectively (Abdullah-
e77 e88 e15
15 e16
16
Al-Shafi and Bahar, 2018). More explanations about
these energies and how they can be calculated were
e17 e18
17 18
described in Walus et al. (2004).

e19 e20
4.2 Comparison results
19 20

Ciin=0
=-1
There are two cost functions to evaluate QCA
Fig. 8 Cells polarization in a case where the inputs (A, B, designs. One of the cost metrics is based only on the
and Cin) are (−1, 1, and −1) by considering the output cell occupied area (A) and delay (T) with no consider‐
which shows 1 (a) and the output cell which shows −1 (b) ation about the number of fundamental gates (majority
and NOT gates) in the circuit. Eq. (7) shows this cost
used to construct a subtractor. Fig. 11 shows our pro‐ metric (Liu et al., 2014). The other metric is based on
posed 4-bit ripple borrow subtractors. the numbers of inverters and majority gates. The
crossover is important in this metric. Eq. (8) shows
3.5 Two-bit array multiplier
this cost metric which shows greater efficiency in QCA
An array multiplier is a combinational logic circuit designs. In this metric, M, I, and C stand for the num‐
used for multiplying two binary numbers by employ‐ bers of majority gates, inverters, and crossovers,
ing an array of AND gates and adders. Figs. 12 and 13 respectively. T indicates the delay of the circuit, and
show the proposed 2-bit array multiplier structures and k, l, p are the exponential weightings (Liu et al., 2014).

Table 1 Physical verification for Fig. 8: kink energies between adjacent cell electrons (e1 to e20) and output cell electrons
(x and y)
Case Applied kink energy to x electron (J) Applied kink energy to y electron (J) Total (J)
Fig. 8a 16.773e−20 14.791e−20 31.564e−20
Fig. 8b 17.210e−20 14.952e−20 32.162e−20
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Fig. 9 Proposed 1-bit add/sub circuit: (a) logical diagram; (b) QCA layout 1; (c) QCA layout 2; (d) QCA layout 3

Cost = A × T 2 , (7) located around the circuit are marked as scalable in

k
Cost = ( M + I + C ) × T .l p
(8) Table 4.
Each clock zone should be configured with at
Table 4 shows the comparison between our least two cells to have stable and robust connectivity.
proposed 1-bit full adder and recent ones. Only the The designs that have accounted for this point in
single-layer-schematic designs without any rotating or their architecture are distinguished in Table 4.
shifting cells have been considered in this comparison. All designs have been evaluated by both forms
Scalability and connectivity are important factors of cost metrics defined above. The exponential weight‐
in designing extendable QCA circuits. The location ings (k, l, p) are considered to be (2, 2, 2), as was
of applying inputs should not disarrange the design introduced in Liu et al. (2014).
architecture in larger circuits. All the inputs and outputs The simulation results reveal that our circuits
should be located around the circuit to make them are superior in many aspects such as scalability, con‐
easier to access, unless using them in multi-layer nectivity, complexity (cell count), area usage, delay
concepts. The designs whose inputs and outputs are (clock cycles), and energy dissipation. Also, in our
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B3
3 A33 B22 A22 B11 A1
1 B0
0 A0
0 S00

A00
Cout
out Full C2
2 Full C1
1 Full
Full C00 Full
Full Cin
in B00
adder 4 adder 3 adder
adder 22 adder
adder 11

−1
-1
S11
S33 S2
2 S11 S00

(a)

−1
-1 −1
-1
S00

A0
0

B00 A11 B1
1

S1
1

−1
-1

−1
-1
−1
-1
S22
−1
-1 −1
-1 1
A2
2

A11
B11
−1
-1 −1
-1
B22
S22

A22 B2
2

−1
-1 −1
-1

−1
-1

−1
-1
1

S3
3

A3
3

−1
-1 −1
-1
S3 B33
3

A33 B33
−1
-1 −1
-1

−1
-1 −1
-1

1
Cout
out
Cout
out
(c) (b)
Fig. 10 Proposed 4-bit ripple carry adder: (a) logical diagram; (b) QCA layout 1; (c) QCA layout 2
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D00
D00
A0
0 B00
A00
D1
1

B00 1

1
D11

−1 −1

A11 B11

−1
-1 −1
-1

D2
2

A
A11 B11

A2
2 B22
−1 −1

−1
-1
−1
-1
D22
1
A2
2

D33
A3
3 B33
−1
-1 −1
-1 −1
-1 −1
-1
B22

Brr
B
−1
-1
(b)
−1
-1
1

D3
3

A33
−1
-1 −1
-1
B33

−1
-1 −1
-1

Brr
B
(a)
Fig. 11 Proposed 4-bit ripple borrow subtractor structures: (a) QCA layout 1; (b) QCA layout 2
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A00
B00
B1
1 −1
-1 P0
P 0

A0
A 0 P1
P 1

−1
-1
B0
B 0

B1
B 1
A11 B00
B11 1
A1
A 1

−1
-1 −1
-1
P2
P 2 1

HA
HA
C S C S −1
-1 −1
-1

P33 P2
2
P1
1 P00
P3
P 3

(a) (b)

Fig. 12 Proposed 2-bit array multiplier structures: (a) logical diagram; (b) QCA layout

Fig. 13 Simulation results of the proposed 2-bit array multiplier

Table 2 The simulation setup parameters

Parameter Value Parameter Value
Cell width (nm) 18.00 Total simulation time (s) 5.00e−011
Cell height (nm) 18.00 Clock high (J) 9.80e−022
Dot diameter (nm) 5.00 Clock low (J) 3.80e−023
Temperature (K) 1.00 Clock shift 0.00
Relaxation time (s) 1.00e−015 Clock slope Gauss (s) 1.00e−012
Clock period (s) 4.00e−012 Radius of effect (nm) 80.00
Input period (s) 4.00e−012 Relative permittivity 12.90
Time step (s) 1.00e−016 Calculation method Euler method
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Table 3 Performance evaluation of the proposed designs

Desgin Number of cells Delay (c.c) Area (μm2) Sum_bath (eV) Avg_bath (eV) Sum_clk (eV) Avg_clk (eV)
1-bit full adder 1 21 0.5 0.01 2.06e−2 1.87e−3 7.52e−4 6.83e−5
1-bit full adder 2 55 1 0.05 3.39e−2 3.09e−3 −1.72e−2 −1.60e−3
1-bit full adder 3 46 1 0.04 2.73e−2 2.48e−3 −2.80e−3 −2.55e−4
1-bit add/sub 1 53 1 0.04 3.15e−2 2.86e−3 −8.70e−3 −7.90e−4
1-bit add/sub 2 93 1.5 0.13 4.93e−2 4.48e−3 −2.96e−2 −2.70e−3
1-bit add/sub 3 83 1.5 0.11 3.90e−2 3.55e−3 −1.71e−2 −1.60e−3
4-bit RCA 1 331 3.5 0.38 1.44e−1 1.31e−2 −1.01e−1 −9.20e−3
4-bit RCA 2 309 3.5 0.44 1.14e−1 1.03e−2 −6.79e−2 −6.20e−3
4-bit RBS 1 332 3.5 0.38 9.83e−2 8.93e−3 −7.32e−2 −6.70e−3
4-bit RBS 2 310 3.5 0.44 9.02e−2 8.20e−3 −5.23e−2 −4.80e−3
2-bit array multiplier 145 1.75 0.14 6.28e−2 5.71e−3 −2.53e−2 −2.30e−3
RCA: ripple carry addrer; RBS: ripple borrow subtractor; (c.c): clock cycles

Table 4 Comparison of 1-bit QCA full adder designs

Number Delay Area Total energy Cost Cost
Reference Crossover Scalability Connectivity
of cells (c.c) (μm2) dissipation (eV) Eq. (7) Eq. (8)
Abdullah-Al-Shafi and 28 0.5 0.02 2.10e−2 Not required × √ 0.005 3.25
Bahar, 2018
Balali and Rezai, 2018 39 1 0.04 3.51e−2 Logical crossing √ × 0.04 11
Heikalabad et al., 2018 41 1 0.03 3.48e−2 Not required √ × 0.03 51
Babaie et al., 2019 26 0.5 0.03 2.45e−2 Not required × √ 0.007 3.25
Mosleh, 2019 30 0.75 0.03 2.20e−2 Not required × × 0.016 7.312
Wang and Xie, 2019 45 1 0.05 2.53e−2 Not required × × 0.05 27
Majeed et al., 2020 37 0.75 0.04 2.23e−2 Not required × √ 0.022 6.178
Safoev and Jeon, 2020 56 1 0.05 2.72e−2 Logical crossing × √ 0.05 14
Wang and Xie, 2020 60 1 0.06 2.60e−2 Not required × × 0.06 53
Joy et al., 2021 61 1 0.06 2.93e−2 Not required × × 0.06 8
This paper (Proposed 1) 21 0.5 0.01 2.06e−2 Not required × √ 0.002 3.25
This paper (Proposed 2) 55 1 0.05 3.39e−2 Not required √ √ 0.05 55
This paper (Proposed 3) 46 1 0.04 2.73e−2 Logical crossing √ √ 0.04 30

proposed circuits, outputs are designed in a single and 2.06e − 2 eV, respectively. The others are designed
clock signal. This is an important issue in extended to be fully scalable. Our full adders are compared
parallel-circuit design. with the most recent ones, and the results indicate
their superiority. We have also designed other rele‐
vant arithmetic circuits. The 1-bit add/sub, 4-bit ripple
5 Conclusions carry adder, 4-bit ripple borrow subtractor, and 2-bit
array multiplier are proposed and simulated.
In this paper, we present optimal 1-bit QCA full
adders. The proposed full adders are designed on a Contributors
single layer with no rotated or shifted cells. One of Hamideh KHAJEHNASIR-JAHROMI and Pooya TORK‑
ZADEH designed the research. Hamideh KHAJEHNASIR-
our proposed 1-bit full adders is constructed out of
JAHROMI processed the data and drafted the paper. Pooya
21 QCA cells with 0.5 clock cycle latency. The total TORKZADEH helped organize the paper. Pooya TORKZA‐
occupied area and the energy dissipation are 0.01 μm2 DEH and Massoud DOUSTI revised and finalized the paper.
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Khajehnasir-Jahromi et al. / Front Inform Technol Electron Eng 2022 23(8):1264-1276 1275

Compliance with ethics guidelines Technol Trans Electr Eng, 45(3):993-999.

Hamideh KHAJEHNASIR-JAHROMI, Pooya TORKZA‐ https://doi.org/10.1007/s40998-020-00395-5
DEH, and Massoud DOUSTI declare that they have no con‐ Heikalabad SR, Asfestani MN, Hosseinzadeh M, 2018. A full
flict of interest. adder structure without cross-wiring in quantum-dot
cellular automata with energy dissipation analysis. J
Supercomput, 74(5):1994-2005.
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International Journal of Theoretical Physics (2022) 61: 23

https://doi.org/10.1007/s10773-022-05013-0

Design and Power Analysis of an Ultra-high Speed

Fault-tolerant Full-adder Cell in Quantum-dot
Cellular Automata

Milad Bagherian Khosroshahy 1 & Alireza Abdoli 1 & Amir Masoud Rahmani 2

Received: 18 August 2021 / Accepted: 3 December 2021 / Published online: 11 February 2022
# The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022

Abstract
The Quantum Cellular Automata (QCA) technology was proposed in response to the
limitations of CMOS technology. In addition, the full-adder cell (FAC) is a crucial part of
arithmetic computing so that efficient designs can play a significant role. We designed a
fault-tolerant FAC implemented on a single-layer, with no rotated or constant cells that
significantly improve the design’s manufacturability. Moreover, to further simplify the
manufacturing of our proposed circuit, we present a real clocking scheme that clusters the
proposed design based on clock regions. Besides, the design can tolerate a single
omission fault. As a result, the proposed design shows considerable complexity, area
consumption, and energy dissipation improvements by almost 22.7%, 43.75%, and 21%
in 1 Ek, respectively. Additionally, the proposed fault-tolerant FAC improves the com-
plexity, area consumption, latency, and total energy dissipation by almost 22.5%, 8%,
33.33%, and 37.74% in 1 Ek compared to the cutting-edge QCA-based single-layer fault-
tolerant FAC designs.

Keywords Quantum-dot Cellular Automata . Arithmetic computing . Single-layer circuit design .

Full-adder design . Fault tolerance . Energy dissipation analysis

1 Introduction

There have been enormous developments in the chip design industry over the last decade.
Because of Moore’s law, the size of transistors has condensed to the nanoscale, while
simultaneously, the number of completed computations per unit of time has increased. So,
electronic researchers try to provide new technologies to simplify this issue. Some

* Amir Masoud Rahmani

rahmania@yuntech.edu.tw

1
Department of Computer Science and Engineering, Shahid Beheshti University, Tehran, GC, Iran
2
Future Technology Research Center, National Yunlin University of Science and Technology, 123
University Road, Section 3, 64002 Douliou, Yunlin, Taiwan
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23 Page 2 of 19 Int J Theor Phys (2022) 61: 23

technologies were introduced instead of CMOS; those technologies have impalement in

nanoscales like QCA, CNFET, and so on [1, 2]. In general, to design VLSI circuits, three
essential parameters of speed, area, and power consumption [3–5] are regarded as portable
electronic devices that face issues such as limited battery lifetime and excessive power
consumption. Supply voltage scaling has been a notable method for the reduction of overall
power dissipation [6]. In the current generations of chips, the energy dissipation phenomena
are caused by the leakages through thin dielectric materials, transistor channels, and resistance
of chip interconnects. Researchers have proposed many techniques such as energy recapturing
and charge recovery to mitigate energy dissipation. In addition, arithmetic circuits are used in
many applications, so the increased safety of such circuits can affect other parts of the design
[7]. As a result, to address this problem, circuit designers introduced fault-tolerant designs.
Nowadays, there are many efforts about this issue. However, different applications come with
different requirements. Therefore, detecting and tolerating faults has been well studied and is
an active area of research in CMOS circuits [8, 9].
Faults in QCA circuits can occur due to the production process and misalignment of cells
on a surface. Thus, fault tolerance is crucial for designers and producers. Furthermore,
considering the tiny size of the QCA cells and the high level of accuracy required towards
cell alignment, a variety of defects may arise during the deposition step, which can be
categorized into cell displacement, extra-cell deposition, and cell omission [10].
Nowadays, VLSI physical design algorithms achieve many followers because in order to
simplify the fabrication process and manage a layout of the circuit, need to use new CAD
Algorithms CAD algorithm focuses on three main parameters like placement, routing, and
clustering each of these require different strategies so in each algorithm code developers
focuses on one of these [11]. In other words, there are some limitations about Quantum-dot
cellular Automata technologies based on problem situations that need different approaches, so
there are many parallel parameters, and unique algorithms cannot be useful for all weaknesses.
In general, there are some valuable parameters to solve each problem based on designers’
priorities in embedded design. Also, there is some specific limitation and design rules about
QCA layout circuits. Hence, physical design (CAD) management to develop these technolo-
gies play a vital role [11–13].
This study presents an optimized fault-tolerant FAC implementation based on a new
efficient and robust three-input majority gate and fault-tolerant five-input majority gate. Then
to show extendibility, we designed an efficient fault tolerance full adder gate with real clocking
capability, simplifying the fabrication process and VLSI physical design (CAD) management.
Besides, it introduced an efficient algorithm to clarify more information about the proposed
physical design (CAD) capability and functionality.
The paper is organized in the following format: Section 2 is an overview of the QCA
preliminaries. Section 3 discusses the related works, while Section 4 presents area-efficient
fault-tolerant QCA logic gate designs. Section 5 includes simulation results and comparisons,
as well as energy dissipation results. Finally, Section 6 concludes the paper.

2 Fundamentals of QCA

Electrons could take two different positionings inside the QCA cells representing logical
values’ 0’ and ‘1’. As shown in Fig. 1(a) , the electrons tunnel (i.e. move) between quantum
dots, forming cell polarization of either P = -1 (i.e., logic ‘0’) or in P = 1 (i.e., logic ‘1’).
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Int J Theor Phys (2022) 61: 23 Page 3 of 19 23

Fig. 1 (a) QCA logic ‘0’ and logic ‘1’ cells (b) QCA inverter gate (c) QCA three-input majority gate

Equation (1) defines the polarity, where ρi is probability of having an electron in the
corresponding quantum-dot [10, 14–16].

ρ1 ρ3 ρ2 ρ4
P 1
ρ1 ρ3 ρ2 ρ4

Figure 1(b) and (c) show that inverter and majority gates are two fundamental gates utilized
in logical calculations. The majority gate votes among input cells and the majority polarization
of input cells is subsequently propagated to the output cell. Equation (2) corresponds to the
majority gate. Moreover, by fixing a single input to “0” / “1”, the majority gate would
respectively turn into logic “AND” / “OR” gates [14–18].

Maj A; B; C AB BC AC 2

2.1 Clocking Scheme in QCA

The source of power in QCA circuits is the clock signal. The clock signal mechanism consists
of the following four phases, i.e., switch, hold, release, and relax, which regulate data
propagation through QCA circuits, as shown in Fig. 2 [14–19].

2.2 QCA Crossovers

There are three types of QCA crossovers: multi-layer, coplanar, and different phase crossovers,
as shown in Fig. 3.
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Fig. 2 Clocking zones in QCA designs

Multi-layer Crossover In order to prevent interference between intersecting QCA wires, the
multi-layer crossover requires two separate substrates. Unfortunately, no research has been
reported on implementing the multi-layer crossovers based on the semiconductor QCA [20].
However, there is a hybrid methodology for implementing multi-layer crossovers based on
molecular QCA. The authors created the multi-layer crossover using graphene as the substrate
and a carbon nanotube [20].

Coplanar Crossover In this type of crossover, the cells of one regular wire would cross the
other wire with cells rotated by 45 degrees. Given the different polarization of cells in the two
wires, there would be no conflicts. However, this type is not robust enough [20].

Fig. 3 Defect types in QCA circuits (a) cell omission defect (b) cell displacement defect (c) cell misalignment
defect, and (d) extra cell deposition defect [22, 23]
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Different Phase Crossover The different phase crossover applies clock signals in different
phases to allow the signals in each wire to cross through with no conflicts [21].

QCA Defect Types Defects in QCA circuits would mainly arise during the deposition process.
Various defect types are shown in Fig. 4, which basically can be categorized into the following
four categories [22, 23].

1. Cell omission defect: As the name implies, this defect happens due to cell omission, as
shown in Fig. 3(a).
2. Cell displacement and misalignment: This defect arises due to the displacement of cells
from their originally intended position, as shown in Fig. 3(b) and (c).
3. Extra cell deposition: This defect happens when a cell is deposited incorrectly, as shown
in Fig. 3(d).

2.3 Kink energy

The electrostatic interaction force between two electrons in a QCA cell is calculated using
Eq. (3) [24].
K*qi qj
E ij Joules 3
r2ij

E ij would be kink energy, where K is the Coulomb constant, qi and qj are corresponding electric
charges and rij is the distance between the two electric charges i and j. Setting K = 9 * 109, qi =
qj = 1.6 * 10−19 provides the kink energy between any two electrons as shown in Eq. (4).
In addition, U is the aggregate total energy in each cell. When we need to evaluate single-
cell power, we use Eq. (4) without the need for the distance parameter rij But when we need to
calculate the fault tolerance capability of a layout design, we need to add distance parameter
and show that with r, so in Tables 1 and 2, this parameter is added to the formula.
2
U K qi qj 9 109 1:6 10 38
23:04 10 29
4

Equation (5) calculates electrostatic energy applied to electrons qi and qj. U Ti is the interaction
energy between two electrons in each cell, and n is the number of total electrons in each
design.
Xn
U Ti E
i 1 ij
5

3 Previous Studies on Fault-tolerant QCA Designs

In general, to evaluate previous related studies, drawing attention to two gates is vital to
include types of five-input majority gates and types of full-adder gates. Hence, below each part
is illustrated with considerable detail.
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3.1 Five‑input Majority Gate

As discussed before, inverter and majority gates constitute two fundamental elements that
serve as the building blocks for realizing more complex QCA circuits. Thus, inverter and
majority gates ought to be designed to accommodate a variety of different applications. For
example, consider an embedded system design where the design should be based on specific
criteria, including speed, area, complexity, and power consumption. Furthermore, fault toler-
ance would take precedence over area, speed, power consumption, and complexity in some
applications, such as mission-critical systems. For example, the user might need a low-power
device in some applications due to a lack of access to power sources for an extended period.
Thus, there are two approaches to circuit design, embedded and general circuit designs. There
is a handful of research on five-input majority gates for embedded applications [25].
Figure 4(a) shows Farazkish et al.‘s design [26] with 50 cells and an occupying area of
0.0352 µm2. The authors evaluated single-cell omission, with the main disadvantage of their
design being the placement of the output cell in the middle of the design. Thus, to extend their
design, it is necessary to use a multi-layer structure. Another design is illustrated in Fig. 4(b) by
Du et al. [27], implemented with 22 cells and occupying an area of 0.0163 µm2, with single-
cell omission. The design by Goswamiet et al. [28], as shown in Fig. 4(c), takes 27 cells and
occupies an area of 0.0318 µm2, being evaluated with single-cell omission. Sum et al. [29], as

Fig. 4 The various cutting-edge fault-tolerant five-input majority gates

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shown in Fig. 4(d), implemented their design using 27 cells and occupying a 0.0135 µm2 area,
with single-cell omission. Finally, Moghimizadeh et al. [30] implemented their design to
include 27 cells and occupy an area of 0.0353 µm2 with single-cell omission.

3.2 Fault-tolerant FA

The fault-tolerant versions of FAC designs by (a) Du et al. [27], (b) Goswami et al. [28], (c)
Sun et al. [29], (d) Singh et al. [31] all use the corner inverter gates instead of fault-tolerant
inverter gates in their designs. Besides, these designs incur large area consumption, higher
complexity, and high latency to implement the circuits. In order to mitigate the disadvantages,
we propose a novel structure. Our design decreases the parameters mentioned above, but it is
also capable of handling single-cell omission faults (Fig. 5).

Fig. 5 The fault-tolerant one-bit FAC designs introduced in (a) [27], (b) [28], (c) [29], (d) [31]
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4 The Proposed Designs

This paper proposes a fault-tolerant FAC design based on fault-tolerant inverter gates and
majority gates. The proposed five-input majority gate in this paper is similar to the one
introduced by Khosroshahy et al. [32]. However, the original paper did not provide any
mathematical proof to show fault tolerance capabilities. Moreover, the original work merely
used the five-input majority gate for low-power applications. In this paper, we utilize the fault-
tolerant inverter gate introduced by [15]. In addition, in the QCA technologies to implement
adder gates, there are two solutions. First, fully implement based on a 3-input majority gate.
Second, design based on Five-input majority gates. So, when we need to increase parallelism
in our circuit, the second solution is best because middle input signals can apply
simultaneously.
Furthermore, the second solution provides the capability. Although there is some effort to
implement fault tolerance circuits based on the first solution [33], there is a critical point. In the
QCA circuits full covering fault can implement based on the second solution.
Additionally, we introduce a novel three-input robust majority gate as part of the proposed
fault-tolerant FAC design. Our FAC is implemented based on a real clocking technique, as
shown in Fig. 8. None of the previous designs reported fault-tolerant full-adders based on real
clocking, which is a crucial advantage of the proposed design towards facilitated fabrication
process and cost affordability [34]. Moreover, fixed input cells in a circuit can be challenging
due to physical design issues, so decreasing fixed input cells in a design plays a significant role
[35]. We did not use any constant values to design the proposed circuit, which is another
advantage of the proposed design.
The proposed FAC was implemented based on Azghadi’s formula [36]. This formula’s
advantages include a simpler implementation and a significant decrease in the number of gates
used in the design [37]. The proposed structure consists of an inverter gate, a three-input
majority gate, and a five-input majority gate. Azghadi’s formula is shown in Eqs. (6) and (7):

Sum MV Carry; Carry; Cin ; A; B 6

Carry AB BC AC 7

4.1 Evaluating the Modified Five-input Fault-tolerant Majority Gate

The proposed structure is extensively evaluated through physical verification and by consid-
ering a single-cell omission defect scenario. The modified five-input fault-tolerant majority
gate is shown in Figs. 6 and 7. Our design has 11 middle cells; however, because the energy at
the center of the design is valuable, we chose to study single-cell omission defects of the
middle cell. As a result, when the middle cell is missing, the worst-case situation happens. The
assigned values for input cells are as follows: a, b, c = 1 and d, e = 0. The kink energy between
the electrons in design is shown in Tables 1 and 2 (Fig. 8).
Generally, taking real clocking into account is an essential aspect of designing QCA
circuits. Real clocking can dramatically decrease manufacturing costs while also simplifying
the physical design of QCA circuits. As a result, designers have made various attempts to
create QCA circuits based on real clocking. A handful of such designs were implemented in
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Fig. 6 The modified five-input majority gate

pipeline format [12], while others were implemented with dynamic style [11, 13]. Moreover,
previous studies have been conducted on real clocking for the implementation of circuits with
3-inputs. To the best of our knowledge, there have been no previous studies on real clocking
for five-input majority-based circuit designs. This paper introduces a new real clocking method
with efficient clustering and placement towards complex circuits based on five-input majority
gates.
Furthermore, the clustering and real cloaking are suitable for circuits that use majority gates
with more than three inputs, i.e., five, seven, nine, etc. The method sets the cluster size such
that the biggest part of the circuit is the voter of the five-input majority gate, so we use 3 * 3
clusters. Another benefit of this cluster size is the square shape and being symmetric, which is
useful for facilitating the physical design of the circuit. Moreover, we can apply irregular

Fig. 7 Calculating output when the middle cell is missing

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Table 1 Kink energies between electrons of Fig. 7(a) based on Electron X

A 23:04 10 29 20 A 23:04 10 29 20
U1 r1 56:57 10 9
0:41 10 J U2 r2 62:03 10 9
0:37 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U3 r3 44:72 10 9
0:51 10 J U4 r4 58:03 10 9
0:4 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U5 r5 58 10 9
0:4 10 J U6 r6 43:86 10 9
0:52 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U7 r7 44:72 10 9
0:51 10 J U8 r8 43:91 10 9
0:52 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U9 r9 20 10 9
1:27 10 J U 10 r10 18:11 10 9
0:61 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U 11 r11 40 10 9
0:576 10 J U 12 r12 28:42 10 9
0:81 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U 13 r13 20 10 9
1:152 10 J U 14 r14 18:11 10 9
1:27 10 J

Table 2 Kink energies between electrons of Fig. 7(a) based on Electron Y

A 23:04 10 29 20 A 23:04 10 29 20
U1 r1 62:03 10 9
0:37 10 J U2 r2 56:57 10 9
0:41 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U3 r3 43:91 10 9
0:52 10 J U4 r4 44:72 10 9
0:51 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U5 r5 43:16 10 9
0:52 10 J U6 r6 22 10 9
1:05 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U7 r7 58:03 10 9
0:4 10 J U8 r8 44:72 10 9
0:51 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U9 r9 20 10 9
1:152 10 J U 10 r10 42:02 10 9
0:55 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U 11 r11 60:73 10 9
0:38 10 J U 12 r12 40 10 9
0:57 10 J
A 23:04 10 29 20 A 23:04 10 29 20
U 13 r13 42:05 10 9
0:55 10 J U 14 r14 20 10 9
1:15 10 J

Fig. 8 The layout of our proposed single-layer one-bit fault-tolerant FAC design
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Table 3 The kink energy between electrons e1 through e14 with respect to X and Y electrons of Fig. 7(a)

Kink energies applied to Kink energies applied to Sum of kink energies applied to electrons X
electron X electron Y and Y
P14 P14 P2
U T 11 i 1 Ui U T 12 i 1 Ui U T1 i 1 U 1i
9:319 10 20 J 8:644 10 20 J 17:963 10 20 J

clustering to ensure that all the cells in the same cluster have the same clock energy. As seen in
Fig. 9, the first and second columns are not aligned with other columns due to irregular
clustering.
Proceeding with real clocking on the proposed layout, we provide pseudo-code, which at
the core is essentially a 2D bin-packing problem with square bins (algorithm can be general-
ized to work with a rectangle) along with an extra condition that for every bin, all and every
middle cell inside the bin should be from the same clock (i.e., same color). The objective is to
make clusters as big as possible, ending with the least clusters. Following the clustering step,
we connect the clusters of the same color using bars representing different clocks, as seen in
Fig. 9. The pseudo-code for the clustering algorithm is given below:

Fig. 9 Real clocking for our single-layer one-bit fault-tolerant FAC design
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The algorithm starts with the QCA layout and ends with the clustered layout to create the
lowest number of clusters while ensuring that all cells within a cluster are the same color.
If the layout does not contain any color clocking loops and consists of a majority gate with
five or more inputs, the clustering algorithm is executed in line 4. In line 5, the bestClusterSize
is set to the voter size of the majority gate (e.g., 3 × 3 in case of this design). In line 6, the
voter cell is designated as the first cluster, and its position is added to the list of clusters (i.e.,
Clustered). Next, we should examine the neighbors of the voter cell cluster (i.e., CID = 0) for
more clusters of cells with the same color. Line 8 is a while loop that searches for new clusters
until all of the layout’s remaining cells are clustered.
In line 10, we examine the neighbors of previous clusters and look for new clusters,
assuming that the new cluster has not already been added to the list of clusters (Clustered)
(Line 11). Lines 12 through 18 find a new list of neighboringClusters and add it to the list of
previous clusters based on whether the neighboringClusters are to the left/right or top/bottom
(Clustered). Finally, the index of the next cluster to look for neighboring clusters is
incremented (Line 19).

Table 4 The kink energy between electrons e1 through e14 with respect to X and Y electrons of Fig. 7(b)

Kink energies applied to Kink energies applied to Sum of kink energies applied to electrons X
electron X electron Y and Y
P14 P14 P2
U T 21 i 1 Ui U T 22 i 1 Ui U T2 i 1 U 1i
10:699 10 20 J 10:024 10 20 J 20:723 10 20 J

Considering the results in Tables 1, 2, 3 and 4; Fig. 7(a) is more stable than Fig. 7(b)
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Table 5 Comparing various fault-tolerant majority gates based on QCA design metrics

Designs Complexity Area Latency Cell Omission

(µm2) (clock cycles)

[26] 50 0.035 0.25 single

[27] 22 0.016 0.25 single
[28] 27 0.031 0.25 single
[29] 27 0.013 0.25 single
[30] 27 0.035 0.25 single
[39] 28 0.021 0.25 single
Our design 17 0.009 0.25 single

Table 6 Comparing various single-layer fault-tolerant FAC designs based on QCA design metrics

Designs Complexity Area Latency Constant Inputs

(µm2) (clock cycles)

[27] 88 0.061 0.75 Not required

[28] 105 0.0768 0.75 Not required
[29] 113 0.0717 0.75 Not required
Design 1 [40] 138 0.13 1 Not required
Design 2 [40] 108 0.1 1 Not required
[31] 116 0.0768 1 Not required
Our design 70 0.0566 0.5 Not required

Table 7 Energy analysis for the various five-input majority gate designs

Average leakage energy Average switching energy Total energy consumption

(meV) (meV) (meV)

5-input MAJ 0.5 Ek 1 Ek 1.5 Ek 0.5 Ek 1 Ek 1.5 Ek 0.5 Ek 1 Ek 1.5 Ek

[26] 10.53 32.62 60.68 134.66 127.16 118.42 145.19 159.78 179.11
[27] 4.49 13.41 24.5 45.4 42.18 38.64 49.89 55.59 63.14
[28] 4.97 15.33 28.73 71.07 67.1 62.42 76.04 82.43 91.15
[29] 6.24 18.40 33.08 56.78 52.47 47.97 63.02 70.87 81.05
[30] 5.94 18.07 32.90 53.59 49.35 44.86 59.53 67.42 77.77
[39] 8.84 26.69 49.09 89.3 82.78 75.43 98.14 109.47 124.54
Our design 2.25 7.69 15.03 38.44 36.22 33.49 40.69 43.91 48.51

Table 8 Energy analysis of fault-tolerant one-bit FACs (NR = Not Reported)

Average leakage energy Average switching energy Total energy consumption

dissipation (eV) dissipation (eV) (eV)

Designs 0.5 Ek 1 Ek 1.5 Ek 0.5 Ek 1 Ek 1.5 Ek 0.5 Ek 1 Ek 1.5 Ek

[27] NR NR NR NR NR NR NR NR NR
[28] NR NR NR NR NR NR NR NR NR
[29] 0.02968 0.09148 0.16692 0.24168 0.21846 0.19431 0.27136 0.30995 0.36124
Design 1 NR NR NR NR NR NR NR NR NR
[40]
Design 2 NR NR NR NR NR NR NR NR NR
[40]
[31] 0.02255 0.07453 0.14446 0.31000 0.29195 0.26958 0.33255 0.36648 0.41403
Our 0.01779 0.05604 0.10348 0.15188 0.13693 0.12098 0.16967 0.19297 0.22446
design
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Fig. 10 The energy dissipation map for our modified fault-tolerant five-input majority gate designs with the
temperature at 2 K and 1 Ek

Fig. 11 The energy dissipation map for fault-tolerant FAC designs in (a) [29], (b) [31] and (c) the proposed
design at 2 K temperature with 1 Ek
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5 Performance Evaluation

In order to simulate QCA circuits, we used QCADesigner software [38] as the most prominent
and powerful tool for the simulation of QCA circuits. Parameters of the QCADesigner are set
as cell size = 18 nm, quantum dots diameter = 5 nm, relative permittivity = 12.9, sample
number = 50,000, effect radius = 65 nm, convergence tolerance = 0.001, layer separation =
11.5 nm, clock low = 3.8e-23 J, clock amplitude factor = 2.000, clock high = 9.8e-22 J, and
maximum iterations per sample = 100. As shown in Figs. 12 and 13, the simulation results
validate our fault-tolerant FAC design functionality. Moreover, in Tables 5 and 6, we compare
our proposed fault-tolerant FAC against the top-notch fault-tolerant designs.
QCAPro is a tool used to evaluate total energy dissipation, switching, and leakage in QCA
circuit designs [41]. Tables 7 and 8 show the energy dissipation analysis for our proposed
fault-tolerant five-input majority gate design and one-bit FAC design. The simulation statistics
are calculated in three levels of distinct tunneling energy (i.e., 0.5, 1, and 1.5 Ek), given
operational temperature at 2 K. Moreover, Fig. 10 shows a thermal map of our proposed
design given temperatures as 2 K and 1 Ek. While Fig. 11 shows the thermal map for our
proposed fault-tolerant FAC design alongside some top-notch designs at 2 K temperature and
1 Ek. It should be mentioned that darker QCA cells exhibit higher energy dissipation in the
circuit design.
The graphical thermal diagram depicted in Fig. 11 demonstrates a comparison of total
energy dissipation for various designs, depicting the energy efficiency of the suggested circuit
design. Figure 11 shows that our suggested design has reduced energy dissipation when

Fig. 12 The simulation results for a five-input majority gate design

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Fig. 13 The simulation results of our proposed fault-tolerant one-bit FAC design

compared to top-notch designs. The primary contributors to minimized energy consumption

include cell arrangements and refraining from rotated cells in our design. In terms of total
energy dissipation, as shown in Table 8, our proposed design dissipates on average %37.73,
%37.74, and %37.86 less energy for tunneling energy levels of 0.5Ek, 1Ek, and 1.5Ek,
respectively (Figs. 12 and 13).
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6 Conclusions

Initially, we introduced a novel fault-tolerant five-input majority gate design capable of

tolerating single-omission fault. Our design, compared with state-of-the-art implementations,
has less complexity, area, and power consumption. Moreover, our modified fault-tolerant
majority gate is implemented in a symmetric square shape that helps with simplified physical
design management. Then, we proposed a new fault-tolerant FAC design that is highly
efficient in power consumption, area consumption, and complexity. Additionally, our sug-
gested design was implemented based on a novel dynamic real clocking scheme. The real
clocking can be used for circuits designed based on multi-input majority gates (majority gates
with more than three inputs). Because multi-input majority gates, in comparison with other
gates, occupy more area, the cluster size should be chosen appropriately to give better results,
according to the size of the voter of the majority gate. Clustering placement does not
necessarily have to be regular and irregular clustering can be used to ensure all the cells in a
cluster are of the same color. Furthermore, the clocking can be accomplished with the least
number of bars connecting the clusters corresponding to the same clocking regions. Finally,
compared to top-notch QCA-based single-layer fault-tolerant FAC designs, we obtained
considerable gains in reduced latency, area consumption, total energy dissipation, and com-
plexity by almost 33.33%, 8% 37.74%, and 22.5%, respectively for 1 Ek.

Author Contributions All authors contributed equally to this manuscript.Data Availability Not applicable.

Code Availability Not applicable.

Declarations

Conflicts of Interest/Competing Interests There is no conflict of interest among authors.

Ethics approval Not applicable.

Consent to Participate All participants have provided consent to participate.

Consent for Publication Consent for publication was obtained from all authors.

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