Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers

Single-Channel: 6N137M, HCPL2601M, HCPL2611M

April 2013

Single-Channel: 6N137M, HCPL2601M, HCPL2611M

Dual-Channel: HCPL2630M, HCPL2631M
High-Speed 10 MBit/s Logic Gate Optocouplers
Features Description
■ Very High Speed – 10 MBit/s The 6N137M, HCPL2601M, HCPL2611M single-channel
■ Superior CMR – 10 kV/µs and HCPL2630M, HCPL2631M dual-channel optocou-
■ Fan-out of 8 Over -40°C to +85°C plers consist of a 850 nm AlGaAS LED, optically coupled
■ Logic Gate Output to a very high speed integrated photo-detector logic gate
■ Strobable Output with a strobable output. This output features an open col-
■ Wired OR-open Collector lector, thereby permitting wired OR outputs. The
■ U.L. Recognized (File # E90700, Vol. 2) switching parameters are guaranteed over the tempera-
ture range of -40°C to +85°C. A maximum input signal of
Applications 5 mA will provide a minimum output sink current of
■ Ground Loop Elimination 13 mA (fan out of 8).
■ LSTTL to TTL, LSTTL or 5 V CMOS An internal noise shield provides superior common
■ Line Receiver, Data Transmission mode rejection of typically 10 kV/µs. The HCPL2601M
■ Data Multiplexing and HCPL2631M has a minimum CMR of 5 kV/µs. The
■ Switching Power Supplies HCPL2611M has a minimum CMR of 10 kV/µs.
■ Pulse Transformer Replacement
■ Computer-peripheral Interface

Schematics Package Outlines

8 8
N/C 1 8 VCC + 1 8 VCC
1 1
VF1

+ 2 7 VE _ 2 7 V01
VF
8
_ _ 8
3 6 VO 3 6 V02
1
1
V
F2 Figure 2. Package Options
N/C 4 5 GND + 4 5 GND Truth Table (Positive Logic)
Input Enable Output
H H L
6N137M HCPL2630M
HCPL2601M L H H
HCPL2631M
HCPL2611M (Preliminary) H L H
L L H
A 0.1µF bypass capacitor must be connected between pins 8 and 5(1). H NC L
Figure 1. Schematics L NC H

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Safety and Insulation Ratings for 8-Pin DIP White
As per DIN_EN/IEC 60747-5-2. This optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.

Symbol Parameter Min. Typ. Max. Unit

Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150 VRMS I–IV
For Rated Mains Voltage < 300 VRMS I–IV
For Rated Mains Voltage < 450 VRMS I–III
For Rated Mains Voltage < 600 VRMS I–III
Climatic Classification 40/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
CTI Comparative Tracking Index 175
VPR Input to Output Test Voltage, Method b, 1,669
VIORM x 1.875 = VPR, 100% Production Test with
tm = 1 s, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a, 1,335
VIORM x 1.5 = VPR, Type and Sample Test with
tm = 60 s, Partial Discharge < 5 pC
VIORM Max Working Insulation Voltage 890 VPEAK
VIOTM Highest Allowable Over Voltage 6,000 VPEAK
External Creepage 8.0 mm
External Clearance 7.4 mm
External Clearance (for Option T, 0.4” Lead Spacing) 10.16 mm
Insulation Thickness 0.5 mm
Safety Limit Values, Maximum Values Allowed in the
Event of a Failure
TS Case Temperature 150 °C
IS,INPUT Input Current 200 mA
PS,OUTPUT Output Power (Duty Factor ≤ 2.7%) 300 mW
RIO Insulation Resistance at TS, VIO = 500 V 109 Ω

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 2
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified.

Symbol Parameter Value Units

TSTG Storage Temperature -40 to +125 °C
TOPR Operating Temperature -40 to +100 °C
TSOL Lead Solder Temperature 260 for 10 s °C
Emitter
IF DC/Average Forward Single Channel 50 mA
Input Current Dual Channel (Each Channel) 30
VE Enable Input Voltage Not to Exceed Single Channel 5.5 V
VCC by more than 500 mV
VR Reverse Input Voltage Each Channel 5.0 V
PI Power Dissipation Single Channel 100 mW
Dual Channel (Each Channel) 45
Detector
VCC Supply Voltage 7.0 V
(1 minute max)
IO Output Current Single Channel 50 mA
Dual Channel (Each Channel) 50
VO Output Voltage Each Channel 7.0 V
PO Collector Output Single Channel 85 mW
Power Dissipation Dual Channel (Each Channel) 60

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Min. Max. Units

IFL Input Current, Low Level 0 250 µA
IFH Input Current, High Level *6.3 15 mA
VCC Supply Voltage, Output 4.5 5.5 V
VEL Enable Voltage, Low Level 0 0.8 V
VEH Enable Voltage, High Level 2.0 VCC V
TA Ambient Operating Temperature -40 +85 °C
N Fan Out (TTL load) 8

*6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value
is 5.0 mA or less.

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 3
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Electrical Characteristics (TA = 0 to 70°C unless otherwise specified)
Individual Component Characteristics
Symbol Parameter Test Conditions Min. Typ.* Max. Unit
EMITTER
VF Input Forward Voltage IF = 10 mA 1.8 V
TA = 25°C 1.4 1.75
BVR Input Reverse Breakdown IR = 10 µA 5.0 V
Voltage
CIN Input Capacitance VF = 0, f = 1 MHz 60 pF
ΔVF / ΔTA Input Diode Temperature IF = 10 mA -1.4 mV/°C
Coefficient
DETECTOR
ICCH High Level Supply Current VCC = 5.5 V, IF = 0 mA, Single Channel 6 10 mA
VE = 0.5 V Dual Channel 10 15
ICCL Low Level Supply Current Single Channel VCC = 5.5 V, 8 13 mA
IF = 10 mA
Dual Channel VE = 0.5 V 14 21
IEL Low Level Enable Current VCC = 5.5 V, VE = 0.5 V -0.7 -1.6 mA
IEH High Level Enable Current VCC = 5.5 V, VE = 2.0 V -0.5 -1.6 mA
VEH High Level Enable Voltage VCC = 5.5 V, IF = 10 mA 2.0 V
(3)
VEL Low Level Enable Voltage VCC = 5.5 V, IF = 10 mA 0.8 V

Switching Characteristics (TA = -40°C to +85°C, VCC = 5 V, IF = 7.5 mA unless otherwise specified)
Symbol AC Characteristics Test Conditions Min. Typ.* Max. Unit
TPLH Propagation Delay RL = 350 Ω, TA = 25°C 20 40 75 ns
Time to Output HIGH CL = 15 pF(4) (Fig. 14) 100
Level
TPHL Propagation Delay TA = 25°C(5) 25 40 75 ns
Time to Output LOW RL = 350 Ω, CL = 15 pF (Fig. 14) 100
Level
|TPHL–TPLH| Pulse Width Distortion RL = 350 Ω, CL = 15 pF (Fig. 14) 1 35 ns
(6)
tr Output Rise Time RL = 350 Ω, CL = 15 pF (Fig. 14) 30 ns
(10% to 90%)
tf Output Rise Time RL = 350 Ω, CL = 15 pF(7) (Fig. 14) 10 ns
(90% to 10%)
tELH Enable Propagation IF = 7.5 mA, VEH = 3.5 V, RL = 350 Ω, CL = 15 pF(8) 15 ns
Delay Time to Output (Fig. 15)
HIGH Level
tEHL Enable Propagation IF = 7.5 mA, VEH = 3.5 V, RL = 350 Ω, CL = 15 pF(9) 15 ns
Delay Time to Output (Fig. 15)
LOW Level
|CMH| Common Mode TA = 25°C, |VCM| = 50 V 6N137M, HCPL2630M 10,000 V/µs
Transient Immunity (Peak), IF = 0 mA, HCPL2601M, 5000 10,000
(at Output HIGH Level) VOH (Min.) = 2.0 V, HCPL2631M
RL = 350 Ω(10) (Fig. 16)

|VCM| = 400 V HCPL2611M 10,000 15,000 V/µs

|CML| Common Mode RL = 350 Ω, IF = 7.5 mA, 6N137M, HCPL2630M 10,000
Transient Immunity VOL (Max.) = 0.8 V, HCPL2601M, 5000 10,000
(at Output LOW Level) TA = 25°C(11) (Fig. 16) HCPL2631M
|VCM| = 400 V HCPL2611M 10,000 15,000

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 4
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Electrical Characteristics (Continued)
Transfer Characteristics (TA = -40 to +85°C unless otherwise specified)
Symbol DC Characteristics Test Conditions Min. Typ.* Max. Unit
IOH HIGH Level Output Current VCC = 5.5 V, VO = 5.5 V, 100 µA
IF = 250 µA, VE = 2.0 V(2)
VOL LOW Level Output Current VCC = 5.5 V, IF = 5 mA, VE = 2.0 V, 0.4 0.6 V
ICL = 13 mA(2)
IFT Input Threshold Current VCC = 5.5 V, VO = 0.6 V, VE = 2.0 V, 3 5 mA
IOL = 13 mA

Isolation Characteristics (TA = -40°C to +85°C unless otherwise specified.)

Symbol Characteristics Test Conditions Min. Typ.* Max. Unit
II-O Input-Output Insulation Relative humidity = 45%, 1.0* µA
Leakage Current TA = 25°C, t = 5 s,
VI-O = 3000 VDC(12)
VISO Withstand Insulation Test RH < 50%, TA = 25°C, 5000 VRMS
Voltage II-O ≤ 10 µA, t = 1 min.(12)
RI-O Resistance (Input to Output) VI-O = 500 V(12) 1011 Ω
CI-O Capacitance (Input to Output) f=1 MHz(12) 1 pF

*All Typicals at VCC = 5 V, TA = 25°C

Notes:
1. The VCC supply to each optoisolator must be bypassed by a 0.1 µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package VCC and GND pins of each device.
2. Each channel.
3. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
4. tPLH – Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
5. tPHL – Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH – Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
HIGH state (i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/µs).
11. CML – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
LOW output state (i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 5
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Typical Performance Curves
For Single-Channel Devices: 6N137M, HCPL2601M, and HCPL2611M
0.8

IF = 5 mA
VOL – LOW LEVEL OUTPUT VOLTAGE (V)

0.7 VE = 2 V
10
VCC = 5.5 V

IF – FORWARD CURRENT (mA)

0.6
IOL = 12.8 mA
0.5 1
IOL = 16 mA

0.4
0.100
0.3 IOL = 6.4 mA

IOL = 9.6 mA
0.2
0.010
0.1

0.0 0.001
-40 -20 0 20 40 60 80 100 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
TA – AMBIENT TEMPERATURE (°C) VF – FORWARD VOLTAGE (V)

Figure 3. Low Level Output Voltage vs. Ambient Temperature Figure 4. Input Diode Forward Voltage vs. Forward Current

120 50
VCC = 5 V
TA = 25°C
IOL – LOW LEVEL OUTPUT CURRENT (mA)

100 45
TP – PROPAGATION DELAY (ns)

IF = 15 mA

80 RL = 4 kΩ (tPLH) 40
IF = 10 mA

60 RL = 350 Ω (tPLH) 35
RL = 1 kΩ (tPLH)
IF = 5 mA
40 30
RL = 4 kΩ (tPHL) VCC = 5 V
RL = 1 kΩ (tPHL) VE = 2 V
20 25
RL = 350 Ω (tPHL) VOL = 0.6 V

0 20
5 7 9 11 13 15 -40 -20 0 20 40 60 80 100
IF – FORWARD CURRENT (mA) TA – AMBIENT TEMPERATURE (°C)

Figure 5. Switching Time vs. Forward Current Figure 6. Low Level Output vs. Ambient Temperature

4.0 6

VCC = 5 V
IFT – INPUT THRESHOLD CURRENT (mA)

3.5 VE = 2 V 5
VOL = 0.6 V
VO – OUTPUT VOLTAGE (V)

3.0 4
RL = 350 Ω RL = 1 kΩ

2.5 3
RL = 1 kΩ
RL = 350 Ω

2.0 RL = 4 kΩ 2

RL = 4 kΩ
1.5 1

1.0 0
-40 -20 0 20 40 60 80 100 0 1 2 3 4 5 6
TA – AMBIENT TEMPERATURE (°C) IF - FORWARD CURRENT (mA)
Figure 7. Input Threshold Current vs. Ambient Temperature Figure 8. Output Voltage vs. Input Forward Current

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 6
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Typical Performance Curves (Continued)
(For Single-Channel Devices: 6N137M, HCPL2601M, HCPL2611M)

60 500

IF = 7.5 mA
PWD – PULSE WIDTH DISTORTION (ns)

VCC = 5 V IF = 7.5 mA
50
400 VCC = 5 V

tR / tF – RISE AND FALL TIME (ns)

40 RL = 4 kΩ (tR)
RL = 4 kΩ 300

30
200
20

100 RL = 1 kΩ (tR)
10
RL = 1 kΩ RL = 350 Ω (tR)

0
0 RL = 4 kΩ (tF)
RL = 350 Ω
RL = 1 kΩ (tF)
RL = 350 Ω (tF)
-10 -100
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TA – AMBIENT TEMPERATURE (°C) TA – AMBIENT TEMPERATURE (°C)

Figure 9. Pulse Width Distortion vs. Temperature Figure 10. Rise and Fall Time vs. Temperature
TE – ENABLE PROPAGATION DELAY (ns)

100 100
IF = 7.5 mA
IF = 7.5 mA
VCC = 5 V 90 VCC = 5 V
80 RL = 4 kΩ (tPLH)
TP – PROPAGATION DELAY (ns)

80
RL = 4 kΩ (tELH)
70
60

60
RL = 1 kΩ (tPLH)
40
RL = 1 kΩ (tELH)
50
RL = 350 Ω (tPLH)
40 RL = 4 kΩ (tPHL)
RL = 350 Ω (tELH)
20 RL = 1 kΩ (tPHL)
RL = 350 Ω (tPHL)
RL = 4 kΩ / 1 kΩ / 350 Ω (tEHL)
30

0 20
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TA – AMBIENT TEMPERATURE (°C) TA – AMBIENT TEMPERATURE (°C)

Figure 11. Enable Propagation Delay vs. Temperature Figure 12. Switching Time vs. Temperature

1.6
IOH – HIGH LEVEL OUTPUT CURRENT (μA)

1.4 VCC = 5 V
VO = 5.5 V
VE = 2 V
1.2 IF = 250 μA

1.0

0.8

0.6

0.4

0.2

0
-40 -20 0 20 40 60 80 100
TA – AMBIENT TEMPERATURE (°C)

Figure 13. High Level Output Current vs. Temperature

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 7
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Typical Performance Curves (Continued)
For Dual-Channel Devices: HCPL2630M and HCPL2631M

0.8 100
VOL – LOW LEVEL OUTPUT VOLTAGE (V)

IF = 5 mA
0.7
VCC = 5.5 V

IF – FORWARD CURRENT (mA)

10
0.6
IOL = 12.8 mA IOL = 16 mA

0.5 1

0.4
IOL = 6.4 mA IOL = 9.6 mA 0.1
0.3

0.2
0.01
0.1

0.0 0.001
-40 -20 0 20 40 60 80 100 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
TA – AMBIENT TEMPERATURE (°C) VF – FORWARD VOLTAGE (V)

Figure 14. Low Level Output Voltage vs. Ambient Temperature Figure 15. Input Diode Forward Voltage
vs. Forward Current

120 50

IOL – LOW LEVEL OUTPUT CURRENT (mA)

VCC = 5 V
TP – PROPAGATION DELAY (ns)

TA = 25°C
100 45
IF = 15 mA
RL = 4 kΩ (TPLH)
IF = 10 mA
80 40
IF = 5 mA

60 35
RL = 1 kΩ (TPLH)

40 RL = 350 Ω (TPLH ) 30
RL = 1 kΩ VCC = 5 V
RL = 4 kΩ (TPHL) VOL = 0.6 V
20 RL = 350 Ω 25

0 20
5 7 9 11 13 15 -40 -20 0 20 40 60 80 100
IF – FORWARD CURRENT (mA) TA – AMBIENT TEMPERATURE (°C)

Figure 16. Switching Time vs. Forward Current Figure 17. Low Level Output Current
vs. Ambient Temperature

6
IFT – INPUT THRESHOLD CURRENT (mA)

VCC = 5.0 V
VOL = 0.6 V 5
VO – OUTPUT VOLTAGE (V)

RL = 350 Ω 4
3
RL = 350 Ω
RL = 4 kΩ
RL = 1 kΩ
3
RL = 4 kΩ

2 2
RL = 1 kΩ

1 0
-40 -20 0 20 40 60 80 100 0 1 2 3 4 5 6
TA – AMBIENT TEMPERATURE (°C) IF - FORWARD CURRENT (mA)

Figure 18. Input Threshold Current Figure 19. Output Voltage vs. Input Forward Current
vs. Ambient Temperature

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 8
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Typical Performance Curves (Continued)
For Dual-Channel Devices: HCPL2630M and HCPL2631M

80 600
PWD – PULSE WIDTH DISTORTION (ns)

Tr/Tf – RISE AND FALL TIME (ns)

500 IF = 7.5 mA
RL = 4 kΩ
VCC = 5 V
60
400
RL = 4 kΩ (tr)
IF = 7.5 mA
VCC = 5 V
40 300

RL = 1 kΩ
200 RL = 4 kΩ (tf)
20 RL = 350 Ω
RL = 1 kΩ RL = 1 kΩ (tr)
100
RL = 350 Ω RL = 350 Ω (tr)
0 0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE (°C) TA – TEMPERATURE (°C)

Figure 20. Pulse Width Distortion vs. Temperature Figure 21. Rise and Fall Time vs. Temperature

120 1.8
RL = 4 kΩ (TPLH) IOH – HIGH LEVEL OUTPUT CURRENT (μA)
1.6 VCC = 5.5 V
TP – PROPAGATION DELAY (ns)

VO = 5.5 V
100 IF = 250 μA
1.4
IF = 7.5 mA
VCC = 5 V
1.2
80
1.0

0.8
60
RL = 1 kΩ (TPLH)
0.6
RL = 350 Ω (TPLH)
40 0.4
RL = 1 kΩ 0.2
RL = 4 kΩ (TPHL)
RL = 350 Ω
20 0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE (°C) TA – TEMPERATURE (°C)
Figure 23. High Level Output Current
Figure 22. Switching Time vs. Temperature vs. Temperature

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 9
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Test Circuits

Pulse
Generator
tr = 5 ns
Z O = 50 Ω +5 V

IF = 7.5 mA
VCC IF = 3.75 mA
Input
1 8 (IF )
t PHL tPLH

.1 μF Output
2 7 RL
(VO )
bypass
1.5 V
Input Output
Monitor
3 6 (VO ) 90%
Output
(I F) CL
(VO )
10%
47 4 5
GND tf tr

Figure 24. Test Circuit and Waveforms for tPLH, tPHL, tr and tf

Pulse
Generator Input
tr = 5 ns Monitor
Z O = 50 Ω (V E)

+5 V

3.0 V
VCC Input
(VE ) 1.5 V
1 8
t EHL t ELH
7.5 mA
Output
2 7 .1 μF
RL
(VO )
bypass 1.5 V
Output
3 6 (VO )
CL

4 5
GND

Figure 25. Test Circuit tEHL and tELH

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 10
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Test Circuits (Continued)

VCC
1 8 +5 V

IF
A 2 7 .1 μF 350 Ω
bypass
B
Output
VFF 3 6 (VO)

4 5
GND

VCM

Pulse Gen

Peak

VCM
0V

5V CM H
Switching Pos. (A), IF = 0
VO
VO (Min)

VO (Max)

Switching Pos. (B), I F = 7.5 mA

VO
0.5 V CM L

Figure 26. Test Circuit Common Mode Transient Immunity

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 11
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Package Dimensions
Through Hole 0.4" Lead Spacing (Option TV) (Pending)
PIN 1
ID.
PIN 1
4 3 2 1 ID.
4 3 2 1
0.270 (6.86)
0.250 (6.35)
5 6 7 8 0.270 (6.86)
0.250 (6.35)

0.390 (9.91)
5 6 7 8
0.370 (9.40)
SEATING PLANE

0.156 (3.94)
0.070 (1.78)
0.144 (3.68)
0.045 (1.14) 0.390 (9.91)
0.370 (9.40)
0.020 (0.51)

SEATING PLANE
0.200 (5.08) MIN 0.156 (3.94)
MAX 0.070 (1.78) 0.144 (3.68)
0.045 (1.14)
0.154 (3.90) 0.020 (0.51)
0.200 (5.08) MIN
0.120 (3.05) MAX
0.022 (0.56) 15° MAX
0.016 (0.40)
0.016 (0.41) 0.154 (3.90)
0.008 (0.20)
0.300 (7.62) 0.120 (3.05)
0.100 (2.54) TYP
TYP
0.022 (0.56) 0° to 15°
0.016 (0.41) 0.016 (0.40)
0.008 (0.20)
0.400 (10.16)
0.100 (2.54) TYP
TYP
0.031 (0.78)

Surface Mount – 0.3" Lead Spacing (Option S) 8-Pin Surface Mount DIP – Land Pattern
(Option S)
0.390 (9.91)
0.370 (9.40)
PIN 1 0.070 (1.78)
4 3 2 1 ID.

0.270 (6.86)
0.060 (1.52)
0.250 (6.35)

5 6 7 8 0.100 (2.54)
0.295 (7.49)
0.030 (0.76)
0.156 (3.94) 0.415 (10.54)
0.070 (1.78) 0.300 (7.62)
0.144 (3.68) TYP
0.045 (1.14)

0.020 (0.51) 0.016 (0.40)

MIN 0.008 (0.20)

0.200 (5.08) 0.015 (0.40) MIN

0.022 (0.56) Both Sides
MAX
0.016 (0.41)

0.100 (2.54)
TYP 0.315 (8.00)
MIN
0.405 (10.30)
MAX.

Note:
All dimensions are in inches (millimeters)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 12
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Package Dimensions (Continued)

Surface Mount – 0.4" Lead Spacing (Option TS) 8-Pin Surface Mount DIP – Land Pattern
(Option TS)
0.390 (9.91)
0.370 (9.40)
PIN 1 0.070 (1.78)
4 3 2 1 ID.

0.270 (6.86)
0.060 (1.52)
0.250 (6.35)

5 6 7 8 0.100 (2.54)
0.392 (9.96)
0.030 (0.76)
0.156 (3.94) 0.511 (13.0)
0.070 (1.78) 0.300 (7.62)
0.144 (3.68)
0.045 (1.14) TYP

0.020 (0.51) 0.016 (0.40)

MIN 0.008 (0.20)

0.015 (0.40) MIN

0.200 (5.08) 0.031 (0.775)
Both Sides
MAX
0.022 (0.56) 0.400 (10.16)
0.016 (0.41)

0.100 (2.54) 0.497 (12.6)

TYP MAX.

Note:
All dimensions are in inches (millimeters)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 13
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Ordering Information
Example Part
Option Number Description
No Suffix 6N137M Standard Through Hole Device, 50 pcs per tube
S 6N137SM Surface Mount Lead Bend
SD 6N137SDM Surface Mount; Tape and Reel
V 6N137VM DIN_EN/IEC60747-5-2 (VDE)
TV 6N137TVM DIN_EN/IEC60747-5-2 (VDE), 0.4” lead spacing
SV 6N137SVM DIN_EN/IEC60747-5-2 (VDE), surface mount
SDV 6N137SDVM DIN_EN/IEC60747-5-2 (VDE), surface mount, tape and reel
TS 6N137TSM Surface Mount, 0.4” lead spacing
TSV 6N137TSVM Surface Mount, 0.4” lead spacing, IEC60747-5-2 approval pending (VDE)
TSR2 6N137TSR2M Surface Mount, Tape and Reel, 0.4” lead spacing
TSR2V 6N137TSR2VM Surface Mount, Tape and Reel, 0.4” lead spacing, IEC60747-5-2 approval
pending (VDE)

Marking Information

6N137 2

6
V XX YY B

3 4 5

Definitions
1 Fairchild logo
2 Device number
DIN_EN/IEC60747-5-2 (VDE) mark (Note: Only appears
3
on parts ordered with VDE option – See order entry table)
4 Two digit year code, e.g., ‘13’
5 Two digit work week ranging from ‘01’ to ‘53’
6 Assembly package code

Note:
‘HCPL’ devices are marked only with the numerical characters (for example, HCPL2630 is
marked as ‘2630’).

The ‘M’ suffix on the part number is an order identifier only. It is used to identify orders for the
white package version. The ‘M’ does not appear on the device’s top mark.

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 14
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Carrier Tape Specifications (Option SD)
D0
P0 P2
t E
K0

F
A0
W1 W
B0

User Direction of Feed P

d D1

Symbol Description Dimension in mm

W Tape Width 16.0 ± 0.3
t Tape Thickness 0.30 ± 0.05
P0 Sprocket Hole Pitch 4.0 ± 0.1
D0 Sprocket Hole Diameter 1.55 ± 0.05
E Sprocket Hole Location 1.75 ± 0.10
F Pocket Location 7.5 ± 0.1
P2 2.0 ± 0.1
P Pocket Pitch 12.0 ± 0.1
A0 Pocket Dimensions 10.30 ±0.20
B0 10.30 ±0.20
K0 4.90 ±0.20
W1 Cover Tape Width 13.2 ± 0.2
d Cover Tape Thickness 0.1 maximum
Max. Component Rotation or Tilt 10°
R Min. Bending Radius 30

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 15
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Carrier Tape Specifications (Option TSR2)
D0
P0 P2
t E
K0

F
A0
W1 W
B0

User Direction of Feed P

d D1

Symbol Description Dimension in mm

W Tape Width 24.0 ± 0.3
t Tape Thickness 0.40 ± 0.1
P0 Sprocket Hole Pitch 4.0 ± 0.1
D0 Sprocket Hole Diameter 1.55 ± 0.05
E Sprocket Hole Location 1.75 ± 0.10
F Pocket Location 11.5 ± 0.1
P2 2.0 ± 0.1
P Pocket Pitch 16.0 ± 0.1
A0 Pocket Dimensions 12.80 ± 0.1
B0 10.35 ± 0.1
K0 5.7 ±0.1
W1 Cover Tape Width 21.0 ± 0.1
d Cover Tape Thickness 0.1 max
Max. Component Rotation or Tilt 10°
R Min. Bending Radius 30

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 16
 Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Reflow Profile
Max. Ramp-up Rate = 3°C/S
TP Max. Ramp-down Rate = 6°C/S
260
240 tP
TL
220
200 Tsmax
tL
Temperature (°C)

180 Preheat Area

160
Tsmin
140
ts
120
100
80
60
40
20
0
120 240 360
Time 25°C to Peak
Time (seconds)

Profile Freature Pb-Free Assembly Profile

Temperature Minimum (Tsmin) 150°C
Temperature Maximum (Tsmax) 200°C
Time (tS) from (Tsmin to Tsmax) 60 to 120 seconds
Ramp-up Rate (tL to tP) 3°C/second maximum
Liquidous Temperature (TL) 217°C
Time (tL) Maintained Above (TL) 60 to 150 seconds
Peak Body Package Temperature 260°C +0°C / –5°C
Time (tP) within 5°C of 260°C 30 seconds
Ramp-down Rate (TP to TL) 6°C/second maximum
Time 25°C to Peak Temperature 8 minutes maximum

©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

6N137M, HCPL26XXM Rev. 1.0.8 17
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M — High Speed 10MBit/s Logic Gate Optocouplers

www.fairchildsemi.com
18
©2009 Fairchild Semiconductor Corporation
6N137M, HCPL26XXM Rev. 1.0.8