A

Project Report
on
DESIGN AND IMPLEMENTATION OF SUBWAY
AUTOMATIC TICKETING SYSTEM BASED ON VERILOG
HDL
Submitted to

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR, ANANTAPURAMU

in partial fulfillment of the requirements for the award of the Degree of

BACHELOR OF TECHNOLOGY

in
ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by

KUMMARA BINDHU MADHAV SAI (199E1A04G0)

SIDDA SONALI (199E1A04I3)
SAREDDY MALLESH REDDY (209E5A0419)
B B JATIN KRISHNA (199E1A04D3)
KANNAN CHANDRA SEKHAR (199E1A04F6)

Under the Guidance of

CH.PALLAVI
M.Tech (Ph.D)
Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SRI VENKATESWARA ENGINEERING COLLEGE
(Approved by AICTE, New Delhi & Affiliated to JNTUA, Ananthapuramu)
Karakambadi Road, TIRUPATI – 517507
2019-2023
 SRI VENKATESWARA ENGINEERING COLLEGE
(Approved by AICTE, New Delhi & Affiliated to JNTUA, Ananthapuramu)
Karakambadi Road, TIRUPATI – 517507
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE

This is to certify that the project report entitled “DESIGN AND IMPLEMENTATION
OF SUBWAY AUTOMATIC TICKETING SYSTEM BASED ON VERILOG HDL”
a bonafide record of the project work done and submitted by

KUMMARA BINDHU MADHAV SAI (199E1A04G0)

SIDDA SONALI (199E1A04I3)
SAREDDY MALLESH REDDY (209E5A0419)
B B JATIN KRISHNA (199E1A04D3)
KANNAN CHANDRA SEKHAR (199E1A04F6)

for the partial fulfillment of the requirements for the award of B.Tech Degree in ELECTRONICS AND
COMMUNICATION ENGINEERING, JNT University Anantapur, Ananthapuramu.

GUIDE Head of the Department

External Viva-Voce Exam Held on

INTERNAL EXAMINER EXTERNAL EXAMINER

 DECLARATION

We hereby declare that the project report entitled “DESIGN AND

IMPLEMENTATION OF SUBWAY AUTOMATIC TICKETING SYSTEM
BASED ON VERILOG HDL” submitted to the department of ELECTRONICS
AND COMMUNICATION ENGINEERING in partial fulfillment of requirements
for the award of the degree of BACHELOR OF TECHNOLOGY. This project is the
result of our own effort and that it has not been submitted to any other University or
Institution for the award of any degree or diploma other than specified above.

KUMMARA BINDHU MADHAV SAI 199E1A04G0

SIDDA SONALI 199E1A04I3
SAREDDY MALLESH REDDY 209E5A0419
B B JATIN KRISHNA 199E1A04D3
KANNAN CHANDRA SEKHAR 199E1A04F6
 ACKNOWLEDGEMENT

We are thankful to our guide CH.Pallavi for her valuable guidance and
encouragement. Her helping attitude and suggestions have helped us in the successful
completion of the project.
We would like to express our gratefulness and sincere thanks to
Dr.D.Srinivasulu Reddy Head of the Department of ELECTRONICS AND
COMMUNICATION ENGINEERING, for his kind help and encouragement during
the course of our study and in the successful completion of the project work.
We have great pleasure in expressing our hearty thanks to our beloved
Principal Dr.C.Chandra Sekhar for spending his valuable time with us to complete
this project.
Successful completion of any project cannot be done without proper support
and encouragement. We sincerely thanks to the Management for providing all the
necessary facilities during the course of study.
We would like to thank our parents and friends, who have the greatest
contributions in all our achievements, for the great care and blessings in making us
successful in all our endeavours.

KUMMARA BINDHU MADHAV SAI (199E1A04G0)

SIDDA SONALI (199E1A04I3)
SAREDDY MALLESH REDDY (209E5A0419)
B B JATIN KRISHNA (199E1A04D3)
KANNAN CHANDRA SEKHAR (199E1A04F6)
 TABLE OF CONTENTS

Chapter No. Description Page No.

Abstract i
List of Figures ii
List of Tables iii
1 Introduction 1
1.1 History Of Verilog 2
1.2 Design Styles 3
1.3 Features Of Verilog HDL 3
1.4 VLSI Design Flow 4
1.5 Module 6
1.6 Data Types 8
1.7 Operators 8
1.7.1 Arithmetic Operators 9
1.7.2 Relational Operators 9
1.7.3 Bit-wise Operators 9
1.7.4 Logical Operators 10
1.7.5 Reduction Operators 11
1.7.6 Shift Operators 11
1.7.7 Concatenation Operator 11
1.7.8 Operator Precedence 12
1.8 Modeling Concepts 12
1.8.1 Types Of Modeling 13
1.8.2 Blocking and Non-blocking 15
1.8.3 Looping Statements 16
2 Literature Review 18
3 Existing Method 20
3.1 Disadvantages 20
Chapter No. Description Page No.

4 Proposed System 21
4.1 Coin Collector Module 21
4.2 Selector Module 22
4.3 Collection Module 23
4.4 Advantages 23
4.5 Applications 23
5 Software Components 24
5.1 Xilinx Verilog HDL Tutorial 24
5.1.1 Introduction 24
5.1.2 Creating New Project 25
5.1.3 Opening a Project 26
5.1.4 Creating a Verilog HDL input 28
file for combinational logic design
5.1.5 Editing the Verilog source file 30
5.1.6 Synthesis and Implementation of 31
the Design
5.2 Xilinx Simulation Procedure 34

6 Results and Discussion 36

6.1 Simulation Results 36
6.2 Synthesis Results 37
7 Conclusion and Future Scope 38
7.1 Conclusion 38
7.2 Future Scope 38
References 39
Appendix-A 40
 ABSTRACT

This project is a synthesis of practical investigation and theoretical analysis using Verilog
HDL language to research a subway automatic ticket selling system. The design of this subway
ticketing system takes convenience, quickness and simplicity as the core, and takes saving time
for passengers as the guide design. It completes the main process of buying subway tickets for
passengers. Firstly, this project studies the development of subway ticketing system at home and
abroad, and then studies the basic components of subway ticketing system. Through Xilinx ISE
development software to do schematic input mode, this project designs the subway automatic
ticket selling system which composed of selector module, coin calculation module and collection
module. This project also simulates the selector module, coin calculation module and collection
module on Xilinx ISE.

(i)
 LIST OF FIGURES

S .NO. FIGURE NO. DESCRIPTION PAGE NO.

1 Fig 1 VLSI Design Flow 4

2 Fig 4 Block Diagram 21

3 Fig 4.1 Coin Collector Module 22

4 Fig 4.2 Selector Module 22

5 Fig 4.3 Collection Module 23

6 Fig 5.1 Xilinx Project Navigator Window 25

7 Fig 5.2 Create New Project 26

8 Fig 5.3 Device Properties 27

9 Fig 5.4 Create New Source Window 28

10 Fig 5.5 Select Source Type 29

11 Fig 5.6 Define Verilog Source Window 29

12 Fig 5.7 New Project Information Window 30

13 Fig 5.8 Verilog Source Code Editor Window 31

14 Fig 5.9 Implementing the Design 32

15 Fig 5.10 Top Level Hierarchy of the design 33

16 Fig 5.11 Schematic Diagram 33

17 Fig 5.12 Simulation Window 35

18 Fig 5.13 Output Window 35

19 Fig 6.1 Subway Automatic Ticketing System 36

Waveform

20 Fig 6.2 Synthesis Results 37

(ii)
 LIST OF TABLES

S.NO. TABLE NO. DESCRIPTION PAGE NO.

1 1.7.2 Relational Operators 9

2 1.7.3 Bit-wise Operators 10

3 1.7.4 Logical Operators 10

4 1.7.5 Reduction Operators 11

5 1.7.6 Shift Operators 11

6 1.7.8 Operator Precedence 12

(iii)