MP4560
MP4560
DESCRIPTION FEATURES
The MP4560 is a high frequency step-down Wide 3.8V to 55V Operating Input Range
switching regulator with integrated internal high- 250mΩ Internal Power MOSFET
side high voltage power MOSFET. It provides 2A Up to 2MHz Programmable Switching
output with current mode control for fast loop Frequency
response and easy compensation. 140μA Quiescent Current
Ceramic Capacitor Stable
The wide 3.8V to 55V input range accommodates Internal Soft-Start
a variety of step-down applications, including
Up to 95% Efficiency
those in automotive input environment. A 12µA
Output Adjustable from 0.8V to 52V
shutdown mode supply current allows use in
battery-powered applications. Available in 3x3 10-Pin QFN and SOIC8
with Exposed Pad Packages
High power conversion efficiency over a wide
load range is achieved by scaling down the APPLICATIONS
switching frequency at light load condition to High Voltage Power Conversion
reduce the switching and gate driving losses. Automotive Systems
The frequency foldback helps prevent inductor Industrial Power Systems
current runaway during startup and thermal Distributed Power Systems
shutdown provides reliable, fault tolerant Battery Powered Systems
operation. All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
By switching at 2MHz, the MP4560 is able to “MPS” and “The Future of Analog IC Technology” are registered trademarks of
prevent EMI (Electromagnetic Interference) noise Monolithic Power Systems, Inc.
problems, such as those found in AM radio and
ADSL applications.
The MP4560 is available in small 3mm x 3mm
10-pin QFN and SOIC8 with exposed pad
packages.
TYPICAL APPLICATION
Efficiency @VOUT=3.3V
fs=500kHz
100
Vin=12V
90
80
70
EFFICIENCY (%)
60 Vin=55V
50
40
30
20
10
0
0 0.5 1 1.5 2
OUTPUT CURRENT (A)
ORDERING INFORMATION
Part Number Package Top Marking
MP4560DQ* 3x3 QFN10 T8
MP4560DN** SOIC8E MP4560DN
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
SW 1 10 BST
SW 1 8 BST
SW 2 9 VIN
EN 2 7 VIN
EN 3 8 VIN
COMP 3 6 FREQ
COMP 4 7 FREQ
FB 4 5 GND
FB 5 6 GND
EXPOSED PAD
EXPOSED PAD
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2.5V, VCOMP = 1.4V, TA= +25C, unless otherwise noted.
Specifications over temperature are guaranteed by design and characterization.
Parameter Symbol Condition Min Typ Max Units
4.5V < VIN < 55V 0.780 0.800 0.820
Feedback Voltage VFB V
–40°C to +85C 0.772 0.829
VBST – VSW = 5V 175 250 330
Upper Switch On Resistance (5) RDS(ON) mΩ
–40°C to +85C 160 400
Upper Switch Leakage VEN = 0V, VSW = 0V 1 μA
2.6 3.2 4.5
Current Limit A
–40°C to +85C 2.2 4.7
COMP to Current Sense
GCS 5.7 A/V
Transconductance
Error Amp Voltage Gain 400 V/V
Error Amp Transconductance ICOMP = ±3µA 120 µA/V
Error Amp Min Source current VFB = 0.7V 10 µA
Error Amp Min Sink current VFB = 0.9V -10 µA
2.7 3.0 3.3
VIN UVLO Threshold V
–40°C to +85C 2.4 3.6
VIN UVLO Hysteresis 0.35 V
Soft-Start Time (5) 0V < VFB < 0.8V 0.5 ms
RFREQ = 95kΩ 0.8 1 1.2
Oscillator Frequency MHz
–40°C to +85C 0.7 1.3
Minimum Switch On Time 100 ns
Shutdown Supply Current VEN < 0.3V 12 20 µA
Quiescent Supply Current No load, VFB = 0.9V 140 µA
Thermal Shutdown Hysteresis = 20C 150 C
Minimum Off Time 100 ns
Minimum On Time (5) 100 ns
1.4 1.55 1.7
EN Up Threshold V
–40°C to +85C 1.3 1.8
EN Threshold Hysteresis 320 mV
Note:
5) Derived from bench characterization. Not tested in production.
PIN FUNCTIONS
QFN SOIC8
Name Description
Pin # Pin #
Switch Node. This is the output from the high-side switch. A low VF Schottky rectifier
1, 2 1 SW to ground is required. The rectifier must be close to the SW pins to reduce switching
spikes.
Enable Input. Pulling this pin below the specified threshold shuts the chip down.
3 2 EN
Pulling it up above the specified threshold or leaving it floating enables the chip.
Compensation. This node is the output of the GM error amplifier. Control loop
4 3 COMP
frequency compensation is applied to this pin.
Feedback. This is the input to the error amplifier. An external resistive divider
5 4 FB connected between the output and GND is compared to the internal +0.8V reference
to set the regulation voltage.
GND, Ground. It should be connected as close as possible to the output capacitor avoiding
6 5 Exposed the high current switch paths. Connect exposed pad to GND plane for optimal thermal
pad performance.
Switching Frequency Program Input. Connect a resistor from this pin to ground to set
7 6 FREQ
the switching frequency.
Input Supply. This supplies power to all the internal control circuitry, both BS
8, 9 7 VIN regulators and the high-side switch. A decoupling capacitor to ground must be placed
close to this pin to minimize switching spikes.
Bootstrap. This is the positive power supply for the internal floating high-side
10 8 BST
MOSFET driver. Connect a bypass capacitor between this pin and SW pin.
EFFICIENCY (%)
60 Vin=48V
60
50
50
40 Vsw
40
10V/div
30 30
20 20 IL
10 10 500mA/div
0 0
0 0.5 1 1.5 2 0 0.5 1 1.5 2
VOUT VOUT
AC Coupled AC Coupled
10mV/div 10mV/div
Vsw Vsw
10V/div 10V/div
IL IL
1A/div 2A/div
Short Circuit Entry Short Circuit Steady State Short Circuit Recovery
IOUT=0.1A to Short IOUT=Short to 0A
IL IL IL
1A/div 1A/div 2A/div
BLOCK DIAGRAM
VIN
REFERENCE INTERNAL
EN
UVLO REGULATORS
BST
ISW --
LOGIC
0.5ms SS SS +
SW
FB -- COMP
SS
0V8 +
OSCILLATOR
For example, for a 3.3V output voltage, R2 is Where VOUT is the output voltage, VIN is the input
10kΩ, and R1 is 31.6kΩ. voltage, fS is the switching frequency, and ∆IL is
the peak-to-peak inductor ripple current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated by:
VOUT V
ILP ILOAD 1 OUT
2 fS L1 VIN
VOUT V 1
ΔVOUT 1 OUT f Z1
8 fS
2
L C2 VIN
2 π C 3 R 3
In the case of tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the output
ripple can be approximated to:
The system may have another zero of 2. Choose the compensation capacitor (C3) to
importance, if the output capacitor has a large achieve the desired phase margin. For
capacitance and/or a high ESR value. The zero, applications with typical inductor values, setting
due to the ESR and capacitance of the output the compensation zero, fZ1, below one forth of the
capacitor, is located at: crossover frequency provides sufficient phase
margin. Determine the C3 value by the following
1
f ESR equation:
2π C2 R ESR
4
C3
In this case, a third pole set by the compensation 2 π R 3 f C
capacitor (C5) and the compensation resistor (R3)
is used to compensate the effect of the ESR zero 3. Determine if the second compensation
on the loop gain. This pole is located at: capacitor (C5) is required. It is required if the
ESR zero of the output capacitor is located at
1 less than half of the switching frequency, or the
fP3
2 π C 5 R 3 following relationship is valid:
The goal of compensation design is to shape the 1 f
converter transfer function to get a desired loop S
2π C2 R ESR 2
gain. The system crossover frequency where the
feedback loop has the unity gain is important. If this is the case, then add the second
Lower crossover frequencies result in slower line compensation capacitor (C5) to set the pole fP3 at
and load transient responses, while higher the location of the ESR zero. Determine the C5
crossover frequencies could cause system value by the equation:
unstable. A good rule of thumb is to set the
crossover frequency to approximately one-tenth C 2 R ESR
C5
of the switching frequency. R3
determines the input/output ripple voltage at The bootstrap diode can be a low cost one such
higher switching frequency. As a result of that, as IN4148 or BAT54.
high frequency ceramic capacitor is strongly
5V
recommended as input decoupling capacitor and
output filtering capacitor for such high frequency
operation. BST
10
VIN 8,9 BST 1,2 VOUT
VIN SW 1.8V
D1
3 5
EN EN FB
MP4560
7 4
FREQ COMP
C3
GND 680pF
C5
6 NS
C4
100nF
10
VIN 8,9 BST 1,2 VOUT
VIN SW 5V
D1
3 5
EN EN FB
MP4560
7 4
FREQ COMP
C3
GND 330pF
C5
6 NS
MP4560
PACKAGE INFORMATION
3mm x 3mm QFN10 (EXPOSED PAD)
2.90 0.30 1.45 PIN 1 ID
3.10 0.50 1.75 SEE DETAIL A
PIN 1 ID
MARKING
0.18
10 1
0.30
2.90 2.25
PIN 1 ID 2.55
3.10 0.50
INDEX AREA
BSC
6 5
NOTE:
2.90
1) ALL DIMENSIONS ARE IN MILLIMETERS.
0.70 1.70 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
0.25 4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
2.50
0.50
1 4
0.051(1.30)
0.067(1.70)
0.0075(0.19)
SEATING PLANE
0.0098(0.25)
0.000(0.00)
0.013(0.33) 0.006(0.15)
0.020(0.51) SIDE VIEW
0.050(1.27)
BSC
GAUGE PLANE
0.010(0.25) BSC
0.024(0.61) 0.050(1.27)
0.016(0.41)
0o-8o 0.050(1.27)
0.063(1.60)
DETAIL "A"
0.103(2.62) 0.213(5.40)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
0.138(3.51) OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
RECOMMENDED LAND PATTERN 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.