L6981

Datasheet

38 V, 1.5 A synchronous step-down converter with 20 µA quiescent current

Features
• 3.5 V to 38 V operating input voltage
• Output voltage from 0.85 V to VIN
• 3.3 / 5 V fixed output voltage versions
• 1.5 A DC output current
• 20 μA operating quiescent current
• Internal compensation network
SO 8L
• Two different versions: LCM for high efficiency at light-loads and LNM for noise
sensitive applications
• 2 μA shutdown current
• Internal soft-start
• High voltage VIN compatible Enable
• Output overvoltage protection
• Output voltage sequencing
Maturity status link • Thermal protection
L6981 • Synchronization to external clock for LNM devices
• SO8 package

Applications
• Designed for 24 V buses industrial power systems
• 24 V battery powered equipment
• Decentralized intelligent nodes
• Sensors and always-on applications
• Low noise applications
• Smart meters
• Robot cleaner

Description
The L6981 is an easy to use synchronous monolithic step-down regulator capable
of delivering up to 1.5 A DC to the load. The wide input voltage range makes the
device suitable for a broad range of applications. The L6981 is based on a peak
current mode architecture and is packaged in an SO8 with internal compensation,
thus minimizing design complexity and size.
The L6981 is available both in low consumption mode (LCM) and low noise mode
(LNM) versions. LCM maximizes the efficiency at light-load with controlled output
voltage ripple so the device is suitable for battery-powered applications.
LNM makes the switching frequency constant and minimizes the output voltage
ripple for light-load operations, meeting the specification for low noise sensitive
applications.
The EN pin provides output enable/disable functionality. The typical shutdown current
is 2 µA when disabled. As soon as the EN pin is pulled up the device is enabled
and the internal 1.3 ms soft-start takes place. Pulse-by-pulse current sensing on
both power elements implements an effective constant current protection and thermal
shutdown prevents thermal run-away.

DS13554 - Rev 3 - December 2022 www.st.com

For further information contact your local STMicroelectronics sales office.
 L6981
Diagram

1 Diagram

Figure 1. Block diagram

(*) Synchronization is allowed for LNM versions only.

DS13554 - Rev 3 page 2/52

 L6981
Pin configuration

2 Pin configuration

Figure 2. Pin connection (top view)

SW 1 8 PGND

BOOT 2 7 VIN

VCC 3 6 AGND

VOUT/FB 4 5 EN/CLKIN(*)

(*) Synchronization is allowed for LNM versions only.

Table 1. Pin description

Pin # Symbol Function

1 SW Switching node
Connect an external capacitor (100 nF typ.) between BOOT and SW pins. The
2 BOOT gate charge required to drive the internal NMOS is refreshed during the low side
switch conduction time.
This pin supplies the embedded analog circuitry. Connect a ceramic capacitor
3 VCC
(≥ 1 µF) to filter internal voltage reference.
This pin operates as VOUT or FB according to the selected part number. In
fixed output voltage versions, VOUT is the output voltage sensing with selected
4 VOUT/FB
internal voltage divider. In adjustable versions, FB is output voltage sensing with
external voltage divider.
Enable pin with internal voltage divider. Pull down/up to disable/enable the
device.
5 EN/CLKIN
In LNM versions, this pin is also used to provide an external clock signal, which
synchronizes the device.
6 AGND Analog ground
7 VIN DC input voltage
8 PGND Power ground

DS13554 - Rev 3 page 3/52

 L6981
Typical application circuit

3 Typical application circuit

Figure 3. Basic application (adjustable version)

(*) Synchronization is allowed for LNM versions only.

Figure 4. Basic application (fixed VOUT versions)

(*) Synchronization is allowed for LNM versions only.

Table 2. Typical application components

Symbol Value Description

CIN 10 µF Input capacitor

CVCC 1 µF VCC bypass capacitor

CBOOT 100 nF Bootstrap capacitor

COUT 22 µF Output capacitor

R1 400 kΩ VOUT divider upper resistor

R2 82 kΩ VOUT divider lower resistor

L 33 µH Output inductor

DS13554 - Rev 3 page 4/52

 L6981
Absolute maximum ratings

4 Absolute maximum ratings

Stressing the device above the ratings listed in the table below may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or any other conditions above those indicated
in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.

Table 3. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

VIN Maximum pin voltage -0.3 42 V

PGND to AGND Maximum pin voltage -0.3 0.3 V
BOOT Maximum pin voltage SW – 0.3 SW + 4 V
VCC Maximum pin voltage -0.3 Min. (VIN + 0.3 V; 4 V) V
VOUT/FB Maximum pin voltage -0.3 8 V
EN Maximum pin voltage -0.3 VIN + 0.3 V
-0.85 VIN + 0.3 V
SW Maximum pin voltage
-3.9 for 0.5 ns VIN + 0.3 V
IHS, ILS High-side / Low-side RMS switch current 1.5 A
TJ Operating temperature range -40 150 °C

TSTG Storage temperature range -65 150 °C

TLEAD Lead temperature (soldering 10 sec.) 260 °C

Note: All values are referred to AGND unless otherwise specified.

Table 4. ESD performance

Symbol Parameter Test conditions Value Unit

HBM 2 kV
ESD ESD Protection voltage
CDM pins 500 V

Table 5. Thermal data

Symbol Parameter Value Unit

Thermal data: Thermal resistance junction ambient (device soldered

RthJA 65 °C/W
on the STMicroelectronics 2Layer 2-Oz Cu demonstration board)

DS13554 - Rev 3 page 5/52

 L6981
Electrical characteristics

5 Electrical characteristics

Table 6. Electrical characteristics TJ = 25 °C, VIN = 24 V unless otherwise specified.

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VIN Operating input voltage range 3.5 38 V

VINH VCC rising threshold 2.3 3.3 V

VINL VCC UVLO falling threshold 2.15 3.15 V

No slope contribution 2 2.3 A

IPK (1) Peak current limit
Full slope contribution 1.55 1.8 A
IVY Valley current limit 1.7 2 2.3 A

ISKIP (1)(2) Skip current limit 0.35 A

IVY_SINK (1)
Reverse current limit LNM or VOUT overvoltage 1.25 1.5 1.75 A

RDSON_HS High-side RDSON 0.175 Ω

RDSON_LS Low-side RDSON 0.125 Ω

FSW Switching frequency 360 400 440 KHz

TOFF_MIN Minimum OFF time 185 ns

TON_MIN Minimum ON time 85 ns

Enable
Rising 0.7 V
VWAKE_UP Wakeup threshold
Falling 0.2 V
Rising 1.08 1.2 1.32 V
VEN Enable threshold
Hysteresis 0.2 V
VCC regulator
VCC LDO output voltage 3.0 3.3 3.6 V

Power consumption
ISHTDWN Shutdown current from VIN EN = GND 2 3 μA

LCM Device

Quiescent current from VIN (refer to ADJ part number 20 35 60 μA

IQ_VIN
Section 6.5 ) Fix VOUT part number 1 3.5 6 μA

IQ_VOUT Quiescent current from VOUT Fix VOUT part number 20 35 60 μA

LNM Device
ADJ part number 1.6 2.3 3 mA
IQ_VIN Quiescent current from VIN
Fix VOUT part number 300 550 800 μA

IQ_VOUT Quiescent current from VOUT Fix VOUT part number 1.3 1.8 2.3 mA

Soft-start
TSS Internal soft-start 1 1.3 1.6 ms

Error amplifier
Adjustable version TJ = 25 °C 0.845 0.85 0.855 V

VFB Voltage feedback Adjustable version TJ = -40 °C ≤ TJ ≤ 125 °C (3) 0.842 0.85 0.858 V

Fixed 3.3 V version TJ = 25 °C 3.27 3.3 3.33 V

DS13554 - Rev 3 page 6/52

 L6981
Electrical characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Fixed 3.3 V version TJ = -40 °C ≤ TJ ≤ 125 °C

(3)
3.284 3.3 3.346 V

VFB Voltage feedback Fixed 5.0 V version TJ = 25 °C 4.955 5.0 5.045 V

Fixed 5.0 V version TJ = -40 °C ≤ TJ ≤ 125 °C

(3)
4.93 5.0 5.07 V

Overvoltage protection
VOVP Overvoltage trip (VOVP/VREF) 115 120 125 %

VOVP_HYST Overvoltage Hysteresis 1 2 6 %

Synchronization (LNM versions only)

fCLKIN (4) Synchronization range 200 500 KHz

VCLKIN_TH
(4)
Amplitude of synchronization clock 2.3 V

Synchronization pulse ON and OFF

60 ns
time 2.3 ≤ VCLKIN_TH ≤ 2.5 V
VCLKIN_T (4)
Synchronization pulse ON and OFF
20 ns
time VCLKIN_TH > 2.5 V

Thermal Shutdown

TSHDWN (5) Thermal shutdown temperature 165 °C

THYS (5) Thermal shutdown hysteresis 30 °C

1. Parameter tested in the static condition during testing phase. The parameter value may change over a dynamic application condition.
2. LCM version.
3. Specifications in the - 40 to 125 °C temperature range are assured by characterization and statistical correlation.
4. LNM version.
5. Not tested in production.

DS13554 - Rev 3 page 7/52

 L6981
Functional description

6 Functional description

The L6981 device is based on a “peak current mode”, constant frequency control. Therefore, the intersection
between the error amplifier output and the sensed inductor current generates the PWM control signal to drive the
power switch.
The device features LNM (low noise mode) that implements a forced PWM control, or LCM (low consumption
mode) to increase the efficiency at light-load.
The main internal blocks shown in the block diagram in Figure 1 are:
• Embedded power elements
• The ramp for the slope compensation to avoid subharmonic instability
• A transconductance error amplifier with integrated compensation network
• The high-side current sense amplifier to sense the inductor current
• A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements
• The soft-start block ramps up the reference voltage on error amplifier, thus decreasing the inrush current at
power-up. The EN pin inhibits the device when driven low
• The EN/CLK pin section, which for LNM versions, allows synchronizing the device to an external clock
generator
• The pulse-by-pulse high-side / low-side switch current sensing to implement the constant current protection
• A circuit to implement the thermal protection function
• The OVP circuitry to discharge the output capacitor in case of overvoltage event.

6.1 Enable
The EN pin is a digital input that turns the device on or off.
In order to maximize both the EN threshold accuracy and the current consumption, the device implements two
different thresholds:
1. The Wake-Up threshold, VWAKE_UP = 0.5 V (see Table 6)
2. The Start-Up threshold, VEN = 1.2 V (see Table 6)
The following image shows the device behavior.

Figure 5. Power up/down behavior

EN(t)
VEN Rising = 1.2 V

VEN THR. Falling = 1.0 V

V WAKE UP Rising ≈ 0.5V

VWAKE UP THR. Falling ≈ 0.4 V

VCC(t) t
VVCC = 3.3 V

SW(t) t

IVIN (t) t
IS_OPVIN I S_OPVIN

ISHDWN = 2 µA
ISHDWN = 2 µA
t

When the voltage applied on the EN pin rises over VWAKEUP, RISING, the device powers up the internal circuit
increasing the current consumption.

DS13554 - Rev 3 page 8/52

 L6981
Soft-start

As soon as the voltage rises over the VEN, RISING, the device starts the switching activities as described in
Section 6.2 Soft-start.
Once the voltage becomes lower than VEN,FALLING, the device interrupts the switching activities.
As soon as the voltage becomes lower than VWAKEUP,FALLING, the device powers down the internal circuit
reducing the current consumption.
The pin is VIN compatible.
Please refer to Table 6 for the reported thresholds.

6.2 Soft-start
The soft-start (SS) limits the inrush current surge and makes the output voltage increase monotonically.
The device implements the soft-start phase, after 800 μs typical tsetup delay, ramping the internal reference with
very small steps. Once the SS ends, the Error Amplifier reference is switched to the internal value of 0.85 V
coming directly from the band gap cell.

Figure 6. Soft-start procedure

EN(t)
VEN Rising =1.2V

t
VCC(t) VVCC = 3.3V

SW(t) t

VREF =0.85V
EA Reference(t) t

t
tSETUP tSS = 1.3ms

During normal operation, a new soft-start cycle takes place in case of:
1. Thermal shutdown event
2. UVLO event
3. EN pin rising over VEN threshold. Please refer to Table 6.

DS13554 - Rev 3 page 9/52

 L6981
Undervoltage lockout

Figure 7. Soft-start phase with IOUT = 1.25 A

6.3 Undervoltage lockout

The device implements the undervoltage lockout (UVLO) continuously sensing the voltage on the VCC pin, if the
UVLO lasts more than 10 μs, the internal logic resets the device by turning off both LS and HS.
After the reset, if the EN pin is still high, the device repeats the soft-start procedure.

6.4 Light-load operation

The L6981 implements two different light-load strategies:
1. Low consumption mode (LCM).
2. Low noise mode (LNM).
Please refer to Table 11 to select the part number with the preferred light-load strategy.

6.4.1 Low consumption mode (LCM)

The LCM maximizes the efficiency at light-load.
When the switch peak current request is lower than the ISKIP threshold (please refer to Electrical characteristics
table), the device regulates VOUT by the skip threshold. The minimum voltage is given by:
R + RPL
VOUT, LCM = VFB, LCM ∙ PHR (1)
PL
Where VFB, LCM is 1.8% (typ.) higher than VFB.
The device interrupts the switching activities when two conditions happen together:
1. The peak inductor current required is lower than ISKIP.
2. The voltage on the FB pin is higher than VFB, LCM.

DS13554 - Rev 3 page 10/52

 L6981
Light-load operation

Figure 8. Light-load operation

A new switching cycle takes place once the voltage on the FB pins becomes lower than VFB,LCM.
The HS switch is kept on until the inductor current reaches ISKIP.
Once the current on the HS reaches the defined value, the device turns the HS off and turns the LS on. The LS is
kept enabled until one of the following conditions occurs:
1. The inductor current sensed by the LS becomes equal to zero.
2. The switching period ends.
If, at the end of the switching cycle, the voltage on the FB pin rises over the VFB,LCM threshold, the LS is kept
enabled until the inductor current becomes equal to zero. Otherwise, the device turns on the HS again and starts
a new switching pulse.
During the burst pulse, if the energy transferred to COUT increases the VFB level over the threshold defined in
Equation 1, the device interrupts the switching activities. The new cycle takes place only when VFB becomes
lower than the defined threshold. Otherwise, as soon as the LS is turned off, the HS is turned on.
Given the energy stored in the inductor during a burst, the voltage ripple depends on the capacitor value:
T
∆ QIL ∫0 BURST IL t dt
VOUT RIPPLE = C = (2)
OUT COUT

Figure 9. LCM operation with ISKIP = 350 mA typ. at zero load. L = 33 μH; COUT = 32 μF

DS13554 - Rev 3 page 11/52

 L6981
Light-load operation

Figure 10. LCM operation at zero load condition (part 1-pulse skipping)

Figure 11. LCM operation over 15 mA load condition (part 2-pulse skipping)

DS13554 - Rev 3 page 12/52

 L6981
Light-load operation

Figure 12. LCM operation over 100 mA load condition (part 3-pulse skipping)

Figure 13. LCM operation over 190 mA load condition (part 4-CCM)

DS13554 - Rev 3 page 13/52

 L6981
Light-load operation

6.4.2 Low noise mode (LNM)

The low noise mode implements a forced PWM operation over the different loading conditions. The LNM features
a constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed
VIN.
The regulator in steady loading condition operates in continuous conduction mode (CCM) over the different
loading conditions.
The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output
voltage ripple, that depends on the capacitor value and the equivalent resistive component (ESR). Consequently,
the output capacitor has to be selected in order to have a voltage ripple compliant with the application
requirements.
∆ ILMAX
VOUT RIPPLE = ESR ∙ ∆ ILMAX + (3)
8 ∙ COUT ∙ fSW

Usually the resistive component of the ripple can be neglected if the selected output capacitor is a multi-layer
ceramic capacitor (MLCC).

Figure 14. Low noise mode operation at zero load

DS13554 - Rev 3 page 14/52

 L6981
Light-load operation

6.4.3 Efficiency for Low consumption mode and Low noise mode part number
Figure 15 and Figure 16 report the efficiency measurements to highlight the gap at the light-load between LNM
and LCM part numbers. The graph reports also the same efficiency at the medium / high load.

Figure 15. Light-load efficiency for low consumption mode and low noise mode - linear scale. VIN = 24 V;
VOUT = 5 V; FSW = 400 KHz.

100
90
80
Efficiency [%]

70
60
50
40
30 LCM
20 LNM
10
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4

IOUT [A]

Figure 16. Light-load efficiency for low consumption mode and low noise mode - log scale. VIN = 24 V;
VOUT = 5 V; FSW = 400 KHz.

100
90
80
70
Efficiency [%]

60
50
40
30
20 LCM
10 LNM
0
0.0001 0.001 0.01 0.1 1

IOUT [A]

DS13554 - Rev 3 page 15/52

 L6981
Switch-over feature (fixed VOUT part numbers only)

6.4.4 Load regulation for low consumption mode and low noise mode part number
Figure 17 and Figure 18 report the load regulation to highlight the gap, given by the different regulation strategy,
at the light-load between LNM and LCM part numbers. When the required IOUT is higher than the threshold
defined in the Low consumption mode (LCM) paragraph, the behavior of the different part numbers is the same.

Figure 17. Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 KHz - linear scale

2.5
LCM
2
Load regulation [%]

LNM
1.5

0.5

-0.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4

IOUT [A]

Figure 18. Load regulation for LCM and LNM part numbers. VIN = 24 V; VOUT = 5 V; FSW = 400 KHz - log
scale

2.5

2 LCM
Load regulation [%]

1.5 LNM

0.5

-0.5
0.0001 0.001 0.01 0.1 1

IOUT [A]

6.5 Switch-over feature (fixed VOUT part numbers only)

The Switch-Over maximizes the efficiency at light-load that is crucial for LCM applications.
In order to minimize the regulator quiescent current sunk from the input voltage on fixed VOUT part number the
internal circuitry are supplied from VOUT pin.
The total current drawn from the input voltage is given by:
V
IQVIN = IQOPVIN + η 1 ∙ OUT ∙ IQVOUT (4)
L6981 VIN

DS13554 - Rev 3 page 16/52

 L6981
Output overvoltage protection

6.6 Output overvoltage protection

The overvoltage is a second level protection, and it should never be triggered in normal operating conditions if the
system is properly dimensioned. In other words, the selection of the external power components and the dynamic
performance determined by the compensation network should guarantee an output voltage regulation within the
overvoltage threshold even during the worst-case scenario in terms of load transitions. The protection is reliable
and able to operate even during normal load transitions for a system whose dynamic performance is not in line
with the load dynamic request. Consequently, the output voltage regulation would be affected.

6.6.1 Low consumption mode part numbers

The overvoltage protection continuously compares the FB pin with 120% nominal output voltage and enables
the low-side MOSFET at the beginning of the switching cycle keeping it active until 1.5 A typ. negative current
limitation is reached, in order to discharge the output capacitor.
The following graph shows the LCM part number behavior during an OVP event.

Figure 19. OVP event low consumption mode part number

VOUT (t)

VOVP
VOVP_HYST

VOUT, LCM
t
Isw(t)

ISKIP
t
ISKIP_LNM

IVY_SINK
SW(t)
VIN
VOUT
t
Body Diode HS
TON,min LS

As soon as the output voltage goes out of the OVP hysteresis (typ. 2%) the L6981 device sets the switching node
on high impedance. It restarts the switching activity accordingly with the main loop regulation of the peak current
mode architecture.

DS13554 - Rev 3 page 17/52

 L6981
Overcurrent protection

6.6.2 Low noise mode part numbers

The following graph shows the LNM part number behavior during an OVP event.

Figure 20. OVP event low noise mode part numbers

The LNM device regulates the output voltage with valley sinking capability down to the negative current limitation
(IVY_SINK in Figure OVP Event Low Noise Mode part number). This hysteretic operating mode between peak
current mode threshold (ISKIP_LNM) and modulated low side switch conduction time for VOUT regulation
persists until the valley current level triggers the negative current limitation (IVY_SINK), that is the maximum
sinking capability of the device (highlighted in green in Figure 20).
If the source injection further increases, the output voltage is a partitioning between source impedance and
maximum sinking capability above described (highlighted in blue in Figure 20).

6.7 Overcurrent protection

The current protection circuitry features a constant current protection, so the device limits the maximum peak
current (please refer to Table 6) in an overcurrent condition.
The L6981 device implements a pulse-by-pulse current sensing on both power elements (high-side and low-side
switches) for effective current protection over the duty cycle range. The high-side current sensing is called “peak”,
the low-side sensing “valley”.
The internal noise generated during the switching activity makes the current sensing circuitry ineffective for a
minimum conduction time of the power element. This time is called “masking time” because the information from
the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. Therefore,
the peak current protection is disabled for a masking time after the high-side switch is turned on. The masking
time for the valley sensing is activated after the low-side switch is turned on. In other words, the peak current
protection can be ineffective at extremely low duty cycles, the valley current protection at extremely high duty
cycles.
The L6981 device assures an effective overcurrent protection sensing the current flowing in both power elements.
In case one of the two current sensing circuitries is ineffective because of the masking time, the device is
protected, sensing the current on the opposite switch. Thus, the combination of the “peak” and “valley” current
limits assure the effectiveness of the overcurrent protection even in extreme duty cycle conditions.

DS13554 - Rev 3 page 18/52

 L6981
Overcurrent protection

In case the current diverges because of the high-side masking time, the low-side power element is turned on until
the switch current level drops below the valley current sense threshold. The low-side operation is able to prevent
the high-side turn-on, so the device can skip pulses decreasing the switching frequency.

Figure 21. Overcurrent protection behavior

In a worst case scenario, reported in Figure 21 of the overcurrent protection, the switch current is limited to:
V − VOUT
IMAX = IVY + IN ∙ TMASKHS (5)
L
Where IVY is the current threshold of the valley sensing circuitry (please refer to Electrical characteristics table)
and TMASKHS is the masking time of the high-side switch.
In most of the overcurrent conditions, the conduction time of the high-side switch is higher than the masking time
and so the peak current protection limits the switch current.
IMAX = IPEAKTH (6)

The DC current flowing in the load in overcurrent condition is:

I V VIN − VOUT
IDCOUT = IMAX − RIPPLE2 OUT = IMAX − ∙ TON (7)
2∙L

DS13554 - Rev 3 page 19/52

 L6981
Thermal shutdown

Figure 22 shows the L6981 soft-start procedure with VOUT shorted to GND.

Figure 22. Soft-start procedure with VOUT shorted to GND

Figure 23 shows the L6981 over current protection with a persistent short-circuit between VOUT and GND.

Figure 23. Over current procedure with persistent short circuit between VOUT and GND

6.8 Thermal shutdown

The shutdown block disables the switching activity if the junction temperature is higher than a fixed internal
threshold (TSHDWN refer to Table 6). The thermal sensing element is close to the power elements, ensuring fast
and accurate temperature detection. A hysteresis of approximately 30 °C prevents the device from turning ON
and OFF too fast. After a thermal protection event has expired, the L6981 restarts with a new soft-start.

DS13554 - Rev 3 page 20/52

 L6981
Closing the loop

7 Closing the loop

The following image shows the typical compensation network required to stabilize the system.

Figure 24. Block diagram of the loop

7.1 GCO(s) control to output transfer function

The accurate control to output transfer function for a buck peak current mode converter can be written as:

1 + ωs
1 Z ∙F
GCO s = RLOAD ∙ gCS ∙ ∙ H (8)
RLOAD ∙ TSW s
1+ ∙ mC ∙ 1 − D − 0.5 1 +
L ωP

Where RLOAD represents the load resistance, gCS the equivalent sensing trans-conductance of the current sense
circuitry, ωP the single pole introduced by the power stage and ωZ the zero given by the ESR of the output
capacitor. FH (s) accounts the sampling effect performed by the PWM comparator on the output of the error
amplifier that introduces a double pole at one half of the switching frequency.

ωZ = ESR ∙1C (9)

OUT

1 mC ∙ 1 − D − 0.5
ωP = R + (10)
LOAD ∙ COUT L ∙ COUT ∙ fSW

Where:
S
mC = 1 + Se
n
Se = ISLOPE ∙ fSW (11)
VIN − VOUT
Sn = L
Where ISLOPE is equal to 1 A.

DS13554 - Rev 3 page 21/52

 L6981
Error amplifier compensation network

Sn represents the ON time slope of the sensed inductor current, Se the ON time slope of the external ramp that
implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50 %.
The sampling effect contribution FH (s) is:

FH s = 1 (12)
s s2
1+ ω ∙Q + 2
n P ωn

Where:
1
QP = (13)
π ∙ mC ∙ 1 − D − 0.5

7.2 Error amplifier compensation network

The following figure shows the typical compensation network required to stabilize the system.

Figure 25. Trans-conductance embedded error amplifier

RC and CC introduce a pole and a zero in the open loop gain. The transfer function of the error amplifier and its
compensation network is:
AVO ∙ 1 + s ∙ RC ∙ CC
AO s = 2 (14)
s ∙ RO ∙ CO ∙ RC ∙ CC + s ∙ RO ∙ CC + RO ∙ CO + RC ∙ CC + 1

DS13554 - Rev 3 page 22/52

 L6981
Voltage divider (Adjustable part number)

Where:
AVO = Gm ∙ RO (15)

The poles of this transfer function are (if CC » CO):

1
fPLF = 2 ∙ π ∙ R (16)
O ∙ CC
1
fPHF = 2 ∙ π ∙ R (17)
O ∙ CO
Whereas the zero is defined as:
1
fZ = 2 ∙ π ∙ R (18)
C ∙ CC

7.3 Voltage divider (Adjustable part number)

The contribution of a simple voltage divider is:
R
GDIV s = R +2R (19)
1 2
A small signal capacitor in parallel to the upper resistor (only for the adjustable part number) of the voltage divider
implements a leading network (fZERO < fPOLE), sometimes necessary to improve the system phase margin:

Figure 26. Leading network example

(*) Synchronization is allowed for LNM versions only.

Laplace transformer of the leading network:
R2 1 + s ∙ R1 ∙ CR1
GDIV s =
R1 + R2 ∙
(20)
R ∙R
1 + s ∙ R 1+ R2 ∙ CR1
1 2

fZ = 2 ∙ π ∙ R1 ∙ C (21)
1 R1
1
fP = (22)
R1 ∙ R2
2 ∙ π ∙ R + R ∙ CR1
1 2
fZ < fP (23)

So closing the loop, the loop gain is:

G s = GDIV s ∙ GCO s ∙ AO s (24)

DS13554 - Rev 3 page 23/52

 L6981
Design of the power components

8 Design of the power components

8.1 Programmable power up threshold

The Enable rising threshold is equal to 1.2 V typical (refer to Table 6). The power up threshold is adjusted
accordingly with the following equation:
R
VPower Up = 1.2 ∙ 1 + REN H (25)
EN L

Figure 27. Leading network example

(*) Synchronization is allowed only for LNM versions.

The Enable falling threshold is equal to 1.0 V typical (refer to Electrical characteristics table). The turn off
threshold is obtained accordingly with the following equation:
R
VPower Down = 1.0 ∙ 1 + REN H (26)
EN L

8.2 External synchronization (only available for Low Noise Mode)

The device allows a direct connection between a clock source and the EN/CLKIN pin.

Figure 28. External synchronization. Direct connection

(*) Synchronization is allowed only for LNM versions.

The device internally implements a low pass filter connected to EN/CLKIN pin that is able to acquire the average
value of the applied signal.

DS13554 - Rev 3 page 24/52

 L6981
Output voltage adjustment (Adjustable part number)

The device turns on when the average of the signal applied is higher than VEN rising (refer to Table 6). The device
turns off when the average of the signal should be lower than VEN falling (refer to Table 6).
Considering, for example, a clock source with VPP = 5.0 V, the minimum duty cycle to guarantee the power-up is
given by:
VEN, TH Rising
Dutymin = = 0.24 (27)
VPP

The maximum duty cycle to guarantee the turn off is given by:
VEN, TH Falling
DutyMAX, = = 0.2 (28)
VPP

The device allows also the AC coupling.

Figure 29. External synchronization. AC coupling

(*) Synchronization is allowed only for LNM versions.

The AC-coupling allows the device to keep the power-up and down thresholds defined by the partition connected
to the EN/CLKIN pin and described in the "Programmable power up threshold" section.
The following table resumes the minimum pulse duration and maximum duty cycle that allow the synchronization,
keeping the selected power-up and down thresholds.

Table 7. External synchronization AC coupling suggested operation range

VPP [V] TON,MIN [ns] DMAX [%]

2.3 70 45
3.3 20 30
5 20 20

The minimum amplitude for the external clock signal is, for both configurations, equal to 2.3 V.
The network given by CEN and RENL sets a high pass filter. Considering a resistor in the order of 220 KΩ, a
capacitor equal to 1 nF is a correct choice.

8.3 Output voltage adjustment (Adjustable part number)

The error amplifier reference voltage is 0.85 V typical (refer to Table 6). The output voltage is adjusted accordingly
with the following equation:
R
VOUT = 0.85 ∙ 1 + R1 (29)
2

DS13554 - Rev 3 page 25/52

 L6981
Design of the power components

CR1 capacitor is sometimes useful to increase the small signal phase margin (please refer to Section 7 Closing
the loop)

Figure 30. Application circuit

(*) Synchronization is allowed only for LNM versions.

8.4 Design of the power components

8.4.1 Input capacitor selection

The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.
During the switching activity a pulsed current flows into the input capacitor and so, its RMS current capability must
be selected accordingly with the application conditions. Internal losses of the input filter depend on the ESR value,
so usually low ESR capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the
other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher
conversion efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:

1− D D
IRMS = IOUT ∙ η ∙ η
(30)

Where IOUT is the maximum DC output current, D is the duty cycles, η is the efficiency. This function has a
maximum at D = 0.5 and, considering η = 1, it is equal to IOUT/2. In a specific application, the range of possible
duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and
minimum duty cycles can be calculated as:
VOUT + ∆ VLOWSIDE
DMAX = V (31)
INmin + ∆ VLOWSIDE − ∆ VHIGHSIDE
VOUT + ∆ VLOWSIDE
Dmin = V (32)
INMAX + ∆ VLOWSIDE − ∆ VHIGHSIDE
Where ΔVHIGHSIDE and ΔVLOWSIDE are the voltage drops across the embedded switches. The peak-to-peak
voltage across the input filter can be calculated as:
I
VPP = C OUT ∙ 1− D D
η ∙ η + ESR ∙ IOUT + ∆ IL
(33)
IN ∙ FSW
In case of negligible ESR (MLCC capacitor), the equation of CIN as a function of the target VPP can be written as
follows:
I
CIN = V OUT ∙ 1− D D
η ∙ η
(34)
PP ∙ FSW
Considering η = 1 this function has its maximum in D = 0.5:

DS13554 - Rev 3 page 26/52

 L6981
Design of the power components

I
CINmin = 4 ∙ V OUT ∙ F (35)
PPMAX SW
Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage across the input filter in the order of 5 %
VINMAX.
In the following table, some suitable capacitor part numbers are listed.

Table 8. Input capacitors

Manufacturer Series Size Cap value (µF) Rated voltage (V)

TDK CGA5L3X5R1H106K160AB 1206 10 50

C3216X5R1H106K160AB 1206 10 50
Murata GRT31CR61H106KE01 1206 10 50

8.4.2 Inductor selection

The inductor current ripple flowing into the output capacitor determines the output voltage ripple. Usually the
inductor value is selected in order to keep the current ripple lower than 20% - 40% of the output current over the
input voltage range. The inductance value can be calculated by the following equation:
VIN − VOUT V
∆ IL = ∙ TON = OUT
L ∙ TOFF (36)
L
Where TON and TOFF are the ON and OFF time of the internal power switch. The maximum current ripple, at fixed
VOUT, is obtained at maximum TOFF that is at minimum duty cycle. So fixing ΔIL = 20% to 40% of the maximum
output current, the minimum inductance value can be calculated:
V 1−D
Lmin = ∆ ILOUT ∙ F min (37)
MAX SW
For those applications requiring higher inductor value for minimized current ripple, pay attention as the
maximum value must prevent the sub-harmonic instability given the designed internal slope compensation. As
a consequence the inductor value must satisfy the quality factor range:
0.4 ≤ QP ≤ 1.33 (38)

Where QP has been defined in Section 7.1 GCO(s) control to output transfer function. The peak current through
the inductor is given by:
∆I
IL, PK = IOUT + L (39)
2
So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device)
increases. The higher the inductor value, the higher the average output current that can be delivered, without
reaching the current limit.

8.4.3 Output capacitor selection

The triangular shaped current ripple (with zero average value) flowing into the output capacitor gives the
output voltage ripple, which depends on the capacitor value and the equivalent resistive component (ESR).
Therefore, the output capacitor has to be selected in order to have a voltage ripple compliant with the application
requirements.
The voltage ripple equation can be calculated as:
∆ IL, MAX
∆ VOUT = ESR ∙ ∆ IL, MAX + (40)
8 ∙ COUT ∙ FSW

For a ceramic (MLCC) capacitor, the capacitive component of the ripple dominates the resistive one. While for
an electrolytic capacitor the opposite is true. Neglecting the ESR contribution, the minimum value of the output
capacitor is given by:
∆ IL, MAX
COUT, min, RIPPLE = (41)
8 ∙ ∆ VOUT ∙ FSW

DS13554 - Rev 3 page 27/52

 L6981
Design of the power components

As the compensation network is internal, the output capacitor should be selected in order to have a proper phase
margin and then a stable control loop. A good rule to obtain a proper dimensioning for the minimum amount of the
output capacitor is to set the target system bandwidth equal to FSW/10. The following equation takes into account
the precedent consideration:

COUT, BW, min = F 4.02 (42)

SW
10 ∙ VOUT
The maximum amount of the output capacitor is given by:

∙ 10−3
COUT, BW, MAX = 0.48 (43)
VOUT

DS13554 - Rev 3 page 28/52

 L6981
Application board

9 Application board

The figure below shows the reference evaluation board schematic:

Figure 31. Evaluation board schematic

L1 MSS1038T-333M
L
L2

n.m.

L1 33mH TP6

C13 R6
C4 C5 C6 VOUT
n.m. n.m. 22mF 10mF n.m.
U1
TP1 EN
EN 1 8
SW PGND
C7 R1
2 7 VIN _L6981
TP2 BOOT VIN
C9
CLK_IN 100nF 0 Ohm 3 6
n.m. VCC AGND C2 C1
R4
4 5 1mF 10mF
FB EN/ SY NC 10k
C3
J1 J2 1mF 10V EN
L6981CDR
R5
L3 L4 R3 n.m.
TP3 VIN _L6981 R2 402K
VIN
MPZ2012S221A 4.7mH
82.5K
C11 C12 C14 C10
+ C8
4.7mF 4.7mF 4.7mF n.m.
10pF

TP5
TP4
GND

GND

EMI FIlters. Optional Component

s

The additional input filter (C11, L3, C12, L4, C14 and C10) limits the conducted emission on the power supply.

DS13554 - Rev 3 page 29/52

 L6981
Application board

Table 9. Bill of material

Reference Part number Description Manufacturer

C1 C3216X7R1H106K160AC 10 µF TDK
C2 CGA4J3X7R1H105K125AB 1 µF TDK
C3 1 µF
C4 GRJ32EC71E226KE11 22 µF Murata
C6 n.m.
C5 C3216X7R1H106K160AC 10 µF TDK
C7 100 nF
C8 10 pF
C9 n.m.
C10 n.m.
C11, C12, C14 GRM31CR71H475KA12 4.7 µF Murata
C13 n.m.
L1 MSS1038T-333ML 33 µH Coilcraft
L2 n.m.
L3 MPZ2012S221AT000 220 Ω, 100 MHz TDK
L4 XAL4030-472ME 4.7 µH Coilcraft
R1 0Ω
R2 402 kΩ
R3 82.5 kΩ
R4 10 kΩ
R5 n.m.
R6 n.m.
U1 L6981 STMicroelectronics

DS13554 - Rev 3 page 30/52

 L6981
Application board

Figure 32. Top layer

Figure 33. Bottom layer

DS13554 - Rev 3 page 31/52

 L6981
Efficiency curves

10 Efficiency curves

The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, selecting the following output filter:
• COUT:
– 1 x GRJ32EC71E226KE11 22 µF 16 V (Murata)
– 1 x C3216X7R1H106K160AC 10 µF 50 V (TDK)
• Inductor:
– MSS1038T-333ML (Coilcraft)
• C8:
– 10 pF

Figure 34. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz

100
90
80
Efficiency [%]

70
60
50
40 Vout = 5 [V] Fix. LCM

30 Vout = 5 [V] Fix. LNM

20 Vout = 5 [V] Adj. LCM
10 Vout = 5 [V] Adj. LNM
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4

IOUT [A]

Figure 35. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz (log scale)

100
90
80
70
Efficiency [%]

60
50
40
Vout = 5 [V] Fix. LCM
30
Vout = 5 [V] Fix. LNM
20
Vout = 5 [V] Adj. LCM
10 Vout = 5 [V] Adj. LNM
0
0.0001 0.001 0.01 0.1 1
I OUT [A]

DS13554 - Rev 3 page 32/52

 L6981
Efficiency curves

Figure 36. Power losses VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz

1 8
0.9 Vout = 5[V] Fix. LCM
7
0.8 Vout = 5[V] Fix LNM
6
Power losses [W]

0.7 Vout = 5 [V] Adj. LCM

Vout = 5[V] Adj. LNM 5

POUT [W]
0.6
Pout
0.5 4
0.4 3
0.3
2
0.2
0.1 1
0 0
0 0.5 1 1.5
IOUT [A]

The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, selecting the following output filter:
• COUT:
– 1 x GRJ32EC71E226KE11 22 µF 16 V (Murata)
– 1 x C3216X7R1H106K160AC 10 µF 50 V (TDK)
• Inductor:
– MSS1038T-333ML (Coilcraft)
• C8:
– 10 pF

Figure 37. Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHz

100
90
80
70
Efficiency [%]

60
50 Vout = 5 [V] Fix. LCM
40 Vout = 5 [V] Fix. LNM
30
Vout = 5 [V] Adj. LCM
20
10 Vout = 5 [V] Adj. LNM

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
I OUT [A]

DS13554 - Rev 3 page 33/52

 L6981
Efficiency curves

Figure 38. Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHz (log scale)

100
90
80
70
Efficiency [%]

60
50 Vout = 5[V] Fix. LCM
40
Vout = 5[V] Fix. LNM
30
20 Vout = 5 [V] Adj. LCM
10 Vout = 5[V] Adj. LNM
0
0.0001 0.001 0.01 0.1 1

IOUT [A]

Figure 39. Power losses VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHz

0.8 8
Vout = 5 [V] Fix. LCM
0.7 7
Vout = 5 [V] Fix. LNM
Power losses [W]

0.6 Vout = 5 [V] Adj.LCM 6

0.5 5

POUT [W]
Vout = 5 [V] Adj. LNM

0.4 Pout 4
0.3 3
0.2 2
0.1 1
0 0
0 0.5 1 1.5
IOUT [A]

The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, selecting the following output filter:
• COUT:
– 1 x GRJ32EC71E226KE11 22 µF 16 V (Murata)
– 1 x C3216X7R1H106K160AC 10 µF 50 V (TDK)
• Inductor:
– MSS1038T-223ML (Coilcraft)
• C8:
– 10 pF

DS13554 - Rev 3 page 34/52

 L6981
Efficiency curves

Figure 40. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHz

100
90
80
70
Efficiency [%]

60
50 Vout = 3.3 [V] Fix. LCM
40
Vout = 3.3[V] Fix LNM
30
Vout = 3.3 [V] Adj. LCM
20
10 Vout = 3.3 [V] Adj. LNM
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4

I OUT [A]

Figure 41. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHz (log scale)

100
90
80
70
Efficiency [%]

60
50
40 Vout = 3.3 [V] Fix. LCM
30 Vout = 3.3[V] Fix LNM
20 Vout = 3.3 [V] Adj. LCM
10 Vout = 3.3 [V] Adj. LNM
0
0.0001 0.001 0.01 0.1 1

IOUT [A]

DS13554 - Rev 3 page 35/52

 L6981
Efficiency curves

Figure 42. Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHz

0.8 6
Vout = 3.3 [V] Fix. LCM
0.7
Vout = 3.3[V] Fix LNM 5
Power losses [W]

0.6
Vout = 3.3 [V] Adj. LCM
4

POUT [W]
0.5 Vout = 3.3 [V] Adj. LNM
0.4 Pout 3
0.3
2
0.2
1
0.1
0 0
0 0.5 1 1.5

I OUT [A]

The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, selecting the following output filter:
• COUT:
– 1 x GRJ32EC71E226KE11 22 µF 16 V (Murata)
– 1 x C3216X7R1H106K160AC 10 µF 50 V (TDK)
• Inductor:
– MSS1038T-223ML (Coilcraft)
• C8:
– 10 pF

Figure 43. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHz

100
90
80
70
Efficiency [%]

60
50 Vout = 3.3 [V] Fix. LCM
40
Vout = 3.3[V] Fix LNM
30
Vout = 3.3 [V] Adj. LCM
20
10 Vout = 3.3 [V] Adj. LNM

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4

I OUT [A]

DS13554 - Rev 3 page 36/52

 L6981
Efficiency curves

Figure 44. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHz (log scale)

100
90
80
70
Efficiency [%]

60
50
40
Vout = 3.3 [V] Fix. LCM
30
Vout = 3.3[V] Fix LNM
20
Vout = 3.3 [V] Adj. LCM
10
Vout = 3.3 [V] Adj. LNM
0
0.0001 0.001 0.01 0.1 1

IOUT [A]

Figure 45. Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHz

0.9 6
Vout = 3.3 [V] Fix. LCM
0.8
Vout = 3.3[V] Fix LNM 5
0.7
Power losses [W]

Vout = 3.3 [V] Adj. LCM

0.6 4

POUT [W]
Vout = 3.3 [V] Adj. LNM
0.5
Pout 3
0.4
0.3 2
0.2
1
0.1
0 0
0 0.5 1 1.5

I OUT [A]

DS13554 - Rev 3 page 37/52

 L6981
Thermal dissipation

11 Thermal dissipation

The thermal design is important in order to prevent thermal shutdown of the device if junction temperature goes
above 165°C. The three different sources of losses within the device are:
• Conduction losses due to the ON resistance of the high-side switch (RDSON_HS) and low-side switch
(RDSON_LS); these are equal to:

PCOND = RDSON_HS ∙ I2 2
OUT ∙ D + RDSON_LS ∙ IOUT ∙ 1 − D (44)

Where D is the duty cycle of the selected application and is given by:

VOUT + RDSON_LS + DCRl ∙ IOUT

D= (45)
VIN − RDSON − RDSON_LS ∙ IOUT
HS
In order to obtain a more accurate estimation it is necessary to keep in mind that the amount of resistance of the
internal power MOSFET increases with the temperature. For this reason, the value of RDSONHS and RDSONLS,
should be increased from the typical of a factor equal to 20%.
• Switching losses due to high-side Power MOSFET turn ON and OFF; these can be calculated as:

TRISE + TFALL
PSW = VIN ∙ IOUT ∙ FSW = VIN ∙ IOUT ∙ TSW ∙ FSW (46)
2
Where TRISE and TFALL are the overlap times of the voltage across the high-side power switch (VDS) and
the current flowing into it during turn ON and turn OFF phases, as shown in Figure 46. TSW is the equivalent
switching time. For this device the typical value for the equivalent switching time is 30 ns.
• Quiescent current losses, calculated as:
PQ = VIN ∙ IQ, MAX (47)

The quiescent current for constant current operation is equal to 3 [mA]:

The power losses are given by:
PLOSS = PCOND + PSW + PQ (48)

The junction temperature TJ can be calculated as:

T J = TA + RtℎJA ∙ PLOSS (49)

Where TA is the ambient temperature. RthJA is the equivalent thermal resistance junction to ambient of the device;
it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this
device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA measured
on the demonstration board described in the following section is about 65 °C/W.

DS13554 - Rev 3 page 38/52

 L6981
Thermal dissipation

Figure 46. Switching losses

It is also possible to estimate the junction temperature directly from the efficiency measurements acquired on a
stationary application condition.
Considering that the power losses are given by:
PLOSS = PIN − POUT (50)

Neglecting the AC losses of the selected inductor, the power losses related to the L6981 are given by:
2
PLOSS L6981 = VIN ∙ IIN − VOUT ∙ IOUT − DCRl ∙ IOUT (51)

Consequently, the junction temperature TJ can be calculated as:

T J = TA + RtℎJA ∙ PLOSS, L6981 (52)

DS13554 - Rev 3 page 39/52

 L6981
Package information

12 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

DS13554 - Rev 3 page 40/52

 L6981
SO 8L package information

12.1 SO 8L package information

Figure 47. SO 8L package outline

SIDE VIEW

SIDE VIEW

TOP VIEW

DS13554 - Rev 3 page 41/52

 L6981
SO 8L package information

Table 10. SO 8L mechanical data

mm
Sym.
Min. Typ. Max.

A - - 1.75
A1 0.10 - 0.225
A2 1.30 1.40 1.50
A3 0.60 0.65 0.70
b 0.39 - 0.47
b1 0.38 0.41 0.44
c 0.20 - 0.24
c1 0.19 0.20 0.21
D 4.80 4.90 5.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27BSC
L1 1.05REF
h 0.25 - 0.50
L 0.50 - 0.80
ϴ 0 - 8°

Figure 48. SO 8L recommended footprint

DS13554 - Rev 3 page 42/52

 L6981
SO 8L packing information

12.2 SO 8L packing information

Figure 49. SO 8L tape outline

DS13554 - Rev 3 page 43/52

 L6981
SO 8L packing information

Figure 50. SO 8L reel outline

DS13554 - Rev 3 page 44/52

 L6981
Ordering information

13 Ordering information

Table 11. Order codes

Part numbers Output voltage Light-load behavior Package Packaging

L6981CDR Adjustable
L6981C33DR 3.3 V LCM (Low Consumption Mode)
L6981C50DR 5V
SO 8L Tape and reel
L6981NDR Adjustable
L6981N33DR 3.3 V LNM (Low Noise Mode)
L6981N50DR 5V

DS13554 - Rev 3 page 45/52

 L6981

Revision history
Table 12. Document revision history

Date Version Changes

15-Jan-2020 1 First release.

Updated title and added features on the cover page.
Updated LCM device, LNM device, Error amplifier and Voltage feedback
in Table 6.

25-Jul-2022 2 Added new Figure 4, Section 6.5 , Section 12.2 and new part numbers in
Table 11.
Updated Figure 29, Figure 34, Figure 35, Figure 36, Figure 37, Figure
38, Figure 39, Figure 40, Figure 41, Figure 42, Figure 43, Figure 44 and
Figure 45.
Updated Figure 5. Power up/down behavior
19-Dec-2022 3
Updated Figure 6. Soft-start procedure

DS13554 - Rev 3 page 46/52

 L6981
Contents

Contents
1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Typical application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.1 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.2 Soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3 Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.4 Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.4.1 Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.4.2 Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4.3 Efficiency for Low consumption mode and Low noise mode part number . . . . . . . . . . . . . 15
6.4.4 Load regulation for low consumption mode and low noise mode part number. . . . . . . . . . 16
6.5 Switch-over feature (fixed VOUT part numbers only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.6 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.6.1 Low consumption mode part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.6.2 Low noise mode part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.7 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.8 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
7.1 GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3 Voltage divider (Adjustable part number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8.1 Programmable power up threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2 External synchronization (only available for Low Noise Mode) . . . . . . . . . . . . . . . . . . . . . . . . 24
8.3 Output voltage adjustment (Adjustable part number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.4 Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.4.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.4.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.4.3 Output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Application board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10 Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

DS13554 - Rev 3 page 47/52

 L6981
Contents

11 Thermal dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

12 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
12.1 SO 8L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12.2 SO 8L packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

DS13554 - Rev 3 page 48/52

 L6981
List of tables

List of tables
Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Typical application components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 6. Electrical characteristics TJ = 25 °C, VIN = 24 V unless otherwise specified. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 7. External synchronization AC coupling suggested operation range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. SO 8L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 11. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DS13554 - Rev 3 page 49/52

 L6981
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. Basic application (adjustable version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Basic application (fixed VOUT versions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. Power up/down behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Soft-start procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Soft-start phase with IOUT = 1.25 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. LCM operation with ISKIP = 350 mA typ. at zero load. L = 33 μH; COUT = 32 μF. . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. LCM operation at zero load condition (part 1-pulse skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. LCM operation over 15 mA load condition (part 2-pulse skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. LCM operation over 100 mA load condition (part 3-pulse skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. LCM operation over 190 mA load condition (part 4-CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. Low noise mode operation at zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. Light-load efficiency for low consumption mode and low noise mode - linear scale. VIN = 24 V; VOUT = 5 V; FSW =
400 KHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 16. Light-load efficiency for low consumption mode and low noise mode - log scale. VIN = 24 V; VOUT = 5 V; FSW =
400 KHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 KHz - linear scale . . . . . . . . . . . . . . . 16
Figure 18. Load regulation for LCM and LNM part numbers. VIN = 24 V; VOUT = 5 V; FSW = 400 KHz - log scale . . . . . . . 16
Figure 19. OVP event low consumption mode part number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. OVP event low noise mode part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. Overcurrent protection behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Soft-start procedure with VOUT shorted to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. Over current procedure with persistent short circuit between VOUT and GND . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Block diagram of the loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25. Trans-conductance embedded error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Leading network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 27. Leading network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 28. External synchronization. Direct connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. External synchronization. AC coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 30. Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 31. Evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 32. Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 33. Bottom layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 34. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 35. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 36. Power losses VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 37. Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 38. Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHz (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 39. Power losses VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 40. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 41. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHz (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 42. Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 43. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 44. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHz (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 45. Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 46. Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 47. SO 8L package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 48. SO 8L recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 49. SO 8L tape outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DS13554 - Rev 3 page 50/52

 L6981
List of figures

Figure 50. SO 8L reel outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DS13554 - Rev 3 page 51/52

 L6981

IMPORTANT NOTICE – READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names
are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved

DS13554 - Rev 3 page 52/52