Semiconductor Devices

Junction Field-Effect Transistors: Part 2

M. B. Patil
mbpatil@ee.iitb.ac.in
www.ee.iitb.ac.in/~sequel

Department of Electrical Engineering

Indian Institute of Technology Bombay

M. B. Patil, IIT Bombay

JFET I -V relationship
linear VG4
VG Gate
saturation
p+
0V 2a VD VG3

ID
Source Drain
p+
n-Si VG2
VG Gate VG1
L 0
0 VD

In the linear region, i.e., VD < VDsat ,

( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2 (2aZ )
 
ID = G0 VD − (Vbi − VP ) − , G0 = × (qµn Nd ).
3 Vbi − VP Vbi − VP L

M. B. Patil, IIT Bombay

JFET I -V relationship
linear VG4
VG Gate
saturation
p+
0V 2a VD VG3

ID
Source Drain
p+
n-Si VG2
VG Gate VG1
L 0
0 VD

In the linear region, i.e., VD < VDsat ,

( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2 (2aZ )
 
ID = G0 VD − (Vbi − VP ) − , G0 = × (qµn Nd ).
3 Vbi − VP Vbi − VP L
Pinch-off (saturation): VG − VD = VP → VDsat = VG − VP .

M. B. Patil, IIT Bombay

JFET I -V relationship
linear VG4
VG Gate
saturation
p+
0V 2a VD VG3

ID
Source Drain
p+
n-Si VG2
VG Gate VG1
L 0
0 VD

In the linear region, i.e., VD < VDsat ,

( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2 (2aZ )
 
ID = G0 VD − (Vbi − VP ) − , G0 = × (qµn Nd ).
3 Vbi − VP Vbi − VP L
Pinch-off (saturation): VG − VD = VP → VDsat = VG − VP .
Substituting in the ID equation, we get
( "  #)
2 Vbi − VG 3/2

IDsat (VG ) = G0 (VG − VP ) − (Vbi − VP ) 1 − .
3 Vbi − VP

M. B. Patil, IIT Bombay

JFET I -V relationship
linear VG4
VG Gate
saturation
p+
0V 2a VD VG3

ID
Source Drain
p+
n-Si VG2
VG Gate VG1
L 0
0 VD

In the linear region, i.e., VD < VDsat ,

( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2 (2aZ )
 
ID = G0 VD − (Vbi − VP ) − , G0 = × (qµn Nd ).
3 Vbi − VP Vbi − VP L
Pinch-off (saturation): VG − VD = VP → VDsat = VG − VP .
Substituting in the ID equation, we get
( "  #)
2 Vbi − VG 3/2

IDsat (VG ) = G0 (VG − VP ) − (Vbi − VP ) 1 − .
3 Vbi − VP
Note that IDsat depends on VG . For an n-channel JFET, IDsat ↓ as VG ↓
M. B. Patil, IIT Bombay
Comparison of JFET and BJT I -V relationships

saturation

linear
linear VG4
IB5

saturation IB4

VG3 IB3
ID

IC
IB2
VG2

VG1 IB1
0 0
0 VD 0 VCE
n-channel JFET npn BJT

M. B. Patil, IIT Bombay

Comparison of JFET and BJT I -V relationships

saturation

linear
linear VG4
IB5

saturation IB4

VG3 IB3
ID

IC
IB2
VG2

VG1 IB1
0 0
0 VD 0 VCE
n-channel JFET npn BJT

* Note the different nomenclature for linear and saturation regions.

M. B. Patil, IIT Bombay

Comparison of JFET and BJT I -V relationships

saturation

linear
linear VG4
IB5

saturation IB4

VG3 IB3
ID

IC
IB2
VG2

VG1 IB1
0 0
0 VD 0 VCE
n-channel JFET npn BJT

* Note the different nomenclature for linear and saturation regions.

sat ≈ 0.2 V irrespective of I .
* In a BJT, VCE B
In a JFET, VDsat (= VG − VP ) depends on VG .

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

For an n-channel Si JFET with Nd = 1 × 1017 cm−3 , µn = 300 cm2 /V-s, a = 0.2 µm, L = 5 µm,
Z = 10 µm, Vbi = 0.9 V for the p + n gate-to-channel junction,

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

For an n-channel Si JFET with Nd = 1 × 1017 cm−3 , µn = 300 cm2 /V-s, a = 0.2 µm, L = 5 µm,
Z = 10 µm, Vbi = 0.9 V for the p + n gate-to-channel junction,
(a) What is the pinch-off voltage VP ?

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

For an n-channel Si JFET with Nd = 1 × 1017 cm−3 , µn = 300 cm2 /V-s, a = 0.2 µm, L = 5 µm,
Z = 10 µm, Vbi = 0.9 V for the p + n gate-to-channel junction,
(a) What is the pinch-off voltage VP ?
(b) Plot ID versus VG for −2.5 V < VG < 0 V and with (i) VD = 0.1 V and (ii) VD = 5 V.

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

For an n-channel Si JFET with Nd = 1 × 1017 cm−3 , µn = 300 cm2 /V-s, a = 0.2 µm, L = 5 µm,
Z = 10 µm, Vbi = 0.9 V for the p + n gate-to-channel junction,
(a) What is the pinch-off voltage VP ?
(b) Plot ID versus VG for −2.5 V < VG < 0 V and with (i) VD = 0.1 V and (ii) VD = 5 V.
(c) Plot ID versus VD for 0 V < VD < 5 V and VG = −1.5, −1, −0.5, 0 V. Mark the boundary
between the linear and saturation regions.

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

qNd 2
(a) VP = Vbi − a = −2.2 V.
2

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

qNd 2
(a) VP = Vbi − a = −2.2 V.
2
( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2
 
(b) ID = G0 VD − (Vbi − VP ) − , VD < VDsat
3 Vbi − VP Vbi − VP

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

qNd 2
(a) VP = Vbi − a = −2.2 V.
2
( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2
 
(b) ID = G0 VD − (Vbi − VP ) − , VD < VDsat
3 Vbi − VP Vbi − VP
( "  #)
2 Vbi − VG 3/2

= G0 (VG − VP ) − (Vbi − VP ) 1 − , VD > VDsat
3 Vbi − VP

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

qNd 2
(a) VP = Vbi − a = −2.2 V.
2
( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2
 
(b) ID = G0 VD − (Vbi − VP ) − , VD < VDsat
3 Vbi − VP Vbi − VP
( "  #)
2 Vbi − VG 3/2

= G0 (VG − VP ) − (Vbi − VP ) 1 − , VD > VDsat
3 Vbi − VP
2aZ 2 × 0.2 × 10−4 × 10 × 10−4
G0 = qµn Nd = × 1.6 × 10−19 × 300 × 1017 = 3.84 × 10−4 f = 0.384 mf.
L 5 × 10−4

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

qNd 2
(a) VP = Vbi − a = −2.2 V.
2
( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2
 
(b) ID = G0 VD − (Vbi − VP ) − , VD < VDsat
3 Vbi − VP Vbi − VP
( "  #)
2 Vbi − VG 3/2

= G0 (VG − VP ) − (Vbi − VP ) 1 − , VD > VDsat
3 Vbi − VP
2aZ 2 × 0.2 × 10−4 × 10 × 10−4
G0 = qµn Nd = × 1.6 × 10−19 × 300 × 1017 = 3.84 × 10−4 f = 0.384 mf.
L 5 × 10−4
cm × cm cm2 1 A
Units: × Coul × × = = f.
cm V-sec cm3 V
M. B. Patil, IIT Bombay
 0.2
Example

VG Gate

ID (mA)
p+ 0.1
0V 2a VD
Source Drain
p+
n-Si
VP
VG Gate
0
L −2.5 −2 −1.5 −1 −0.5 0
VG (volts)
 0.2
Example

VG Gate

ID (mA)
p+ 0.1
0V 2a VD
Source Drain
p+
n-Si
VP
VG Gate
0
L −2.5 −2 −1.5 −1 −0.5 0
VG (volts)

(b) For the transistor to be in the linear region, we need VG − VD > VP , i.e., VG > VP + VD .
 0.2
Example

VG Gate

ID (mA)
p+ 0.1
0V 2a VD
Source Drain
p+
n-Si
VP
VG Gate
0
L −2.5 −2 −1.5 −1 −0.5 0
VG (volts)

(b) For the transistor to be in the linear region, we need VG − VD > VP , i.e., VG > VP + VD .
(i) VD = 0.1 V, → VG > −2.2 + 0.1 = −2.1 V for linear region.
 0.2
Example

VG Gate

ID (mA)
p+ 0.1
0V 2a VD
Source Drain
p+
n-Si
VP
VG Gate
0
L −2.5 −2 −1.5 −1 −0.5 0
VG (volts)

(b) For the transistor to be in the linear region, we need VG − VD > VP , i.e., VG > VP + VD .
(i) VD = 0.1 V, → VG > −2.2 + 0.1 = −2.1 V for linear region.
(ii) VD = 5 V, → VG > −2.2 + 5 = 2.8 V for linear region.
(Note: such a large VG is not realistic.)
 0.2
Example

VG Gate

ID (mA)
p+ 0.1
0V 2a VD
Source Drain
p+
n-Si
VP
VG Gate
0
L −2.5 −2 −1.5 −1 −0.5 0
VG (volts)

(b) For the transistor to be in the linear region, we need VG − VD > VP , i.e., VG > VP + VD .
(i) VD = 0.1 V, → VG > −2.2 + 0.1 = −2.1 V for linear region.
(ii) VD = 5 V, → VG > −2.2 + 5 = 2.8 V for linear region.
(Note: such a large VG is not realistic.)
The ID -VG plot can now be obtained using the appropriate ID expression.
 0.2
Example

VG Gate

ID (mA)
p+ 0.1
0V 2a VD
Source Drain 5V
p+
n-Si
VP
VD = 0.1 V
VG Gate
0
L −2.5 −2 −1.5 −1 −0.5 0
VG (volts)

(b) For the transistor to be in the linear region, we need VG − VD > VP , i.e., VG > VP + VD .
(i) VD = 0.1 V, → VG > −2.2 + 0.1 = −2.1 V for linear region.
(ii) VD = 5 V, → VG > −2.2 + 5 = 2.8 V for linear region.
(Note: such a large VG is not realistic.)
The ID -VG plot can now be obtained using the appropriate ID expression.

M. B. Patil, IIT Bombay

Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L
Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2
 
(c) ID = G0 VD − (Vbi − VP ) − , VD < VDsat
3 Vbi − VP Vbi − VP
( "  #)
2 Vbi − VG 3/2

= G0 (VG − VP ) − (Vbi − VP ) 1 − , VD > VDsat
3 Vbi − VP
Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2
 
(c) ID = G0 VD − (Vbi − VP ) − , VD < VDsat
3 Vbi − VP Vbi − VP
( "  #)
2 Vbi − VG 3/2

= G0 (VG − VP ) − (Vbi − VP ) 1 − , VD > VDsat
3 Vbi − VP

For each VG , we first find VDsat . For example, with VG = −1.5 V, VDsat = VG − VP = −1.5 − (−2.2) = 0.7 V.
Example

VG Gate

p+
0V 2a VD
Source + Drain
p
n-Si

VG Gate
L

( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2
 
(c) ID = G0 VD − (Vbi − VP ) − , VD < VDsat
3 Vbi − VP Vbi − VP
( "  #)
2 Vbi − VG 3/2

= G0 (VG − VP ) − (Vbi − VP ) 1 − , VD > VDsat
3 Vbi − VP

For each VG , we first find VDsat . For example, with VG = −1.5 V, VDsat = VG − VP = −1.5 − (−2.2) = 0.7 V.
We then use the appropriate ID expression to obtain the ID -VD plot for that particular VG .
 0.2
Example ID = G0 VD
0V
VG Gate
(Isat sat
D ,VD )

ID (mA)
p +
0.1 −0.5 V
0V 2a VD
Source Drain
p+ −1 V
n-Si
VG = −1.5 V
VG Gate
0
L 0 1 2 3 4 5
VD (volts)
( "  #)
2 VD + Vbi − VG 3/2 Vbi − VG 3/2
 
(c) ID = G0 VD − (Vbi − VP ) − , VD < VDsat
3 Vbi − VP Vbi − VP
( "  #)
2 Vbi − VG 3/2

= G0 (VG − VP ) − (Vbi − VP ) 1 − , VD > VDsat
3 Vbi − VP

For each VG , we first find VDsat . For example, with VG = −1.5 V, VDsat = VG − VP = −1.5 − (−2.2) = 0.7 V.
We then use the appropriate ID expression to obtain the ID -VD plot for that particular VG .

M. B. Patil, IIT Bombay

JFET source/drain resistances

p+
2a
S D
n-Si p+

G
L
L’
JFET source/drain resistances

p+
2a
S D
n-Si p+

G
L
L’

* In a real JFET structure, the source and drain contacts are some distance away from the
active part of the device, adding resistances RS and RD in the current path.
JFET source/drain resistances

p+
2a
S D
n-Si p+

G
L
L’

* In a real JFET structure, the source and drain contacts are some distance away from the
active part of the device, adding resistances RS and RD in the current path.
* The intrinsic device model needs to be augmented to include these resistances.
JFET source/drain resistances

G
G
p+
2a S D
S D RS RD
n-Si p+
intrinsic
device
G
L
L’

* In a real JFET structure, the source and drain contacts are some distance away from the
active part of the device, adding resistances RS and RD in the current path.
* The intrinsic device model needs to be augmented to include these resistances.

M. B. Patil, IIT Bombay

 Simplified JFET model for circuit analysis

0.2
ID = G0 VD
VG Gate 0V

(Isat sat
D ,VD )
p+

ID (mA)
0V 2a VD 0.1 −0.5 V
S + D
p
n-Si −1 V
VG Gate VG = −1.5 V
L 0
0 1 2 3 4 5
VD (volts)
 Simplified JFET model for circuit analysis

0.2
ID = G0 VD
VG Gate 0V

(Isat sat
D ,VD )
p+

ID (mA)
0V 2a VD 0.1 −0.5 V
S + D
p
n-Si −1 V
VG Gate VG = −1.5 V
L 0
0 1 2 3 4 5
VD (volts)
* When a JFET is used for amplification, it is biased in the saturation region, and the
saturation current IDsat at a given VG is of interest.
 Simplified JFET model for circuit analysis

0.2
ID = G0 VD
VG Gate 0V

(Isat sat
D ,VD )
p+

ID (mA)
0V 2a VD 0.1 −0.5 V
S + D
p
n-Si −1 V
VG Gate VG = −1.5 V
L 0
0 1 2 3 4 5
VD (volts)
* When a JFET is used for amplification, it is biased in the saturation region, and the
saturation current IDsat at a given VG is of interest.
( "  #)
2 Vbi − VG 3/2

* IDsat (VG ) = G0 (VG − VP ) − (Vbi − VP ) 1 − .
3 Vbi − VP
 Simplified JFET model for circuit analysis

0.2
0.2
ID = G0 VD
VG Gate 0V

(Isat sat

D (mA)
D ,VD )
p+

ID (mA)
0V 2a VD −0.5 V 0.1
0.1

Isat
S + D
p
n-Si analytical
−1 V
VP
VG Gate VG = −1.5 V
L 0 0
0 1 2 3 4 5 −2.5 −2 −1.5 −1 −0.5 0
VD (volts) VG (volts)
* When a JFET is used for amplification, it is biased in the saturation region, and the
saturation current IDsat at a given VG is of interest.
( "  #)
2 Vbi − VG 3/2

* IDsat (VG ) = G0 (VG − VP ) − (Vbi − VP ) 1 − .
3 Vbi − VP
 Simplified JFET model for circuit analysis

0.2
0.2
ID = G0 VD
VG Gate 0V

(Isat sat

D (mA)
D ,VD )
p+

ID (mA)
0V 2a VD −0.5 V 0.1
0.1

Isat
S + D
p
n-Si analytical
−1 V
VP
VG Gate VG = −1.5 V
L 0 0
0 1 2 3 4 5 −2.5 −2 −1.5 −1 −0.5 0
VD (volts) VG (volts)
* When a JFET is used for amplification, it is biased in the saturation region, and the
saturation current IDsat at a given VG is of interest.
( "  #)
2 Vbi − VG 3/2

* IDsat (VG ) = G0 (VG − VP ) − (Vbi − VP ) 1 − .
3 Vbi − VP
* For circuit design, we can use a simplified empirical expression for IDsat :
IDsat (VG ) = IDSS [1 − (VG /VP )]2 , where IDSS = IDsat VG =0 V
.
 Simplified JFET model for circuit analysis

0.2
0.2
ID = G0 VD
VG Gate 0V

(Isat sat

D (mA)
D ,VD )
p+

ID (mA)
0V 2a VD −0.5 V 0.1
0.1 approximate

Isat
S + D
p
n-Si analytical
−1 V
VP
VG Gate VG = −1.5 V
L 0 0
0 1 2 3 4 5 −2.5 −2 −1.5 −1 −0.5 0
VD (volts) VG (volts)
* When a JFET is used for amplification, it is biased in the saturation region, and the
saturation current IDsat at a given VG is of interest.
( "  #)
2 Vbi − VG 3/2

* IDsat (VG ) = G0 (VG − VP ) − (Vbi − VP ) 1 − .
3 Vbi − VP
* For circuit design, we can use a simplified empirical expression for IDsat :
IDsat (VG ) = IDSS [1 − (VG /VP )]2 , where IDSS = IDsat VG =0 V
.

M. B. Patil, IIT Bombay

 JFET small-signal model

VG Gate

p+
0V 2a VD
Source Drain
p+
n-Si

VG Gate
L
 JFET small-signal model

VG Gate

p+
0V 2a VD
Source Drain
p+
n-Si

VG Gate
L

In an amplifier, a JFET is biased in saturation, and we have

IDsat = IDSS [1 − (VG /VP )]2 .

 JFET small-signal model

linear VG4
VG Gate
saturation
p+
0V 2a VD VG3

ID
Source Drain
p+
n-Si VG2
VG Gate VG1
L 0
0 VD

In an amplifier, a JFET is biased in saturation, and we have

IDsat = IDSS [1 − (VG /VP )]2 .

 JFET small-signal model

linear VG4
VG Gate
saturation
p+
0V 2a VD VG3

ID
Source Drain
p+
n-Si VG2
VG Gate VG1
L 0
0 VD

In an amplifier, a JFET is biased in saturation, and we have

IDsat = IDSS [1 − (VG /VP )]2 .

The small-signal model at low frequencies can be derived as follows (with source at 0 V).
∂ID ∂ID
∆ID = ∆VG + ∆VD .
∂VG ∂VD
 JFET small-signal model

linear VG4
VG Gate
saturation
p+
0V 2a VD VG3

ID
Source Drain
p+
n-Si VG2
VG Gate VG1
L 0
0 VD

In an amplifier, a JFET is biased in saturation, and we have

IDsat = IDSS [1 − (VG /VP )]2 .

The small-signal model at low frequencies can be derived as follows (with source at 0 V).
∂ID ∂ID
∆ID = ∆VG + ∆VD .
∂VG ∂VD
2IDSS
 
∂ID VG
→ id = gm vg , with gm = =− 1− .
∂VG VP VP
 JFET small-signal model

linear VG4 id
VG Gate G D
saturation
p+ vgs
0V 2a VD VG3

ID
gm vgs
Source Drain
p+
n-Si VG2
is
VG Gate VG1
S
L 0
0 VD Small-signal model

In an amplifier, a JFET is biased in saturation, and we have

IDsat = IDSS [1 − (VG /VP )]2 .

The small-signal model at low frequencies can be derived as follows (with source at 0 V).
∂ID ∂ID
∆ID = ∆VG + ∆VD .
∂VG ∂VD
2IDSS
 
∂ID VG
→ id = gm vg , with gm = =− 1− .
∂VG VP VP

M. B. Patil, IIT Bombay

 JFET small-signal model

linear VG4 id
VG Gate G D
saturation
p+ vgs
0V 2a VD VG3

ID
gm vgs
Source Drain
p+
n-Si VG2
is
VG Gate VG1
S
L 0
0 VD Small-signal model

In an amplifier, a JFET is biased in saturation, and we have

IDsat = IDSS [1 − (VG /VP )]2 .

The small-signal model at low frequencies can be derived as follows (with source at 0 V).
∂ID ∂ID
∆ID = ∆VG + ∆VD .
∂VG ∂VD
2IDSS
 
∂ID VG
→ id = gm vg , with gm = =− 1− .
∂VG VP VP
(Note that there is a reverse biased pn junction between G and S and betweeen G and D. → ig = 0.)
M. B. Patil, IIT Bombay
 G depletion
p+ region

S D
0V VD

Channel length modulation:

∆L

G VD
V
(VD − Vsat
D )

0 x2
L
 G depletion
p+ region

S D
0V VD

Channel length modulation:

* In saturation, the actual channel length is
∆L Leff = L − ∆L.
G VD
V
(VD − Vsat
D )

0 x2
L
 G depletion
p+ region

S D
0V VD

Channel length modulation:

* In saturation, the actual channel length is
∆L Leff = L − ∆L.
G VD ↑ → ∆L ↑ → Leff ↓
VD
V (2aZ )
 
(VD − Vsat
D ) → G0 = × (qµn Nd ) ↑ → ID ↑
Leff

0 x2
L
 G depletion
p+ region
ID linear saturation

1
slope = gd =
ro

S D
0V VD VD

Channel length modulation:

* In saturation, the actual channel length is
∆L Leff = L − ∆L.
G VD ↑ → ∆L ↑ → Leff ↓
VD
V (2aZ )
 
(VD − Vsat
D ) → G0 = × (qµn Nd ) ↑ → ID ↑
Leff

0 x2
L
 G depletion id
p+ region
G D
ID linear saturation

vgs ro
gm vgs
1
slope = gd =
ro
is
S D S
0V VD VD Small-signal model

Channel length modulation:

* In saturation, the actual channel length is
∆L Leff = L − ∆L.
G VD ↑ → ∆L ↑ → Leff ↓
VD
V (2aZ )
 
(VD − Vsat
D ) → G0 = × (qµn Nd ) ↑ → ID ↑
Leff

0 x2
L M. B. Patil, IIT Bombay
 G depletion id
p+ region
G D
ID linear saturation

vgs ro
gm vgs
1
slope = gd =
ro
is
S D S
0V VD VD Small-signal model

Channel length modulation:

* In saturation, the actual channel length is
∆L Leff = L − ∆L.
G VD ↑ → ∆L ↑ → Leff ↓
VD
V (2aZ )
 
(VD − Vsat
D ) → G0 = × (qµn Nd ) ↑ → ID ↑
Leff
* This “channel length modulation” is significant in
short-channel devices (L ∼ 1 µm).

0 x2
L M. B. Patil, IIT Bombay
JFET: small-signal model

VG Gate

p+
0V 2a VD
Source Drain
p+
n-Si

VG Gate
L
JFET: small-signal model

id
VG Gate
G D
+
p
0V 2a VD vgs ro
Source Drain gm vgs
p+
n-Si

VG Gate is

L S
JFET: small-signal model

id
VG Gate
G D
+
p
0V 2a VD vgs ro
Source Drain gm vgs
p+
n-Si

VG Gate is

L S

* At high frequencies, the device capacitances must be included in the small-signal model.
JFET: small-signal model

id
VG Gate
G D
+
p
0V 2a VD vgs ro
Source Drain gm vgs
p+
n-Si

VG Gate is

L S

* At high frequencies, the device capacitances must be included in the small-signal model.
* The gate capacitance is essentially that of the gate-to-channel reverse-biased p + n junction, which gets
divided between Cgs and Cgd .
JFET: small-signal model

id ig Cgd id
VG Gate
G D G D
rd
+
p
0V 2a VD vgs ro vgs ro
Source Drain gm vgs Cgs gm vgs
p+
n-Si

VG Gate is
rs
L S
is
S

* At high frequencies, the device capacitances must be included in the small-signal model.
* The gate capacitance is essentially that of the gate-to-channel reverse-biased p + n junction, which gets
divided between Cgs and Cgd .

M. B. Patil, IIT Bombay

 0.2 15
JFET amplifiers
VBE = 0.725 V
0V
linear
10
saturation

ID (mA)

IC (mA)
0.1 −0.5 V
0.7 V
5
−1 V
0.675 V
VG = −1.5 V 0.65 V
0 0
0 1 2 3 4 5 0 1 2 3 4 5
VD (volts) VCE (volts)

ig id ib ic
G D B C

vgs ro vbe rπ ro
gm vgs gm vbe

is ie
S JFET BJT E

M. B. Patil, IIT Bombay

 0.2 15
JFET amplifiers
VBE = 0.725 V
0V
linear
10
saturation

ID (mA)

IC (mA)
0.1 −0.5 V
0.7 V
5
−1 V
0.675 V
VG = −1.5 V 0.65 V
0 0
0 1 2 3 4 5 0 1 2 3 4 5
VD (volts) VCE (volts)

ig id ib ic
G D B C

vgs ro vbe rπ ro
gm vgs gm vbe

is ie
S JFET BJT E

* Qualitatively, the ID -VDS relationship of a JFET is similar to the IC -VCE relationship of a BJT.

M. B. Patil, IIT Bombay

 0.2 15
JFET amplifiers
VBE = 0.725 V
0V
linear
10
saturation

ID (mA)

IC (mA)
0.1 −0.5 V
0.7 V
5
−1 V
0.675 V
VG = −1.5 V 0.65 V
0 0
0 1 2 3 4 5 0 1 2 3 4 5
VD (volts) VCE (volts)

ig id ib ic
G D B C

vgs ro vbe rπ ro
gm vgs gm vbe

is ie
S JFET BJT E

* Qualitatively, the ID -VDS relationship of a JFET is similar to the IC -VCE relationship of a BJT.
* A JFET can be used for amplification, e.g., we can have a “common-source” amplifier which is similar to the
“common-emitter” amplifier.
M. B. Patil, IIT Bombay
JFET amplifiers

* For amplification, a JFET needs to be biased

in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ).
 VDD
JFET amplifiers

RD
* For amplification, a JFET needs to be biased
D ID
in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ). G
S
VGG VGS

(a)
VGS = −VGG
 VDD
JFET amplifiers

RD
* For amplification, a JFET needs to be biased
D ID
in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ). G
S
VGG VGS

(a)
VGS = −VGG

ID

(a)

IQ
D

VQ 0 VGS
GS
VP
 VDD VDD
JFET amplifiers

RD RD
* For amplification, a JFET needs to be biased
D ID D ID
in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ). G G
S S
VGG VGS VGS
RS

(a) (b)
VGS = −VGG VGS = −ID RS

ID

(a)

IQ
D

VQ 0 VGS
GS
VP
 VDD VDD
JFET amplifiers

RD RD
* For amplification, a JFET needs to be biased
D ID D ID
in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ). G G
S S
VGG VGS VGS
RS

(a) (b)
VGS = −VGG VGS = −ID RS

ID

(a)

(b)

IQ
D

VQ 0 VGS
GS
VP
 VDD VDD VDD
JFET amplifiers

RD RD R1 RD
* For amplification, a JFET needs to be biased
D ID D ID D ID
in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ). G G G
S S S
VGG VGS VGS VGS
R2
RS RS

(a) (b) (c)

R2
VGS = −VGG VGS = −ID RS VGS = VDD − ID RS
R1 + R2

ID

(a)

(b)

IQ
D

VQ 0 VGS
GS
VP
 VDD VDD VDD
JFET amplifiers

RD RD R1 RD
* For amplification, a JFET needs to be biased
D ID D ID D ID
in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ). G G G
S S S
VGG VGS VGS VGS
R2
RS RS

(a) (b) (c)

R2
VGS = −VGG VGS = −ID RS VGS = VDD − ID RS
R1 + R2

ID

(a)

(b)

(c) IQ
D

VQ 0 VGS
GS
VP
 VDD VDD VDD
JFET amplifiers

RD RD R1 RD
* For amplification, a JFET needs to be biased
D ID D ID D ID
in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ). G G G
S S S
VGG VGS VGS VGS
R2
RS RS
* The drain current equation,
2
IDsat (VG ) = IDSS [1 − (VG /VP )] ,
(a) (b) (c)
implies that there is a unique ID for a given R2
VGS = −VGG VGS = −ID RS VGS = VDD − ID RS
VGS . R1 + R2
However, there is a device-to-device varation
in the ID -VGS curve, giving rise to some ID

deviation from the intended bias point.

(a)

(b)

(c) IQ
D

VQ 0 VGS
GS
VP
 VDD VDD VDD
JFET amplifiers

RD RD R1 RD
* For amplification, a JFET needs to be biased
D ID D ID D ID
in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ). G G G
S S S
VGG VGS VGS VGS
R2
RS RS
* The drain current equation,
2
IDsat (VG ) = IDSS [1 − (VG /VP )] ,
(a) (b) (c)
implies that there is a unique ID for a given R2
VGS = −VGG VGS = −ID RS VGS = VDD − ID RS
VGS . R1 + R2
However, there is a device-to-device varation
in the ID -VGS curve, giving rise to some ID

deviation from the intended bias point.

(a)

(b)

(c) IQ
D

VQ 0 VGS
GS
M. B. Patil, IIT Bombay VP
 VDD VDD VDD
JFET amplifiers

RD RD R1 RD
* For amplification, a JFET needs to be biased
D ID D ID D ID
in the saturation region, and the design goal
is to bias it at a certain Q-point, (ID , VDS ). G G G
S S S
VGG VGS VGS VGS
R2
RS RS
* The drain current equation,
2
IDsat (VG ) = IDSS [1 − (VG /VP )] ,
(a) (b) (c)
implies that there is a unique ID for a given R2
VGS = −VGG VGS = −ID RS VGS = VDD − ID RS
VGS . R1 + R2
However, there is a device-to-device varation
in the ID -VGS curve, giving rise to some ID

deviation from the intended bias point.

(a)
* The voltage divider scheme (c) is superior
since it is least sensitive, i.e., the deviation in (b)
ID is small compared to the other schemes.
(c) IQ
D

VQ 0 VGS
GS
M. B. Patil, IIT Bombay VP
Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

R1 RD

D ID

G
S
VGS
R2
RS

R2
VGS = VDD − ID RS
R1 + R2

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID

G
S
VGS
R2
RS

R2
VGS = VDD − ID RS
R1 + R2

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VGS
R2
RS

R2
VGS = VDD − ID RS
R1 + R2

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VD = VDD − ID RD = 12 V − 0.4 mA × 15 k = 6 V. VGS
R2
RS

R2
VGS = VDD − ID RS
R1 + R2

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VD = VDD − ID RD = 12 V − 0.4 mA × 15 k = 6 V. VGS
Q R2
→ VS = VD − VDS = 6V − 4V = 2V RS

R2
VGS = VDD − ID RS
R1 + R2

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VD = VDD − ID RD = 12 V − 0.4 mA × 15 k = 6 V. VGS
Q R2
→ VS = VD − VDS = 6 V − 4 V = 2 V → RS = VS /IDQ = 2 V/0.4 mA = 5 kΩ. RS

R2
VGS = VDD − ID RS
R1 + R2

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VD = VDD − ID RD = 12 V − 0.4 mA × 15 k = 6 V. VGS
Q R2
→ VS = VD − VDS = 6 V − 4 V = 2 V → RS = VS /IDQ = 2 V/0.4 mA = 5 kΩ. RS

For VGS to be −0.735 V, we need VG = VS + VGS = 2 V + (−0.735 V) = 1.265 V.

R2
VGS = VDD − ID RS
R1 + R2

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VD = VDD − ID RD = 12 V − 0.4 mA × 15 k = 6 V. VGS
Q R2
→ VS = VD − VDS = 6 V − 4 V = 2 V → RS = VS /IDQ = 2 V/0.4 mA = 5 kΩ. RS

For VGS to be −0.735 V, we need VG = VS + VGS = 2 V + (−0.735 V) = 1.265 V.

R2 R2
Since VG = VDD , we now need to choose suitable values of R1 and R2 to get VGS = VDD − ID RS
R1 + R2 R1 + R2
the above VG . R1 = 200 kΩ and R1 = 23.5 kΩ is one such choice.

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VD = VDD − ID RD = 12 V − 0.4 mA × 15 k = 6 V. VGS
Q R2
→ VS = VD − VDS = 6 V − 4 V = 2 V → RS = VS /IDQ = 2 V/0.4 mA = 5 kΩ. RS

For VGS to be −0.735 V, we need VG = VS + VGS = 2 V + (−0.735 V) = 1.265 V.

R2 R2
Since VG = VDD , we now need to choose suitable values of R1 and R2 to get VGS = VDD − ID RS
R1 + R2 R1 + R2
the above VG . R1 = 200 kΩ and R1 = 23.5 kΩ is one such choice.
Finally, we check whether the transistor is indeed biased in saturation.

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VD = VDD − ID RD = 12 V − 0.4 mA × 15 k = 6 V. VGS
Q R2
→ VS = VD − VDS = 6 V − 4 V = 2 V → RS = VS /IDQ = 2 V/0.4 mA = 5 kΩ. RS

For VGS to be −0.735 V, we need VG = VS + VGS = 2 V + (−0.735 V) = 1.265 V.

R2 R2
Since VG = VDD , we now need to choose suitable values of R1 and R2 to get VGS = VDD − ID RS
R1 + R2 R1 + R2
the above VG . R1 = 200 kΩ and R1 = 23.5 kΩ is one such choice.
Finally, we check whether the transistor is indeed biased in saturation.
For saturation, we need VGS − VDS < VP ,

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VD = VDD − ID RD = 12 V − 0.4 mA × 15 k = 6 V. VGS
Q R2
→ VS = VD − VDS = 6 V − 4 V = 2 V → RS = VS /IDQ = 2 V/0.4 mA = 5 kΩ. RS

For VGS to be −0.735 V, we need VG = VS + VGS = 2 V + (−0.735 V) = 1.265 V.

R2 R2
Since VG = VDD , we now need to choose suitable values of R1 and R2 to get VGS = VDD − ID RS
R1 + R2 R1 + R2
the above VG . R1 = 200 kΩ and R1 = 23.5 kΩ is one such choice.
Finally, we check whether the transistor is indeed biased in saturation.
For saturation, we need VGS − VDS < VP , i.e., −0.735 − 4 < −2 V.

M. B. Patil, IIT Bombay

Example

The JFET parameters are IDSS = 1 mA, VP = −2 V. For VDD = 12 V and RD = 15 kΩ, find
suitable values of R1 , R2 , RS to get a bias point of IDQ = 0.4 mA and VDS
Q
= 4 V. VDD

Solution: The drain current in the saturation region is given by RD

R1
IDsat (VG ) = IDSS [1 − (VGS /VP )]2 .
D ID
Solving for IDsat = IDQ = 0.4 mA, we get Q
VGS = −0.735 V.
G
S
VD = VDD − ID RD = 12 V − 0.4 mA × 15 k = 6 V. VGS
Q R2
→ VS = VD − VDS = 6 V − 4 V = 2 V → RS = VS /IDQ = 2 V/0.4 mA = 5 kΩ. RS

For VGS to be −0.735 V, we need VG = VS + VGS = 2 V + (−0.735 V) = 1.265 V.

R2 R2
Since VG = VDD , we now need to choose suitable values of R1 and R2 to get VGS = VDD − ID RS
R1 + R2 R1 + R2
the above VG . R1 = 200 kΩ and R1 = 23.5 kΩ is one such choice.
Finally, we check whether the transistor is indeed biased in saturation.
For saturation, we need VGS − VDS < VP , i.e., −0.735 − 4 < −2 V.

M. B. Patil, IIT Bombay

Common-source amplifier

VDD

RD
R1
G D
D CD
G vs R′ vgs ro RD RL vo
CG S
vO RL gm vgs
vs R2 S
RS
CS
Ri Ro

M. B. Patil, IIT Bombay

Common-source amplifier

VDD

RD
R1
G D
D CD
G vs R′ vgs ro RD RL vo
CG S
vO RL gm vgs
vs R2 S
RS
CS
Ri Ro

vo
* AV ≡ = −gm (RD0 k RL ), where RD0 = RD k ro ≈ RD if ro is large.
vs

M. B. Patil, IIT Bombay

Common-source amplifier

VDD

RD
R1
G D
D CD
G vs R′ vgs ro RD RL vo
CG S
vO RL gm vgs
vs R2 S
RS
CS
Ri Ro

vo
* AV ≡ = −gm (RD0 k RL ), where RD0 = RD k ro ≈ RD if ro is large.
vs
AVO = AV = −gm RD0 .
RL →∞

M. B. Patil, IIT Bombay

Common-source amplifier

VDD

RD
R1
G D
D CD
G vs R′ vgs ro RD RL vo
CG S
vO RL gm vgs
vs R2 S
RS
CS
Ri Ro

vo
* AV ≡ = −gm (RD0 k RL ), where RD0 = RD k ro ≈ RD if ro is large.
vs
AVO = AV = −gm RD0 .
RL →∞

* Ri = R 0 = R1 k R2 , Ro = RD0 .

M. B. Patil, IIT Bombay

Common-source amplifier: Example

VDD

RD
R1
G D
D CD
G vs R′ vgs ro RD RL vo
CG S
vO RL gm vgs
vs R2 S
RS
CS
Ri Ro

For the common-source amplifier of the last example, find (a) gain with RL → ∞ and (b) input resistance Ri .

M. B. Patil, IIT Bombay

Common-source amplifier: Example

VDD

RD
R1
G D
D CD
G vs R′ vgs ro RD RL vo
CG S
vO RL gm vgs
vs R2 S
RS
CS
Ri Ro

For the common-source amplifier of the last example, find (a) gain with RL → ∞ and (b) input resistance Ri .
Solution:

M. B. Patil, IIT Bombay

Common-source amplifier: Example

VDD

RD
R1
G D
D CD
G vs R′ vgs ro RD RL vo
CG S
vO RL gm vgs
vs R2 S
RS
CS
Ri Ro

For the common-source amplifier of the last example, find (a) gain with RL → ∞ and (b) input resistance Ri .
Solution:
! 
VQ 1 −0.735 V 1
    
gm = 2 IDSS 1 − GS × − = 2 (1 mA) 1 − × − = 0.63 mS.
VP VP −2 V −2 V

M. B. Patil, IIT Bombay

Common-source amplifier: Example

VDD

RD
R1
G D
D CD
G vs R′ vgs ro RD RL vo
CG S
vO RL gm vgs
vs R2 S
RS
CS
Ri Ro

For the common-source amplifier of the last example, find (a) gain with RL → ∞ and (b) input resistance Ri .
Solution:
! 
VQ 1 −0.735 V 1
    
gm = 2 IDSS 1 − GS × − = 2 (1 mA) 1 − × − = 0.63 mS.
VP VP −2 V −2 V
(a) AVO = −gm RD = −0.63 mS × 15 kΩ = −9.5, assuming ro to be large.

M. B. Patil, IIT Bombay

Common-source amplifier: Example

VDD

RD
R1
G D
D CD
G vs R′ vgs ro RD RL vo
CG S
vO RL gm vgs
vs R2 S
RS
CS
Ri Ro

For the common-source amplifier of the last example, find (a) gain with RL → ∞ and (b) input resistance Ri .
Solution:
! 
VQ 1 −0.735 V 1
    
gm = 2 IDSS 1 − GS × − = 2 (1 mA) 1 − × − = 0.63 mS.
VP VP −2 V −2 V
(a) AVO = −gm RD = −0.63 mS × 15 kΩ = −9.5, assuming ro to be large.
(b) Ri = R1 k R2 = 200 kΩ k 23.5 kΩ = 21 kΩ.

M. B. Patil, IIT Bombay

n-channel Metal-Semiconductor Field-Effect Transistor (MESFET)

Source Gate Drain

n+ n+ a

semi-insulating GaAs

M. B. Patil, IIT Bombay

n-channel Metal-Semiconductor Field-Effect Transistor (MESFET)

Source Gate Drain

n+ n+ a

semi-insulating GaAs

* In a MESFET, the channel conductance is modulated by a rectifying metal-semiconductor junction.

M. B. Patil, IIT Bombay

n-channel Metal-Semiconductor Field-Effect Transistor (MESFET)

Source Gate Drain

n+ n+ a

semi-insulating GaAs

* In a MESFET, the channel conductance is modulated by a rectifying metal-semiconductor junction.

* The substrate is semi-insulating, with a resistivity of about 108 Ω-cm.

M. B. Patil, IIT Bombay

n-channel Metal-Semiconductor Field-Effect Transistor (MESFET)

Source Gate Drain

n+ n+ a

semi-insulating GaAs

* In a MESFET, the channel conductance is modulated by a rectifying metal-semiconductor junction.

* The substrate is semi-insulating, with a resistivity of about 108 Ω-cm.
* On the substrate, an n-type channel region is deposited, and the n+ source/drain regions are created by
ion implantation.

M. B. Patil, IIT Bombay

n-channel Metal-Semiconductor Field-Effect Transistor (MESFET)

Source Gate Drain

n+ n+ a

semi-insulating GaAs

* In a MESFET, the channel conductance is modulated by a rectifying metal-semiconductor junction.

* The substrate is semi-insulating, with a resistivity of about 108 Ω-cm.
* On the substrate, an n-type channel region is deposited, and the n+ source/drain regions are created by
ion implantation.
* The S/D contacts are ohmic; gate contact is rectifying.

M. B. Patil, IIT Bombay

n-channel Metal-Semiconductor Field-Effect Transistor (MESFET)

Source Gate Drain

n+ n+ a

semi-insulating GaAs

M. B. Patil, IIT Bombay

n-channel Metal-Semiconductor Field-Effect Transistor (MESFET)

Source Gate Drain

n+ n+ a

semi-insulating GaAs

* For MESFETs, GaAs is preferred over silicon because of its higher electron mobility
(typically a factor of 5 larger than µn in silicon).

M. B. Patil, IIT Bombay

n-channel Metal-Semiconductor Field-Effect Transistor (MESFET)

Source Gate Drain

n+ n+ a

semi-insulating GaAs

* For MESFETs, GaAs is preferred over silicon because of its higher electron mobility
(typically a factor of 5 larger than µn in silicon).
* Small channel lengths (tenths of a micron) are often used to make the transistor faster,
by reducing the transit time from source to drain and also the gate capacitance.

M. B. Patil, IIT Bombay

n-channel Metal-Semiconductor Field-Effect Transistor (MESFET)

Source Gate Drain

n+ n+ a

semi-insulating GaAs

* For MESFETs, GaAs is preferred over silicon because of its higher electron mobility
(typically a factor of 5 larger than µn in silicon).
* Small channel lengths (tenths of a micron) are often used to make the transistor faster,
by reducing the transit time from source to drain and also the gate capacitance.
* GaAs MESFETs are commonly used in high-frequency (a few GHz) applications.

M. B. Patil, IIT Bombay