A HIGH ACCURACY 22 BIT SIGMA-DELTA CONVERTER FOR DIGITAL

REGULATION OF SUPER-CONDUCTING MAGNET CURRENTS

J G Pett

CERN. Switzerland

tones’, is the unwanted generation of low level output

INTRODUCTION frequencies within the pass band of the ADC.
The design of the latest CERN particle accelerator for THE PROBLEM AREAS
high energy particle physics research, the Large
Hadron Collider (LHC), has been underway for some For use as a precise DC to low-frequency digitiser
years. The new machine requires stronger magnetic (1 kHz), the Sigma-Delta ADC presents many
fields which necessitates the use of super-conducting variables for the designer to optimise. Furthermore,
magnets around most of the 27km ring tunnel. The the theoretical understanding of the method, while
powering of these magnets, with currents up to 13 kA, well established in certain areas, was rather weak in
. presents new challenges in precision, which can be the areas of interest for digital regulation. The main
summarised as an improvement in setting and points of study were therefore :
regulation of certain currents to the part per million
(ppm) level. This represents approximately a factor of The development of a complete simulation process
ten improvement over present analogue methods. This for optimising/experimenting with the basic
paper will concentrate on the design and performance concepts and design parameters.
of the analogue to digital converter (ADC), which is Output noise and its minimisation.
the key element in the digital regulation loops The generation of ‘idle-tones’ and their
employed in each magnet power converter. dependence on both DC input level and other
design choices.
WHY SIGMA-DELTA ? Digital filter design, including external
synchronisation and in particular low group delay.
The ADC employed in the digital regulation loops for Factors affecting long term stability, such as
LHC requires high resolution and accurate digitisation component drift and temperature variations.
of very low frequency waveforms. Since the ADC is Overall system aspects, such as external noise
one of the major sources of error in the magnet sensitivity and isolation.
current, along with the current transducer, its Testing methods at such extremes of performance.
performance largely determines the overall accuracy
which can be obtained. Research into alternative DEVELOPMENT
designs of ADC’s during the early 90’s revealed that
ppm levels of resolution, noise, linearity and stability, The basic structure chosen is shown in Fig. 1. A
while attainable, were essentially limited to slow number of prototype realisations were made based on
digitising processes, with a corresponding long delay an initial optimisation of parameters obtained via
from triggering to digital output. Such a delay within simulation :
a digital control loop is unacceptable and should be
minimised.
The potential of the Sigma-Delta method to deliver
buffer
ppm performance with shorter delay and probably
LOGIC
improved overall performance seemed most attractive.
As no obvious alternatives were known, a research and
development programme was started to examine the 1 bit I j pulses
j viaF.0.
j link
potential of the new method. However, at that w
moment in time the DC and low-frequency
performance had not been demonstrated and in
particular many papers mentioned pattern noise with
DC inputs as a major problem e.g. Candy and Temes
(1) page 4. Pattern noise, which is often termed ‘idle Figure 1 : Sigma-Delta ADC Basic Structure

Advanced A/D and D/A Conversion Techniques and their Applications,

27 - 28 July 1999 Conference Publication No. 466 0IEE 1999

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 47

These prototypes have all been based on the use of the This simple method injects a disturbing signal into the
following elements : comparator, at a frequency close to the clock frequency
A continuous-time (analogue) third order and of such amplitude as to 100% modulate the
modulator structure clocked at 1 MHz ; using an analogue input to the comparator. The effect of this
over-sampling ratio of 500 and auto-clamping of dither is to whiten the natural noise and hence reduce
the second and third integrators for start-up etc. tones by either frequency smearing or phase-rotation
A single bit digital to analogue converter (DAC) at very low frequencies. In some respects this dither
using a precision reference and switchllogic appears to move the modulator closer to instability and
design and including the use of a 62 ns guard- create ‘quasi-chaotic’ conditions. Simulated phase
band between bit samples to ensure adequate plots have been made and could merit further
linearity. theoretical investigation.
A sinc4 digital filter, realised in field
programmable gate array ( P G A ) form. KEY PERFORMANCE RESULTS
An accurate temperature regulation of the key
components by the use of a Peltier element. The following results have been obtained with a
number of different prototypes and are quite
The early prototypes exhibited many practical repeatable, within the limits stated.
problems which have been understood and corrected
over time. These problems have been concerned The measured numerical performance parameters of
mainly with the following areas : the ADC are shown below. The measurement of
Component performance, e.g. reference drift, resolution remains to be extended to higher
resistor matching and operational amplifier slew frequencies and the longer term stability has not yet
rates. been evaluated for long enough and therefore only an
Mutual interference between the analogue and fast estimate has been given. All figures in ppm are of
digital sections, which generates DC offsets, or Full Scale Range (20V).
locking to clock edges. Bandwidth DC-lkHz (-3 dB)
Noise and linearity measurements and
improvements, which included the design of a Group Delay 500 ps
single ground plane printed circuit board.
In band pattern noise, or ‘tone’ production when Data rate (ext. synch.) 0 to 5 k.samples/s
using DC inputs and methods to reduce them. Resolution (DC to -10 Hz) 22 bits
While the first three areas were very much of a
practical nature, the latter was a theoretical problem Noise (1 k.sample/s) < 1.0 ppm rms
which was expected but not well quantified. In spite Linearity (uncorrected) < rt 1.5 ppm
of the design options outlined above which tended to
reduce such tones to the minimum, practical tests (corrected) < rt 0.5 ppm
revealed tones at a peak level of around -115dB with
respect to full scale input at certain ‘cardinal’ values, Temp. Coeff. (5 to 40°C) 0.1 ppm/”C(max)
notably about zero input voltage. Such levels were
Stability (24 hrs) < 0.5 ppm
unacceptable for the intended use, since they occurred
down to frequencies below 1 Hz. and a method to (1 month) < 1.5 ppm
suppress them needed to be found.
The graphical results complement and expand on the
While experimenting with traditional low frequency
‘dither’ injection, which did not help, an effective
method has been found to suppress all observed in-
band tones to below -126dB and is shown in Fig. 2.

comparator
output - 8
-pulses

m. &
Oscillator
0 1 2
Time in seconds
3 4
5.0000

Figure 2: High Frequency ‘Chaotic’ Dither Method Figure 3 : 100 pV Step Input

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 C
E
300
Bin width: 0.05ppm
0
l,o --
- Corrected
Uncorrected '
~

d
30

20
L
Samples: 8192
:: 200
a,

-
a, Rate: 1kHz 10
U)

a 2
5 o s
-
0
o = 0.65 .-c
& 100
n -10 E
W
5
Z

0
-3 -2 -1 0 1 2 3
-l.O
-1.5
t' '
-20

-30
-10 -5 0 5 10
Offset from mean in ppm of +/-1OV Input voltage

Figure 4 : Noise Distribution Figure 6 : Linearity

above details. Fig. 3 shows a 5 ppm input step from a further to <0.1 ppm rms at 10 Hz and below. This
Datron Calibrator, while Fig. 4 shows the full scale very low frequency noise is in part due to the inherent
noise as a distribution. circuit and reference noise. These figures suggest that
Fig. 5 is a Fast Fourier Transform (FFT)of the ADC in the intended application an effective resolution of at
least 22 bits could be expected up to 10 Hz and even
noise with a 500 pV DC input voltage. The effect of
beyond. However, other measurements must be
the dither generator is to suppress all spectral
performed with dynamic signals to complete and
components below 126 dB.
complement these figures.
The linearity plot shown in Fig. 6 shows both
uncorrected and digitally corrected examples. The USE IN THE DIGITAL REGULATION LOOP
correction is applied as two different scale factors for
positive or negative inputs. The basic system components involved in the digital
regulation of magnet currents are shown in Fig 7 and
EFFECTIVE RESOLUTION an example of a typical test with a 20 kA switch-mode
power converter is shown in Fig. 8
The noise distribution shown in Fig. 4 indicates that
Since the 31d order modulator and 41h order digital
the wide band noise with a DC input is approximately
filter are isolated by a simple fibre optic link, the noise
gaussian. Therefore, since the sigma has a value of
environment of the power converter and the digital
0.65 ppm rms this suggests that a resolution of
regulation hardware (Digital Signal Processor, or
<1 ppm can be obtained, which corresponds to 20 bits.
DSP), is well isolated from the sensitive analogue
However, analysis of this noise reveals a higher level
circuitry. In very simple terms, the performance of
at high frequencies, as would be expected due to the
the regulation loop is as good as the ADC (loop
noise shaping, with a correspondingly lower value at
dynamics apart), and fully justifies the initial choice of
lower frequency and DC. By band limiting the noise
the ADC method. It is important to realise that the
progressively from 1 kHz downwards, a value of
closed loop operation of the regulation system
0.12 ppm rms at 100 Hz was found which reduced
effectively filters the higher frequency noise of the
ADC. The overall noise and resolution therefore

1 -40
0
Samples: 81 92
Rate: 1 kHz
appears to be limited essentially by the remaining low
frequency noise, which is well below the 1 ppm level.

4
U,
9
c!?
-80

-120

-160
,
input
+
DSP
digital Regulation
value Algorithm
-200 I I
0 100 200 300 400 500
Frequency in Hz I

Figure 5 : Noise FFT Figure 7 : Digital Regulation Components

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 49

9,
12
E,
Q
0 .G
I
a,
2
-1
-E
L

0’
-2
0 60 120 I80 240
Time in Minutes

Figure 8 : Magnet Current Stability

CONCLUDING REMARKS ACKNOWLEDGEMENTS

Although trials with other high power converters and The author wishes to acknowledge the support of
magnets are still underway, the initial experience many CERN colleagues, the theoretical support of the
indicates that the Sigma-Delta design is well suited to late Dr. C. P. Lewis (Coventry University) and the
use in such demanding applications and has now industrial support from M. Story and D. McCleod of
demonstrated the 1 ppm performance required for the dCS.
LHC machine.
REFERENCES
Certain practical aspects, such as synchronisation from
external sources, minimum delay times and easy 1. Candy J., and Temes G., 1992 “Oversampling
galvanic isolation makes this ADC design well suited Delta-Sigma Converters”. IEEE Press New York,
for use in the digital regulation of high-power, power USA.
converters. The use of a Peltier based temperature
regulation improves the temperature coefficient by a
factor of approximately fifteen but also enables other
key elements to operate with better long term stability.
The development of this high accuracy ADC has built
on the substantial base of theoretical knowledge
established by many workers since the mid 1980’s (1).
The practical results reported here extend the
performance into the high accuracy DC and low
frequency domain by using existing precision analogue
design methods and an unusual high frequency,’quasi-
chaotic’ dither technique for tone suppression.
However, it must be stated that the difficulty of
making measurements to the ppm level has been
considerable. In a number of areas it is all but
impossible to separate the errors of the ADC from
those of the measuring equipment. As a consequence,
the most pessimistic figures have been quoted and
some remain to be completed. It should be noted that,
contrary to present commercial practice, these results
have been obtained without the use of frequent in-situ
re-calibrations etc. As such, the final results are very
close to those suggested by both theory and simulation.

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