L5973AD

2A SWITCH STEP DOWN SWITCHING REGULATOR

■ 2A INTERNAL SWITCH
■ OPERATING INPUT VOLTAGE FROM 4.4V TO 36V
■ 3.3V / (±2%) REFERENCE VOLTAGE
■ OUTPUT VOLTAGE ADJUSTABLE FROM
1.235V TO 35V
HSOP8 - EXPOSED PAD
■ LOW DROPOUT OPERATION: 100% DUTY
CYCLE ORDERING NUMBERS: L5973AD (Tube)
■ 500KHz INTERNALLY FIXED FREQUENCY L5973ADTR (Tape & Reel)
■ VOLTAGE FEEDFORWARD
■ ZERO LOAD CURRENT OPERATION DESCRIPTION
■ INTERNAL CURRENT LIMITING The L5973AD is a step down monolithic power
■ INHIBIT FOR ZERO CURRENT switching regulator with a switch current limit of 2A so
CONSUMPTION it is able to deliver more than 1.5A DC current to the
■ SYNCHRONIZATION load depending on the application conditions.
■ PROTECTION AGAINST FEEDBACK The output voltage can be set from 1.235V to 35V.
DISCONNECTION The high current level is also achieved thanks to an
■ THERMAL SHUTDOWN SO8 package with exposed frame, that allows to re-
duce the Rth(j-amb) down to approximately 40°C/W
The device uses an internal P-Channel D-MOS tran-
sistor (with a typical of 200mΩ) as switching element
APPLICATIONS: to avoid the use of bootstrap capacitor and guarantee
■ CONSUMER: STB, DVD, TV, VCR,CAR high efficiency.
RADIO, LCD MONITORS An internal oscillator fixes the switching frequency at
■ NETWORKING: XDSL, MODEMS,DC-DC 500KHz to minimize the size of external components.
MODULES Having a minimum input voltage of 4.4V only, it is
■ COMPUTER: PRINTERS, AUDIO/GRAPHIC particularly suitable for 5V bus, available in all com-
CARDS, OPTICAL STORAGE, HARD DISK puter related applications.
DRIVE Pulse by pulse current limit with the internal frequen-
■ INDUSTRIAL: CHARGERS, CAR BATTERY cy modulation offers an effective constant current
DC-DC CONVERTERS short circuit protection.
TEST APPLICATION CIRCUIT

VREF
3.3V 6 OUT L1 15µH VOUT=3.3V
1
VIN = 4.4V to 35V VCC
8 D1
L5973AD STPS340U R1
SYNC. 2 5.6K C2
COMP 5 330µF
C1 4 3 7 FB 10V
10µF C4
22nF INH GND
35V R2
CERAMIC 3.3K
C3 R3
220pF 4.7K

D03IN1453

September 2003 1/13

This datasheet has been downloaded from http://www.digchip.com at this page

L5973AD

THERMAL DATA
Symbol Parameter Value Unit
Rth (j-amb) Thermal Resistance Junction to ambient Max. 40 (*) °C/W
(*) Package mounted on board

PIN CONNECTION

OUT 1 8 VCC
SYNC 2 7 GND
INH 3 6 VREF
COMP 4 5 FB
D98IN955

PIN DESCRIPTION
N. Name Description
1 OUT Regulator Output.
2 SYNC Master/Slave Synchronization. When it is open, a signal synchronous with the turn-off of the inter-
nal power is present at the pin. When connected to an external signal at a frequency higher than
the internal one, then the device is synchronized by the external signal.
Connecting together the SYNC pin of two devices, the one with the higher frequency works as
master and the other one, works as slave.
3 INH A logical signal (active high) disables the device. With IHN higher than 2.2V the device is OFF and with
INH lower than 0.8V, the device is ON.
If INH is not used the pin must be grounded. When it is open, an internal pull-up disables the device.
4 COMP E/A output to be used for frequency compensation.
5 FB Stepdown feedback input. Connecting the output voltage directly to this pin results in an output
voltage of 1.235V. An external resistor divider is required for higher output voltages (the typical
value for the resistor connected between this pin and ground is 4.7K).
6 VREF Reference voltage of 3.3V. No filter capacitor is needed to stability.
7 GND Ground.
8 VCC Unregulated DC input voltage.

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
V8 Input Voltage 40 V
V1 Output DC voltage -1 to 40 V
Output peak voltage at t = 0.1µs -5 to 40 V
I1 Maximum output current int. limit.
V4, V5 Analog pins 4 V
V3 INH -0.3V to VCC
V2 SYNC -0.3 to 4 V
Ptot Power dissipation at Tamb ≤ 60°C 2.25 W
Tj Operating junction temperature range -40 to 150 °C
Tstg Storage temperature range -55 to 150 °C

2/13
 L5973AD

ELECTRICAL CHARACTERISTICS (Tj = 25°C, VCC = 12V, unless otherwise specified.)

Symbol Parameter Test Condition Min. Typ. Max. Unit
VCC Operating input voltage range Vo = 1.235V; Io = 2A 4.4 36 V
RDSON Mosfet on Resistance 0.250 0.5 Ω
Il Maximum limiting current VCC = 4.4V to 36V 2.3 A
fs Switching frequency 500 KHz
Duty cycle 0 100 %
DYNAMIC CHARACTERISTICS (see test circuit ).
V5 Voltage feedback 4.4V < VCC < 36V 1.220 1.235 1.25 V
η Efficiency VO = 5V, VCC = 12V 90 %
DC CHARACTERISTICS
Iqop Total Operating Quiescent Current 5 7 mA
Iq Quiescent current Duty Cycle = 0; VFB = 1.5V 2.7 mA
Iqst-by Total stand-by quiescent current Vinh > 2.2V 50 100 µA
INHIBIT
INH Threshold Voltage Device ON 0.8 V
Device OFF 2.2 V
ERROR AMPLIFIER
VOH High level output voltage VFB = 1V 3.5 V
VOL Low level output voltage VFB = 1.5V 0.4 V
Io source Source output current VCOMP = 1.9V; VFB = 1V 200 300 µA
Io sink Sink output current VCOMP = 1.9V; VFB = 1.5V 1 1.5 mA
Ib Source bias current 2.5 4 µA
DC open loop gain RL = ∞ 50 57 dB
gm Transconductance Icomp = -0.1mA to 0.1mA 2.3 mS
VCOMP = 1.9V
SYNC FUNCTION
High Input Voltage VCC = 4.4V to 36V 2.5 VREF V
Low Input Voltage VCC = 4.4V to 36V 0.74 V
Slave Sink Current Vsync = 0.74V (1) 0.11 0.25 mA
Vsync = 2.33V 0.21 0.45 mA

Master Output Amplitude Isource = 3mA 2.75 3 V

Output Pulse Width no load, Vsync = 1.65V 0.20 0.35 µs
REFERENCE SECTION
Reference Voltage 3.234 3.3 3.366 V
IREF = 0 to 5mA 3.2 3.3 3.399 V
VCC = 4.4V to 36V
Line Regulation IREF = 0mA 5 10 mV
VCC = 4.4V to 36V
Load Regulation IREF = 0 to 5mA 8 15 mV
Short Circuit Current 10 18 30 mA
Note: 1. Guaranteed by design

3/13
L5973AD

FUNCTIONAL DESCRIPTION
The main internal blocks are shown in Fig. 1, where is reported the device block diagram. They are:
■ A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3V reference
voltage is externally available.
■ A voltage monitor circuit that checks the input and internal voltages.
■ A fully integrated sawtooth oscillator whose frequency is500KHz
■ Two embedded current limitations circuitries which control the current that flows through the
power switch. The Pulse by Pulse Current Limit forces the power switch OFF cycle by cycle
if the current reaches an internal threshold, while the Frequency Shifter reduces the switch-
ing frequency in order to strongly reduce the duty cycle.
■ A transconductance error amplifier.
■ A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive
the internal power.
■ An high side driver for the internal P-MOS switch.
■ An inhibit block for stand-by operation.
■ A circuit to realize the thermal protection function.

Figure 1. Block Diagram

VCC

VOLTAGES
TRIMMING
MONITOR
VREF
SUPPLY VREF
BUFFER
THERMAL
SHUTDOWN 1.235V 3.5V
INH INHIBIT
PEAK TO PEAK
COMP CURRENT LIMIT

E/A
FB - PWM
+ D Q
+
1.235V - Ck DRIVER
LPDMOS
POWER
FREQUENCY
SYNC OSCILLATOR
SHIFTER

GND OUT D00IN1125

POWER SUPPLY & VOLTAGE REFERENCE

The internal regulator circuit (shown in Figure 2) consists of a start-up circuit, an internal voltage Prereg-
ulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks.
The Starter gives the start-up currents to the whole device when the input voltage goes high and the de-
vice is enabled (inhibit pin connected to ground).
The Preregulator block supplies the Bandgap cell with a preregulated voltage V REG that has a very low
supply voltage noise sensitivity.

4/13
 L5973AD

VOLTAGES MONITOR
An internal block senses continuously the Vcc, Vref and Vbg. If the voltages go higher than their thresholds, the
regulator starts to work. There is also an hysteresis on the VCC (UVLO).

Figure 2. Internal Regulator Circuit

VCC

STARTER PREREGULATOR

VREG

BANDGAP

IC BIAS

D00IN1126 VREF

OSCILLATOR & SYNCHRONIZATOR

Figure 3 shows the block diagram of the oscillator circuit.
The Clock Generator provides the switching frequency of the device that is internally fixed at 500KHz. The frequency
shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is
then used in the internal logic circuitry and is the input of the Ramp Generator and Synchronizator blocks.
The Ramp Generator circuit provides the sawtooth signal, used to realize the PWM control and the internal volt-
age feed forward, while the Synchronizator circuit generates the synchronization signal. Infact the device has a
synchronization pin that can works both as Master and Slave.
As Master to synchronize external devices to the internal switching frequency.
As Slave to synchronize itself by external signal.
In particular, connecting together two devices, the one with the lower switching frequency works as Slave and
the other one works as Master.
To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization
threshold with a duty cycle that can vary approximately from 10% to 90%, depending also on the signal frequen-
cy and amplitude.
The frequency of the synchronization signal must be at least higher than the internal switching frequency of the
device (500KHz).

5/13
L5973AD

Figure 3. Oscillator Circui

FREQUENCY
SHIFTER CLOCK
t

Ibias_osc

CLOCK RAMP
GENERATOR GENERATOR RAMP

SYNCHRONIZATOR
SYNC
D00IN1131

CURRENT PROTECTION
The L5973AD has two current limit protections, pulse by pulse and frequency fold back.
The schematic of the current limitation circuitry for the pulse by pulse protection is shown in figure 4.
The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series,
RSENSE. The current is sensed through Rsense and if reaches the threshold, the mirror is unbalanced and the
PDMOS is switched off until the next falling edge of the internal clock pulse.
Due to this reduction of the ON time, the output voltage decreases.
Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a suf-
ficiently low duty cycle at 500KHz, the output current, in strong overcurrent or short circuit conditions, could in-
crease again. For this reason the switching frequency is also reduced, so keeping the inductor current under its
maximum threshold. The Frequency Shifter (see fig. 3) depends on the feedback voltage. As the feedback volt-
age decreases (due to the reduced duty cycle), the switching frequency decreases too.

Figure 4. Current Limitation Circuitry

VCC

RSENSE RTH
IOFF

DRIVER
A1 A2 IL

OUT
A1/A2=95
I I NOT

PWM

D00IN1134

ERROR AMPLIFIER
The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose
non inverting input is connected to the internal voltage reference (1.235V), while the inverting input (FB) is con-
nected to the external divider or directly to the output voltage. The output (COMP) is connected to the external

6/13
 L5973AD

compensation network.
The uncompensated error amplifier has the following characteristics:
Transconductance 2300µS

Low frequency gain 65dB

Minimum sink/source voltage 1500µA/300µA

Output voltage swing 0.4V/3.65V

Input bias current 2.5µA

The error amplifier output is compared with the oscillator sawtooth to perform PWM control.

PWM COMPARATOR AND POWER STAGE

This block compares the oscillator sawtooth and the error amplifier output signals generating the PWM
signal for the driving stage.
The power stage is a very critical block cause it has to guarantee a correct turn on and turn off of the PD-
MOS.
The turn on of the power element, or better, the rise time of the current at turn on, is a very critical param-
eter to compromise.
At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses.
But there is a limit introduced by the recovery time of the recirculation diode.
In fact when the current of the power element equals the inductor current, the diode turns off and the drain
of the power is free to go high. But during its recovery time, the diode can be considered as an high value
capacitor and this produces a very high peak current, responsible of many problems:
Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics.
Turn on overcurrent causing a decrease of the efficiency and system reliability.
Big EMI problems.
Shorter freewheeling diode life.
The fall time of the current during the turn off is also critical. In fact it produces voltage spikes (due to the
parasitics elements of the board) that increase the voltage drop across the PDMOS.
In order to minimize all these problems, a new topology of driving circuit has been used and its block dia-
gram is shown in fig. 5.
The basic idea is to change the current levels used to turn on and off the power switch, according with the
PDMOS status and with the gate clamp status.
This circuitry allow to turn off and on quickly the power switch and to manage the above question related
to the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that Vgs of the
internal switch goes higher than Vgsmax. The ON/OFF Control block avoids any cross conduction be-
tween the supply line and ground.

7/13
L5973AD

Figure 5. Driving Circuitry

VCC

Vgsmax

IOFF

CLAMP GATE
PDMOS
VOUT
DRAIN
L
STOP
ON/OFF OFF
ILOAD
DRIVE CONTROL ESR

ON
DRAIN
C
ION

D00IN1133

INHIBIT FUNCTION
The inhibit feature allows to put in stand-by mode the device. With INH pin higher than 2.2V the device is dis-
abled and the power consumption is reduced to less than 100µA. With INH pin lower than 0.8V, the device is
enabled. If the INH pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit
threshold and the device is disabled. The pin is also Vcc compatible.

THERMAL SHUTDOWN
The shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher
than a fixed internal threshold (150°C). The sensing element of the chip is very close to the PDMOS area, so
ensuring an accurate and fast temperature detection. An hysteresis of approximately 20°C avoids that the de-
vices turns on and off continuously

ADDITIONAL FEATURES AND PROTECTIONS

FEEDBACK DISCONNECTION
In case of feedback disconnection, the duty cycle increases versus the maximum allowed value, bringing the
output voltage close to the input supply. This condition could destroy the load.
To avoid this dangerous condition, the device is turned off if the feedback pin remains floating.

OUTPUT OVERVOLTAGE PROTECTION

The overvoltage protection, OVP, is realized by using an internal comparator, which input is connected to the
feedback, that turns off the power stage when the OVP threshold is reached. This threshold is typically 30%
higher than the feedback voltage.
When a voltage divider is requested for adjusting the output voltage (see test application circuit), the OVP inter-
vention will be set at:
R1 + R2
V O VP = 1.3 ⋅ -------------------- ⋅ V FB
R2

8/13
 L5973AD

Where R1 is the resistor connected between the output voltage and the feedback pin, while R2 is between the
feedback pin and ground.

ZERO LOAD
Due to the fact that the internal power is a PDMOS, no boostrap capacitor is required and so, the device works prop-
erly also with no load at the output. In this condition it works in burst mode, with random repetition rate of the burst.

APPLICATION CIRCUIT
In figure 6 is shown the demo board application circuit, where the input supply voltage, Vcc, can range from 4.4V
to 25V due to the rated voltage of the input capacitor and the output voltage is adjustable from 1.235V to Vcc.

Figure 6. Demo board Application Circuit

VREF
3.3V 6 OUT L1 15µH VOUT=3.3V
1
VIN = 4.4V to 25V VCC
8 D1
L5973AD STPS2L25U R1
SYNC. 2 5.6K C2
COMP 5 330µF
C1 4 3 7 FB 6.3V
10µF C4
22nF INH GND
25V R2
CERAMIC 3.3K
C3 R3
220pF 4.7K

D03IN1454

Table 1. Component List

Reference Part Number Description Manufacturer

C1 10µF, 25V TOKIN

C2 POSCAP 6TPB330M 330µF, 6.3V Sanyo

C3 C1206C221J5GAC 220pF, 5%, 50V KEMET

C4 C1206C223K5RAC 22nF, 10%, 50V KEMET

R1 5.6K, 1%, 0.1W 0603 Neohm

R2 3.3K, 1%, 0.1W 0603 Neohm

R3 4.7K, 1%, 0.1W 0603 Neohm

D1 STPS2L25U 2A, 25V ST

L1 DO3316P-153 15µH, 3A COILCRAFT

9/13
L5973AD

Figure 7. Junction Temperature vs. Output Figure 9. Efficiency vs. Output Current
Current

Tj(°C)
95
100
90 Vo=2.5V
90
Vin=5V Vo=3.3V
80 Vout=3.3V

Efficiency (%)
Tamb=25°C 85
70
Vo=1.8V 80
60
Vout=2.5V
50 75
Vin=5V
40 Vout=1.8V
70
30
65
20
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Io(A) Io(A)

Figure 8. Junction Temperature vs Output Figure 10. Efficiency vs. Output Current
Current

Tj(C)
110 95
100 Vo=3.3V
90
Vin=12V Vo=5V Vout=5V
90
Tamb=25°C 85
Efficiency (%)

80
70 Vo=2.5V 80 Vout=3.3V
60
75
50 Vout=2.5V
40 70 Vin=12V
30
65
20
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Io(A)
Io(A)

10/13
 L5973AD

APPLICATION IDEAS

Figure 11. Positive Buck-Boost regulator

L1 D2
15uH STPS2L25U VOUT=12V/0.6A
VIN=5V Vcc OUT
8 1
D1
L5973AD STPS2L25U 24k
COMP FB
4 5 C4
C1
2 6 7 3 M1 100uF
10uF
C2 C3 STN4NE03L 16V
10V
220pF 22nF SYNC VREF GND INH 2.7k
Ceramic
R3
4.7k 3.3V

Figure 12. Buck-Boost regulator

VREF
3.3V 6 OUT L1 15µH
1
VIN = 5V VCC
8 D1
L5973AD STPS2L25U
SYNC. 2
2.7K VOUT=-12V/
COMP 5 0.6A
C1 C2 4 3 7 FB
10µF 10µF C4
INH GND C5
10V 25V 22nF
24K 100µF
CERAMIC CERAMIC 16V
C3 R3
220pF 4.7K

D03IN1455

Figure 13. Dual output voltage with auxiliary winding

D2
N1/N2=2 1N4148 VOUT1=5V/
50mA
VREF
3.3V 6 OUT VOUT=3.3V/
1 0.5A
VIN = 5V VCC
8 Lp 22µH
L5973AD
SYNC. 2 D1
STPS25L25U
COMP 5
C1 4 3 7 FB
10µF C3
INH GND C4 C5
25V 22nF
100µF 47µF
CERAMIC 10V 10V
C2 R3
220pF 4.7K

D03IN1456

Refer to L5973AD application note (AN1723) to have additional information, details, and more application
ideas.
L5973AD belongs to L597x family.
Related part numbers are:
■ L5970D: 1.5A (Isw), 250KHz Step Down DC-DC Converter in SO8
■ L5972D: 2A (Isw), 250KHz Step Down DC-DC Converter in SO8
■ L5973D: 2.5A (Isw), 250KHz Step Down DC-DC Converter in HSOP8
In case higher current is needed, the nearest DC-DC Converter family is L497x.

11/13
L5973AD

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 1.350 1.750 0.531 0.069

A1 0.100 0.250 0.004 0.010

A2 1.100 1.650 0.043 0.065

B 0.330 0.510 0.013 0.020

C 0.190 0.250 0.07 0.010

D 4.800 5.000 0.189 0.197

E 3.800 4.000 0.150 0.157

e 1.270 0.05

H 5.800 6.200 0.228 0.244

h 0.250 0.500 0.010 0.020

L 0.400 1.270 0.016 0.05

k 0˚ (min), 8˚ (max)

ddd 0.100 0.010

HSOP8
(1) Dimension D does not include mold flash, protusions (Exposed Pad)
or gate burrs shall not exeed 0.15mm (both side).

7195016

12/13
 L5973AD

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

© 2003 STMicroelectronics - All rights reserved

STMicroelectronics GROUP OF COMPANIES

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com

13/13