HCPL-9000/-0900, -9030/-0930,

HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J
High Speed Digital Isolators

Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product

Description Features
The HCPL-90xx and HCPL-09xx CMOS digital isolators • +3.3V and +5V TTL/CMOS compatible
feature high speed performance and excellent transient • 3 ns max. pulse width distortion
immunity specifications. The symmetric magnetic
coupling barrier gives these devices a ­ typical pulse • 6 ns max. propagation delay skew
width distortion of 2 ns, a typical propagation delay • 15 ns max. propagation delay
skew of 4 ns and 100 Mbaud data rate, making them the • High speed: 100 MBd
industry’s fastest digital isolators.
• 15 kV/µs min. common mode rejection
The single channel digital isolators (HCPL-9000/
• Tri-state output (HCPL-9000/-0900)
-0900) features an active-low logic output enable.
The dual channel digital isolators are configured as • 2500 V RMS isolation
­unidirectional (HCPL-9030/-0930) and bi-directional • UL1577 and IEC 61010-1 approved
(HCPL-9031/-0931), operating in full duplex mode making
it ideal for digital fieldbus applications. Applications
The quad channel digital isolators are configured as • Digital fieldbus isolation
unidirectional (HCPL-900J/-090J), two channels in one • Multiplexed data transmission
direction and two channels in opposite direction (HCPL-
• Computer peripheral interface
901J/-091J), and one channel in one direction and
three channels in opposite direction (HCPL-902J/-092J). • High speed digital systems
These high channel density make them ­ ideally suited • Isolated data interfaces
to isolating data conversion devices, parallel buses and
• Logic level shifting
peripheral interfaces.
They are available in 8-pin PDIP, 8-pin Gull Wing, 8‑pin
SOIC packages, and 16–pin SOIC narrow-body and wide-
body packages. They are specified over the temperature
range of -40°C to +100°C.
CAUTION: It is advised that normal static precautions
be taken in handling and assembly of this component
to prevent damage and/or degradation, which may be
induced by ESD.
Selection Guide
Device Number Channel Configuration Package
HCPL-9000 Single 8-pin DIP (300 Mil)
HCPL-0900 Single 8-pin Small Outline
HCPL-9030 Dual 8-pin DIP (300 Mil)
HCPL-0930 Dual 8-pin Small Outline
HCPL-9031 Dual, Bi-Directional 8-pin DIP (300 Mil)
HCPL-0931 Dual, Bi-Directional 8-pin Small Outline
HCPL-900J Quad 16-pin Small Outline, Wide Body
HCPL-090J Quad 16-pin Small Outline, Narrow Body
HCPL-901J Quad, 2/2, Bi-Directional 16-pin Small Outline, Wide Body
HCPL-091J Quad, 2/2, Bi-Directional 16-pin Small Outline, Narrow Body
HCPL-902J Quad, 1/3, Bi-Directional 16-pin Small Outline, Wide Body
HCPL-092J Quad, 1/3, Bi-Directional 16-pin Small Outline, Narrow Body

Ordering Information
HCPL-09xx and HCPL-90xx are UL Recognized with 2500 Vrms for 1 minute per UL1577.

Option
RoHS Non RoHS Surface Gull Tape &
Part number Compliant Compliant Package Mount Wing Reel Quantity
HCPL-9000 -000E No option
300mil 50 per tube
HCPL-9030 DIP-8
-300E -300 X X 50 per tube
HCPL-9031
-500E -500 X X X 1000 per reel
HCPL-0900 -000E No option X 100 per tube
HCPL-0930 SO-8
HCPL-0931 -500E -500 X X 1500 per reel
HCPL-900J -000E No option
Wide Body X 50 per tube
HCPL-901J
HCPL-902J -500E -500 SO-16 X X 1000 per reel
HCPL-090J -000E No option
Narrow Body X 50 per tube
HCPL-091J
HCPL-092J -500E -500 SO-16 X X 1000 per reel

To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-9031-500E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel in RoHS
compliant.

Example 2:
HCPL-0900 to order product of SO-8 package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.


Pin Description Functional Diagrams
Symbol Description Single Channel
VDD1 Power Supply 1
VDD1 8 VDD2 Truth Table
VDD2 Power Supply 2 1

Galvanic Isolation
INX Logic Input Signal IN1 2 7 VOE IN1 VOE OUT1
OUTX Logic Output Signal L L L
NC 3 6 OUT1
GND1 Power Supply Ground 1 H L H

GND2 Power Supply Ground 2

GND1 4 5 GND2 L H Z
H H Z
VOE Logic Output Enable
HCPL-9000/0900
(Single Channel), Active Low
NC Not Connected

Dual Channel

VDD1 1 8 VDD2 VDD1 1 8 VDD2

Galvanic Isolation

Galvanic Isolation

IN1 2 7 OUT1 IN1 2 7 OUT1

IN2 3 6 OUT2 OUT2 3 6 IN2

GND1 4 5 GND2 GND1 4 5 GND2

HCPL-9030/0930 HCPL-9031/0931

Quad Channel

VDD1 1 16 VDD2 VDD1 1 16 VDD2 VDD1 1 16 VDD2

GND1 2 15 GND2 GND1 2 15 GND2 GND1 2 15 GND2

IN1 3 14 OUT1 IN1 3 14 OUT1 IN1 3 14 OUT1

Galvanic Isolation
Galvanic Isolation

Galvanic Isolation

IN2 4 13 OUT2 IN2 4 13 OUT2 IN2 4 13 OUT2

IN3 5 12 OUT3 OUT3 5 12 IN3 IN3 5 12 OUT3

IN4 6 11 OUT4 OUT4 6 11 IN4 OUT4 6 11 IN4

NC 7 10 NC NC 7 10 NC NC 7 10 NC

GND1 8 9 GND2 GND1 8 9 GND2 GND1 8 9 GND2

HCPL-900J/-090J HCPL-901J/-091J HCPL-902J/-092J


Package Outline Drawings
HCPL-9000, HCPL-9030 and HCPL-9031 Standard DIP Packages

8 7 6 5

0.240 (6.096)
0.260 (6.604)

1 2 3 4

0.370 (9.398)
0.400 (10.160)
0.290 (7.366) 0.55 (1.397)
0.310 (7.874) 0.65 (1.651)

0.120 (3.048)
0.150 (3.810)
0.008 (0.203)
0.015 (0.381)
0.015 (0.381)
0.035 (0.889)
3°
8°
0.030 (0.762) 0.090 (2.286) 0.300 (7.620)
0.045 (1.143) 0.110 (2.794) 0.370 (9.398)
0.015 (0.380)
0.023 (0.584)
0.045 (1.143)
0.065 (1.651)

DIMENSIONS: INCHES (MILLIMETERS) MIN

MAX

HCPL-9000, HCPL-9030 and HCPL-9031 Gull Wing Surface Mount Option 300
PAD LOCATION (for reference only)
0.370 (9.400) 0.040 (1.016)
0.390 (9.900) 0.047 (1.194)

8 7 6 5
0.190 TYP.
(4.826)
0.240 (6.100)
0.260 (6.600) 0.370 (9.398)
0.390 (9.906)
1 2 3 4

0.015 (0.381)
0.047 (1.194) 0.025 (0.635)
0.070 (1.778)
0.045 (1.143) 0.370 (9.400)
0.065 (1.651) 0.390 (9.900)
0.030 (0.762)
0.045 (1.143) 0.290 (7.370)
0.310 (7.870)
0.008 (0.203)
0.120 (3.048) 0.013 (0.330)
0.150 (3.810)

0.030 (0.760) 0.015 (0.385)

0.056 (1.400) 0.035 (0.885)
0.025 (0.632) 12° NOM.
0.100
(2.540) 0.035 (0.892)
BSC
MIN
DIMENSIONS INCHES (MILLIMETERS)
MAX
LEAD COPLANARITY = 0.004 INCHES (0.10 mm)


HCPL-0900, HCPL-0930 and HCPL-0931 Small Outline SO-8 Package

0.189 (4.80)
0.197 (5.00)

8 7 6 5

0.228 (5.80) 0.150 (3.80)

0.244 (6.20) 0.157 (4.00)

1 2 3 4

0.013 (0.33)
0.020 (0.51)

0.010 (0.25)
0.020 (0.50) 0.008 (0.19)
x 45° 0.010 (0.25)
0.004 (0.10)
0.054 (1.37) 0.010 (0.25)
0.069 (1.75)
0°
8°
0.040 (1.016)
0.016 (0.40)
0.060 (1.524)
0.050 (1.27)

DIMENSIONS: INCHES (MILLIMETERS) MIN

MAX

HCPL-900J, HCPL-901J and HCPL-902J Wide Body SOIC-16 Package

0.397 (10.084)
0.413 (10.490) Pin 1 indent
8 1

0.394 (10.007)
0.419 (10.643)
0.291 (7.391)
0.299 (7.595)

0.013 (0.330)
0.020 (0.508)

0.092 (2.337) 0.287 (7.290)

7° TYP 0.104 (2.642) 0.297 (7.544) 0.010 (0.254)
x 45°
7° TYP 0.020 (0.508)

0.080 (2.032) 0° – 8° TYP

0.100 (2.54)

0.040 (1.016) 0.009 (0.229)

0.004 (0.1016) 0.016 (0.40)
0.060 (1.524) 0.012 (0.305)
0.011 (0.279) 0.050 (1.27)

DIMENSIONS: INCHES (MILLIMETERS) MIN

MAX


HCPL-090J, HCPL-091J and HCPL-092J Narrow Body SOIC-16 Package
0.386 (9.802)
0.394 (9.999) Pin 1 indent
8 1

0.228 (5.791)
0.152 (3.861)
0.244 (6.197)
0.157 (3.988)

0.013 (0.330)
0.020 (0.508)

0.054 (1.372) 0.010 (0.245)

0.068 (1.727) 0.008 (0.191) x 45°
0.020 (0.508)
0.010 (0.249)
0.050 (1.270) 0° – 8° TYP
0.060 (1.524)

0.040 (1.016)
0.004 (0.102) 0.016 (0.406)
0.060 (1.524)
0.010 (0.249) 0.050 (1.270)

DIMENSIONS: INCHES (MILLIMETERS) MIN

MAX

Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions
Capacitance (Input-Output) CI-O [1]
pF f = 1 MHz
Single Channel 1.1
Dual Channel 2.0
Quad Channel 4.0
Thermal Resistance θJCT °C/W Thermocouple located at
8-Pin PDIP 150 center underside of package
8-Pin SOIC 240
Package Power Dissipation PPD mW
8-Pin PDIP 150
8-Pin SOIC 150
Notes:
1. Single and dual channels device are considered two-terminal devices: pins 1-4 shorted and pins 5-8 shorted. Quad channel devices are con-
sidered two‑terminal devices: pins 1-8 shorted and pins 9-16 shorted.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all inte-
grated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from
performance degradation to complete failure.


Insulation and Safety Related Specifications
Parameters Condition Min. Typ. Max. Units
Barrier Impedance Ω||pF
Single Channel >1014||3
Dual Channel >1014||3
Quad Channel >1014||7
Creepage Distance (External) mm
8-Pin PDIP 7.036
8-Pin SOIC 4.026
16-Pin SOIC Narrow Body 4.026
16-Pin SOIC Wide Body 8.077
Leakage Current 240 VRMS 0.2 µA
60 Hz

IEC61010-1 Insulation Characteristics*

HCPL-0900 HCPL-9000
HCPL-0930 HCPL-9030
HCPL-090J HCPL-900J
HCPL-091J HCPL-901J
Description Symbol HCPL-092J HCPL-902J Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms I – III I – IV
for rated mains voltage ≤ 300 Vrms I – III
Pollution Degree (DIN VDE 0110/1.89) 2 2
Maximum Working Insulation Voltage VIORM 150 300 Vrms


Absolute Maximum Ratings
Parameters Symbol Min. Max. Units
Storage Temperature TS –55 175 °C
Ambient Operating Temperature [1] TA –55 125 °C
Supply Voltage VDD1, VDD2 –0.5 7 V
Input Voltage VIN –0.5 VDD1 +0.5 V
Voltage Output Enable (HCPL-9000/-0900) VOE –0.5 VDD2 +0.5 V
Output Voltage VOUT –0.5 VDD2 +0.5 V
Output Current Drive IOUT 10 mA
Lead Solder Temperature (10s) 260 °C
ESD 2 kV Human Body Model

Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee performance.

Recommended Operating Conditions

Parameters Symbol Min. Max. Units
Ambient Operating Temperature TA –40 100 °C
Supply Voltage VDD1, VDD2 3.0 5.5 V
Logic High Input Voltage VIH 2.4 VDD1 V
Logic Low Input Voltage VIL 0 0.8 V
Input Signal Rise and Fall Times tIR, tIF 1 µs
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends
that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or stor-
age could range from performance degradation to complete failure.


3.3V operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +3.3 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Quiescent Supply Current 1 IDD1 mA VIN = 0V
HCPL-9000/-0900 0.008 0.01
HCPL-9030/-0930 0.008 0.01
HCPL-9031/-0931 1.5 2.0
HCPL-900J/-090J 0.018 0.02
HCPL-901J/-091J 3.3 4.0
HCPL-902J/-092J 1.5 2.0
Quiescent Supply Current 2 IDD2 mA VIN = 0V
HCPL-9000/-0900 3.3 4.0
HCPL-9030/-0930 3.3 4.0
HCPL-9031/-0931 1.5 2.0
HCPL-900J/-090J 5.5 8.0
HCPL-901J/-091J 3.3 4.0
HCPL-902J/-092J 3.0 6.0
Logic Input Current IIN -10 10 µA
Logic High Output Voltage VOH VDD2 ­– 0.1 VDD2 V IOUT = -20 µA, VIN = VIH
0.8*VDD2 VDD2 – 0.5 V IOUT = -4 mA, VIN = VIH
Logic Low Output Voltage VOL 0 0.1 V IOUT = 20 µA, VIN = VIL
0.5 0.8 V IOUT = 4 mA, VIN= VIL
Switching Specifications
Maximum Data Rate 100 110 MBd CL = 15 pF
Clock Frequency fmax 50 MHz
Propagation Delay Time to Logic tPHL 12 18 ns
Low Output
Propagation Delay Time toLogic tPLH 12 18 ns
High Output
Pulse Width tPW 10 ns
Pulse Width Distortion |PWD|
[1]
2 3 ns
|tPHL – tPLH|
Propagation Delay Skew [2] tPSK 4 6 ns
Output Rise Time (10 – 90%) tR 2 4 ns
Output Fall Time (10 – 90%) tF 2 4 ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance tPHZ 3 5 ns
Low to High Impedance tPLZ 3 5 ns
High Impedance to High tPZH 3 5 ns
High Impedance to Low tPZL 3 5 ns
Channel-to-Channel Skew tCSK 2 3 ns
(Dual and Quad Channels)
Common Mode Transient Immunity |CMH| 15 18 kV/µs Vcm = 1000V
(Output Logic High or Logic Low)[3] |CML|

Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.


5V operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +5.0 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Quiescent Supply Current 1 IDD1 mA VIN = 0V
HCPL-9000/-0900 0.012 0.018
HCPL-9030/-0930 0.012 0.018
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 0.024 0.036
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 2.5 3.0
Quiescent Supply Current 2 IDD2 mA VIN = 0V
HCPL-9000/-0900 5.0 6.0
HCPL-9030/-0930 5.0 6.0
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 8.0 12.0
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 6.0 9.0
Logic Input Current IIN -10 10 µA
Logic High Output Voltage VOH VDD2 – 0.1 VDD2 V IOUT = -20 µA, VIN = VIH
0.8*VDD2 VDD2 – 0.5 V IOUT = -4 mA, VIN = VIH
Logic Low Output Voltage VOL 0 0.1 V IOUT = 20 µA, VIN = VIL
0.5 0.8 V IOUT = 4 mA, VIN= VIL
Switching Specifications
Maximum Data Rate 100 110 MBd CL = 15 pF
Clock Frequency fmax 50 MHz
Propagation Delay Time to Logic tPHL 10 15 ns
Low Output
Propagation Delay Time to Logic tPLH 10 15 ns
High Output
Pulse Width tPW 10 ns
Pulse Width Distortion |PWD|
[1]
2 3 ns
|tPHL – tPLH|
Propagation Delay Skew[2] tPSK 4 6 ns
Output Rise Time (10 – 90%) tR 1 3 ns
Output Fall Time (10 – 90%) tF 1 3 ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance tPHZ 3 5 ns
Low to High Impedance tPLZ 3 5 ns
High Impedance to High tPZH 3 5 ns
High Impedance to Low tPZL 3 5 ns
Channel-to-Channel Skew tCSK 2 3 ns
(Dual and Quad Channels)
Common Mode Transient Immunity |CMH| 15 18 kV/µs Vcm = 1000V
(Output Logic High or Logic Low)[3] |CML|
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.

10
Mixed 5V/3.3V or 3.3V/5V operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = +5.0 V, VDD2 = +3.3V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
HCPL-9000/-0900 0.012 0.018
HCPL-9030/-0930 0.012 0.018
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 0.024 0.036
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 2.5 3.0
Quiescent Supply Current 2 IDD2 mA VIN = 0V
HCPL-9000/-0900 5.0 6.0
HCPL-9030/-0930 5.0 6.0
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 8.0 12.0
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 6.0 9.0
Logic Input Current IIN -10 10 µA
Logic High Output Voltage VOH VDD2 – 0.1 VDD2 V IOUT = -20 µA, VIN = VIH
0.8*VDD2 VDD2 – 0.5 V IOUT = -4 mA, VIN = VIH
Logic Low Output Voltage VOL 0 0.1 V IOUT = 20 µA, VIN = VIL
0.5 0.8 V IOUT = 4 mA, VIN= VIL
Switching Specifications
Maximum Data Rate 100 110 MBd CL = 15 pF
Clock Frequency fmax 50 MHz
Propagation Delay Time to Logic tPHL 12 18 ns
Low Output
Propagation Delay Time to Logic tPLH 12 18 ns
High Output
Pulse Width tPW 10 ns
Pulse Width Distortion [1] |PWD| 2 3 ns
|tPHL – tPLH|
Propagation Delay Skew[2] tPSK 4 6 ns
Output Rise Time (10 – 90%) tR 2 4 ns
Output Fall Time (10 – 90%) tF 2 4 ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance tPHZ 3 5 ns
Low to High Impedance tPLZ 3 5 ns
High Impedance to High tPZH 3 5 ns
High Impedance to Low tPZL 3 5 ns
Channel-to-Channel Skew tCSK 2 3 ns
(Dual and Quad Channels)
Common Mode Transient Immunity |CMH| 15 18 kV/µs Vcm = 1000V
(Output Logic High or Logic Low)[3] |CML|
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.

11
Applications Information Bypassing and PC Board Layout
Power Consumption The HCPL-90xx and HCPL-09xx digital isolators are
extremely easy to use. No external interface circuitry is
The HCPL-90xx and HCPL-09xx CMOS digital isolators required because the isolators use high-speed CMOS IC
achieves low power consumption from the ­ manner by technology allowing CMOS logic to be connected directly
which they transmit data across isolation barrier. By to the inputs and outputs. As shown in Figure 1, the only
detecting the edge transitions of the input logic signal external components required for proper operation are
and converting this to a narrow current pulse, which drives two 47 nF ceramic capacitors for decoupling the power
the isolation barrier, the isolator then latches the input supplies. For each capacitor, the total lead length between
logic state in the output latch. Since the current pulses both ends of the capacitor and the power-supply pins
are narrow, about 2.5 ns wide, the power consumption is should not exceed 20 mm. Figure 2 illustrates the recom-
independent of mark-to-space ratio and solely dependent mended printed circuit board layout for the HCPL-9000
on frequency. or HCPL-0900. For data rates in excess of 10MBd, use of
The approximate power supply current per channel is: ground planes for both GND1 and GND2 is highly recom-
I(Input) = 40(f/fmax)(1/4) mA mended.

where f = operating frequency, fmax = 50 MHz.

Signal Status on Start-up and Shut Down

To minimize power dissipation, the input signals to the
channels of HCPL-90xx and HCPL-09xx digital isolators
are differentiated and then latched on the output side of
the isolation barrier to reconstruct the signal. This could
result in an ambiguous output state depending on power
up, shutdown and power loss sequencing. Therefore, the
designer should consider the inclusion of an initialization
signal in this start-up circuit.

VDD1 1 8 VDD2
C1 C2
HCPL-0900
HCPL-9000

IN1 2 7
VOE
or

NC 3 6 OUT1

GND1 4 5 GND2

Note: C1, C2 = 47 nF ceramic capacitors

Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900.

VDD1 VDD2
HCPL-0900
HCPL-9000

IN1 VOE
C1 C2
or

OUT1

GND1 GND2

Figure 2. Recommended Printed Circuit Board Layout.

12
Propagation Delay, Pulse Width Distortion and Propagation
Delay Skew
Propagation Delay is a figure of merit, which describes As illustrated in Figure 4, if the inputs of two or more
how quickly a logic signal propagates through a system devices are switched either ON or OFF at the same time,
as illustrated in Figure 3. tPSK is the difference between the minimum propagation
5 V CMOS
delay, either tPLH or tPHL, and the maximum propagation
INPUT
VIN 50% delay, either tPLH or tPHL.
0V
tPLH tPHL
VIN 50%
VOH
OUTPUT 90% 90%
VOUT 2.5 V CMOS
10% 10%
VOL 2.5 V
VOUT CMOS
tPSK
Figure 3. Timing Diagrams to Illustrate Propagation Delay, tPLH and tPHL.

The propagation delay from low to high, t PLH , is the VIN 50%
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low, VOUT 2.5 V
CMOS
tPHL, is the amount of time required for the ­input signal to
propagate to the output, causing the output to change
from high to low. Figure 4. Timing Diagrams to Illustrate ­Propagation Delay Skew.

Pulse Width Distortion, PWD, is the difference between tPHL

As mentioned earlier, tPSK, can determine the maximum
and tPLH and often determines the maximum data rate ca-
parallel data transmission rate. Figure 5 shows the timing
pability of a transmission system. PWD can be expressed in
diagram of a typical parallel data transmission application
percent by dividing the PWD (in ns) by the minimum pulse
with both the clock and data lines being sent through the
width (in ns) being transmitted. Typically, PWD on the order
digital isolators. The figure shows data and clock signals at
of 20 – 30% of the minimum pulse width is tolerable.
the inputs and ­outputs of the digital isolators. In this case,
Propagation Delay Skew, tPSK, and Channel-to-Channel the data is clocked off the rising edge of the clock.
Skew, tCSK, are critical parameters to consider in parallel
data transmission applications where ­synchronization of
signals on parallel data lines is a concern. If the parallel DATA

data is being sent through channels of the digital INPUTS

isolators, differences in propagation delays will cause CLOCK

the data to arrive at the ­ outputs of the digital isolators

at different times. If this difference in propagation delay
is large enough, it will limit the maximum transmission DATA

rate at which parallel data can be sent through the digital OUTPUTS
tPSK
isolators. CLOCK

tPSK
tPSK is defined as the difference between the minimum and
maximum propagation delays, either tPLH or tPHL, among two
Figure 5. Parallel Data Transmission.
or more devices which are operating ­under the same con-
ditions (i.e., the same drive current, ­supply voltage, output
load, and operating temperature). tCSK is defined as the
difference between the minimum and maximum propaga-
tion delays, either tPLH or tPHL, among two or more channels
within a single device (applicable to dual and quad channel
­devices) which are operating under the same conditions.

13
Propagation delay skew represents the uncertainty of sent through digital isolators in a parallel application is
where an edge might be after being sent through a digital twice tPSK. A cautious design should use a slightly longer
isolator. Figure 5 shows that there will be ­uncertainty in pulse width to ensure that any additional ­uncertainty in
both the data and clock lines. It is ­important that these the rest of the circuit does not cause a problem.
two areas of uncertainty not overlap, otherwise the clock
Figure 6 shows the minimum pulse width, rise and fall
signal might arrive ­ before all of the data outputs have
time, and propagation delay enable to output waveforms
settled, or some of the data outputs may start to change
for HCPL-9000 or HCPL-0900.
before the clock signal has arrived. From these consider-
ations, the ­ absolute minimum pulse width that can be

50%

VIN

tPZL
90% 90%
tPLZ
50%
VOUT tPHZ
tPZH 10% 10%

tPW
tF

tR
VOE

tPW Minimum Pulse Width tPHZ Propagation Delay, High to High Impedance
tPLZ Propagation Delay, Low to High Impedance tPZL Propagation Delay, High Impedance to Low
tPZH Propagation Delay, High Impedance to High tR Rise Time
tF Fall Time

Figure 6. Timing Diagrams to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to ­Output Waveforms for HCPL‑9000
or HCPL-0900.

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Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved. Obsoletes 5989-0803EN
AV02-0137EN - November 3, 2008