Precision Micropower, Low Dropout

Voltage References
REF19x Series
FEATURES PIN CONFIGURATIONS
Initial Accuracy: ⴞ2 mV Max 8-Lead Narrow-Body SOIC and TSSOP
Temperature Coefficient: 5 ppm/ⴗC Max (S Suffix and RU Suffix)
Low Supply Current: 45 ␮A Max
Sleep Mode: 15 ␮A Max TP 1 8 NC
Low Dropout Voltage VS 2 REF19x 7 NC
Load Regulation: 4 ppm/mA SERIES
SLEEP 3 TOP VIEW 6 OUTPUT
Line Regulation: 4 ppm/V (Not to Scale)
High Output Current: 30 mA GND 4 5 TP
Short Circuit Protection
NC = NO CONNECT
APPLICATIONS TP PINS ARE FACTORY TEST POINTS,
NO USER CONNECTION
Portable Instrumentation
A-to-D and D-to-A Converters
8-Lead Epoxy DIP (P Suffix)
Smart Sensors
Solar Powered Applications
TP 1 8 NC
Loop Current Powered Instrumentations REF19x
VS 2 SERIES 7 NC
GENERAL DESCRIPTION SLEEP 3 TOP VIEW 6 OUTPUT
REF19x series precision band gap voltage references use a pat- (Not to Scale)
GND 4 5 TP
ented temperature drift curvature correction circuit and laser
trimming of highly stable thin film resistors to achieve a very low NC = NO CONNECT
temperature coefficient and a high initial accuracy. TP PINS ARE FACTORY TEST POINTS,
NO USER CONNECTION
The REF19x series is made up of micropower, Low Dropout
Voltage (LDV) devices providing a stable output voltage from Table I.
supplies as low as 100 mV above the output voltage and consum-
ing less than 45 µA of supply current. In sleep mode, which is Part Nominal Output
enabled by applying a low TTL or CMOS level to the sleep pin, Number Voltage (V)
the output is turned off and supply current is further reduced to
REF191 2.048
less than 15 µA.
REF192 2.50
The REF19x series references are specified over the extended REF193 3.00
industrial temperature range (–40°C to +85°C) with typical REF194 4.50
performance specifications over –40°C to +125°C for applications REF195 5.00
such as automotive. REF196 3.30
All electrical grades are available in 8-lead SOIC; the PDIP and REF198 4.096
TSSOP are only available in the lowest electrical grade. Products
are also available in die form.
ORDERING GUIDE
Test Pins (TP)
The test pins, Pin 1 and Pin 5, are reserved for in-package Temperature Package Package
Zener-zap. To achieve the highest level of accuracy at the output, Model Range Description Option1
the Zener-zapping technique is used to trim the output voltage.
REF19xGP –40°C to +85°C 8-Lead Plastic DIP2 N-8
Since each unit may require a different amount of adjustment, the
REF19xES3 –40°C to +85°C 8-Lead SOIC SOIC-8
resistance value at the test pins will vary widely from pin to pin as
REF19xFS3 –40°C to +85°C 8-Lead SOIC SOIC-8
well as from part to part. The user should not make any physical
REF19xGS –40°C to +85°C 8-Lead SOIC SOIC-8
nor electrical connections to Pin 1 and Pin 5.
REF19xGRU4 –40°C to +85°C 8-Lead TSSOP RU-8
REF19xGBC 25°C DICE
NOTES
1
N = Plastic DIP, SOIC = Small Outline, RU = Thin Shrink Small Outline.
2
REV. E 8-lead plastic DIP is only available in “G” grade.
3
REF193 and REF196 are only available in “G” grade.
4
Available for REF192, REF195, and REF198 only.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = 25ⴗC, unless otherwise noted.)
S A

Parameter Symbol Condition Min Typ Max Unit

1
INITIAL ACCURACY
E Grade VO IOUT = 0 mA 2.046 2.048 2.050 V
F Grade 2.043 2.053 V
G Grade 2.038 2.058 V
LINE REGULATION2
E Grade ⌬VO /⌬VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 4 10 ppm/mA
F and G Grades 6 15 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.15 V, ILOAD = 2 mA 0.95 V
VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 30 mA 1.55 V
LONG-TERM STABILITY3 DVO 1000 Hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 20 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +85ⴗC, unless otherwise noted.)

S A

Parameter Symbol Condition Min Typ Max Unit

TEMPERATURE COEFFICIENT1, 2
E” Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 C 5 15 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.15 V, ILOAD = 2 mA 0.95 V
VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 25 mA 1.55 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–2– REV. E
 REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)
S A

Parameter Symbol Condition Min Typ Max Unit

1, 2
TEMPERATURE COEFFICIENT
E Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 ppm/V
F and G Grades 20 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 10 ppm/mA
F and G Grades 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 20 mA 1.55 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. E –3–
REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = 25ⴗC, unless otherwise noted.)
S A

Parameter Symbol Condition Min Typ Max Unit

1
INITIAL ACCURACY
E Grade VO IOUT = 0 mA 2.498 2.500 2.502 V
F Grade 2.495 2.505 V
G Grade 2.490 2.510 V
LINE REGULATION2
E Grade ⌬VO /⌬VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 4 10 ppm/mA
F and G Grades 6 15 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.5 V, ILOAD = 10 mA 1.00 V
VS = 3.9 V, ILOAD = 30 mA 1.40 V
LONG-TERM STABILITY3 DVO 1000 Hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 25 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = –40ⴗC ≤ T ≤ +85ⴗC, unless otherwise noted.)

S A A

Parameter Symbol Condition Min Typ Max Unit

1, 2
TEMPERATURE COEFFICIENT
E Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 5 15 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.5 V, ILOAD = 10 mA 1.00 V
VS = 4.0 V, ILOAD = 25 mA 1.50 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–4– REV. E
 REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)
S A

Parameter Symbol Condition Min Typ Max Unit

1, 2
TEMPERATURE COEFFICIENT
E Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 ppm/V
F and G Grades 20 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 10 ppm/mA
F and G Grades 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.5 V, ILOAD = 10 mA 1.00 V
VS = 4.0 V, ILOAD = 20 mA 1.50 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 3.3 V, TA = 25ⴗC, unless otherwise noted.)

Parameter Symbol Condition Min Typ Max Unit

INITIAL ACCURACY1
G Grade VO IOUT = 0 mA 2.990 3.0 3.010 V
2
LINE REGULATION
G Grades ⌬VO /⌬VIN 3.3 V, ≤ VS ≤ 15 V, IOUT = 0 mA 4 8 ppm/V
2
LOAD REGULATION
G Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 6 15 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.0 V, ILOAD = 30 mA 1.00 V
LONG-TERM STABILITY 3 DVO 1000 Hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 30 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

REV. E –5–
REF19x Series
REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 3.3 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
1, 2
TEMPERATURE COEFFICIENT
G Grade3 TCVO/°C IOUT = 0 mA 10 25 ppm/°C
4
LINE REGULATION
G Grade ⌬VO /⌬VIN 3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 20 ppm/V
4
LOAD REGULATION
G Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 10 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.1 V, ILOAD = 30 mA 1.10 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)

S A

Parameter Symbol Condition Min Typ Max Unit

1, 2
TEMPERATURE COEFFICIENT
G Grade3 TCVO/°C IOUT = 0 mA 10 ppm/°C
4
LINE REGULATION
G Grade ⌬VO /⌬VIN 3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA 20 ppm/V
4
LOAD REGULATION
G Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 10 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.1 V, ILOAD = 20 mA 1.10 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–6– REV. E
 REF19x Series
REF194–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, T = 25ⴗC, unless otherwise noted.)
S A

Parameter Symbol Condition Min Typ Max Unit

1
INITIAL ACCURACY
E Grade VO IOUT = 0 mA 4.498 4.5 4.502 V
F Grade 4.495 4.505 V
G Grade 4.490 4.510 V
LINE REGULATION2
E Grade ⌬VO /⌬VIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ⌬VO /⌬VLOAD VS = 5.8 V, 0 mA ≤ IOUT ≤ 30 mA 2 4 ppm/mA
F and G Grades 4 8 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 5.00 V, ILOAD = 10 mA 0.50 V
VS = 5.8 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY3 DVO 1000 Hours @ 125°C 2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 45 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ VS = 5.0 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)

Parameter Symbol Condition Min Typ Max Unit
1, 2
TEMPERATURE COEFFICIENT
E Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 5.80 V, 0 mA ≤ IOUT ≤ 25 mA 5 15 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 5.00 V, ILOAD = 10 mA 0.5 V
VS = 5.80 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. E –7–
REF19x Series
REF194–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)
S A

Parameter Symbol Condition Min Typ Max Unit

1, 2
TEMPERATURE COEFFICIENT
E Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
F and G Grades 10 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 5.80 V, mA 0 ≤ IOUT ≤ 20 mA 5 ppm/mA
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 5.10 V, ILOAD = 10 mA 0.60 V
VS = 5.95 V, ILOAD = 20 mA 1.45 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–8– REV. E
 REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.10 V, T = 25ⴗC, unless otherwise noted.)
S A

Parameter Symbol Condition Min Typ Max Unit

1
INITIAL ACCURACY
E Grade VO IOUT = 0 mA 4.998 5.0 5.002 V
F Grade 4.995 5.005 V
G Grade 4.990 5.010 V
LINE REGULATION2
E Grade ⌬VO /⌬VIN 5.10 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ⌬VO /⌬VLOAD VS = 6.30 V, 0 mA ≤ IOUT ≤ 30 mA 2 4 ppm/mA
F and G Grades 4 8 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 5.50 V, ILOAD = 10 mA 0.50 V
VS = 6.30 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY3 DVO 1000 Hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 50 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ VS = 5.15 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)

Parameter Symbol Condition Min Typ Max Unit
1, 2
TEMPERATURE COEFFICIENT
E Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 5.15 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 6.30 V, 0 mA ≤ IOUT ≤ 25 mA 5 10 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 5.50 V, ILOAD = 10 mA 0.50 V
VS = 6.30 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. E –9–
REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.20 V, –40ⴗC ≤ T ≤ +125ⴗC, unless otherwise noted.)
S A

Parameter Symbol Condition Min Typ Max Unit

1, 2
TEMPERATURE COEFFICIENT
E Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 5.20 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
F and G Grades 10 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 6.45 V, 0 mA ≤ IOUT ≤ 20 mA 5 ppm/mA
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 5.60 V, ILOAD = 10 mA 0.60 V
VS = 6.45 V, ILOAD = 20 mA 1.45 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REF196–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.5 V, T = 25ⴗC, unless otherwise noted.)
S A

Parameter Symbol Condition Min Typ Max Unit

1
INITIAL ACCURACY
G Grade VO IOUT = 0 mA 3.290 3.3 3.310 V
LINE REGULATION2
G Grades ⌬VO /⌬VIN 3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA 4 8 ppm/V
2
LOAD REGULATION
G Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 30 mA 6 15 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 4.1 V, ILOAD = 10 mA 0.80 V
VS = 4.3 V, ILOAD = 30 mA 1.00 V
LONG-TERM STABILITY3 DVO 1000 Hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 33 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

–10– REV. E
 REF19x Series
REF196–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 3.5 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
1, 2
TEMPERATURE COEFFICIENT
G Grade3 TCVO/°C IOUT = 0 mA 10 25 ppm/°C
4
LINE REGULATION
G Grade ⌬VO /⌬VIN 3.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 20 ppm/V
4
LOAD REGULATION
G Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 25 mA 10 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 4.1 V, ILOAD = 10 mA 0.80 V
VS = 4.3 V, ILOAD = 25 mA 1.00 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ VS = 3.50 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)

Parameter Symbol Condition Min Typ Max Unit
1, 2
TEMPERATURE COEFFICIENT
G Grade3 TCVO/°C IOUT = 0 mA 10 ppm/°C
4
LINE REGULATION
G Grade ⌬VO /⌬VIN 3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA 20 ppm/V
4
LOAD REGULATION
G Grade ⌬VO /⌬VLOAD VS = 5.0 V, 0 mA ≤ IOUT ≤ 20 mA 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 4.1 V, ILOAD = 10 mA 0.80 V
VS = 4.4 V, ILOAD = 20 mA 1.10 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. E –11–
REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 5.0 V, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
1
INITIAL ACCURACY
E Grade VO IOUT = 0 mA 4.094 4.096 4.098 V
F Grade 4.091 4.101 V
G Grade 4.086 4.106 V
LINE REGULATION2
E Grade ⌬VO /⌬VIN 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
F and G Grades 4 8 ppm/V
LOAD REGULATION2
E Grade ⌬VO /⌬VLOAD VS = 5.4 V, 0 mA ≤ IOUT ≤ 30 mA 2 4 ppm/mA
F and G Grades 4 8 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 4.6 V, ILOAD = 10 mA 0.50 V
VS = 5.4 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY3 DVO 1000 Hours @ 125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 40 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at 125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, –40ⴗC ≤ T ≤ +85ⴗC, unless otherwise noted.)

S A

Parameter Symbol Condition Min Typ Max Unit

1, 2
TEMPERATURE COEFFICIENT
E Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
F Grade 5 10 ppm/°C
G Grade3 10 25 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
F and G Grades 10 20 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 5.4 V, 0 mA ≤ IOUT ≤ 25 mA 5 10 ppm/mA
F and G Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 4.6 V, ILOAD = 10 mA 0.50 V
VS = 5.4 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–12– REV. E
 REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 5.0 V, –40ⴗC ≤ TA ≤ +125ⴗC, unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
1, 2
TEMPERATURE COEFFICIENT
E Grade TCVO /°C IOUT = 0 mA 2 ppm/°C
F Grade 5 ppm/°C
G Grade3 10 ppm/°C
LINE REGULATION4
E Grade ⌬VO /⌬VIN 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
F and G Grades 10 ppm/V
LOAD REGULATION4
E Grade ⌬VO /⌬VLOAD VS = 5.6 V, 0 mA ≤ IOUT ≤ 20 mA 5 ppm/mA
F and G Grades 10 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 4.7 V, ILOAD = 10 mA 0.60 V
VS = 5.6 V, ILOAD = 20 mA 1.50 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm °C.
TCV O = (VMAX – VMIN)/ VO(TMAX – TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. E –13–
REF19x Series
WAFER TEST LIMITS (@ I LOAD = 0 mA, TA = 25ⴗC, unless otherwise noted.)
Parameter Symbol Condition Limit Unit
INITIAL ACCURACY
REF191 VO 2.043/2.053 V
REF192 2.495/2.505 V
REF193 2.990/3.010 V
REF194 4.495/4.505 V
REF195 4.995/5.005 V
REF196 3.290/3.310 V
REF198 4.091/4.101 V
LINE REGULATION ⌬VO /⌬VIN (VO + 0.5 V) < VIN < 15 V, IOUT = 0 mA 15 ppm/V
LOAD REGULATION ⌬VO /⌬ILOAD 0 mA < ILOAD < 30 mA, VIN = (VO + 1.3 V) 15 ppm/mA
DROPOUT VOLTAGE VO – V+ ILOAD = 10 mA 1.25 V
ILOAD = 30 mA 1.55 V
SLEEP MODE INPUT
Logic Input High VIH 2.4 V
Logic Input Low VIL 0.8 V
SUPPLY CURRENT VIN = 15 V No Load 45 µA
Sleep Mode No Load 15 µA
For proper operation, a 1 µF capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer probe to the limits shown.
Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications
based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS 1 DICE CHARACTERISTICS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V
OUTPUT OUTPUT
Output to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VS + 0.3 V 6 6
Output to GND Short-Circuit Duration . . . . . . . . . Indefinite
Storage Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
REF19x . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
Package Type ␪JA2 ␪JC Unit
8-Lead PDIP (P) 103 43 °C/W
8-Lead SOIC (S) 158 43 °C/W
8-Lead TSSOP (RU) 240 43 °C/W
2 3 4
Vⴙ SLEEP GND
NOTES
1
Absolute maximum rating applies to both DICE and packaged parts, unless
REF19x Die Size 0.041” ⫻ 0.057”, 2,337 Square Mils
otherwise noted.
2
θJA is specified for worst case conditions, i.e., θJA is specified for device in socket for Substrate Is Connected to V+, Number of Transistors:
PDIP, and θJA is specified for device soldered in circuit board for SOIC package. Bipolar 25, MOSFET4. Process: CBCMOS1

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
REF19x features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

–14– REV. E
 Typical Performance Characteristics–REF19x Series
5.004 50

3 TYPICAL PARTS 45 BASED ON 600 –40ⴗC TA +85ⴗC

5.003 5.15V < VIN < 15V UNITS, 4 RUNS
40

PERCENTAGE OF PARTS – %
5.002
OUTPUT VOLTAGE – V

35
5.001
30

5.000 25

20
4.999
15
4.998
10
4.997 5

4.996 0
–50 –25 0 25 50 75 100 –20 –15 –10 –5 0 5 10 15 20
TEMPERATURE – ⴗC TC – VOUT – ppm/ⴗC

TPC 1. REF195 Output Voltage vs. Temperature TPC 4. TC – VOUT Distribution

32 40

28 35
5.15V VS 15V NORMAL MODE
LOAD REGULATION – ppm/V

24 30

SUPPLY CURRENT – ␮A
–40ⴗC
20 25

16 20
+25ⴗC

12 15
+85ⴗC
8 10

SLEEP MODE
4 5

0 0
0 5 10 15 20 25 30 –50 –25 0 25 50 75 100
ILOAD – mA TEMPERATURE – ⴗC

TPC 2. REF195 Load Regulation vs. ILOAD TPC 5. Quiescent Current vs. Temperature

20 –6

0mA ⱕ IOUT < 25mA

+85ⴗC
16 –5
LINE REGULATION – ppm/mA

SLEEP PIN CURRENT – ␮A

+25ⴗC –4
12
–40ⴗC
–3
8

–2
VL
4
–1 VH

0 0
4 6 8 10 12 14 16
–50 –25 0 25 50 75 100
VIN – V
TEMPERATURE – ⴗC

TPC 3. REF195 Line Regulation vs. VIN TPC 6. SLEEP Pin Current vs. Temperature

REV. E –15–
REF19x Series
2
VIN = 15V 6
4 REF19x
0 10mA
1␮F
0
–20
RIPPLE REJECTION – dB

–40 TPC 9b. Load Transient Response Measurement Circuit

–60

–80

–100 2V
100

90
–120

10 100 1k 10k 100k 1M

FREQUENCY – Hz
1mA
LOAD
TPC 7a. Ripple Rejection vs. Frequency 30mA
10
LOAD
0%
2V 100␮s
10␮F

10␮F TPC 10a. Power ON Response Time

1k⍀ 2 6
VIN = +15V REF19x OUTPUT

10␮F 1␮F 1k⍀

4
2 6
REF
4 REF19x
VIN = 7V 1␮F
TPC 7b. Ripple Rejection vs. Frequency
Measurement Circuit
TPC 10b. Power ON Response Time Measurement Circuit

VIN = 7V 2 6 200V
REF19x VG = 2V p-p
1␮F 4 1␮F 5V
Z VS = 4V ON 100

90
OFF

4
VOUT IL = 1mA
3
IL = 10mA
ZO – ⍀

2 10

0%
1 1V 2ms
0
10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz TPC 11a. SLEEP Response Time
TPC 8. Output Impedance vs. Frequency
VIN = 15V 2
6 VOUT
3 REF19x
5V
OFF 100 4 1␮F
90
ON

TPC 11b. SLEEP Response Time Measurement Circuit

10

0%
20mV 100␮s

TPC 9a. Load Transient Response

–16– REV. E
 REF19x Series
35

30

25

LOAD CURRENT – mA
5V
100 20
90

15

10

5
10

0% 0
200mV 200␮s 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
REF195 DROPOUT VOLTAGE – V

TPC 12. Line Transient Response TPC 13. Dropout Voltage vs. Load Current

+V Output Voltage Bypassing

For stable operation, low dropout voltage regulators and refer-
ences generally require a bypass capacitor connected from their
VOUT pins to their GND pins. Although the REF19x family of
VOUT
references is capable of stable operation with capacitive loads
exceeding 100 µF, a 1 µF capacitor is sufficient to guarantee rated
SLEEP (SHUTDOWN)
performance. The addition of a 0.1 µF ceramic capacitor in parallel
with the bypass capacitor will improve load current transient
performance. For best line voltage transient performance, it is
recommended that the voltage inputs of these devices be bypassed
with a 10 µF electrolytic capacitor in parallel with a 0.1 µF
ceramic capacitor.
GND Sleep Mode Operation
All REF19x devices include a sleep capability that is TTL/CMOS
Figure 1. Simplified Schematic
level compatible. Internally, a pull-up current source to VIN is
connected at the SLEEP pin. This permits the SLEEP pin to be
APPLICATIONS SECTION
driven from an open collector/drain driver. A logic LOW or a 0 V
Output Short Circuit Behavior
condition on the SLEEP pin is required to turn the output stage
The REF19x family of devices is totally protected from damage
OFF. During sleep, the output of the references becomes a high
due to accidental output shorts to GND or to V+. In the event
impedance state where its potential would then be determined
of an accidental short circuit condition, the reference device will
by external circuitry. If the sleep feature is not used, it is recom-
shut down and limit its supply current to 40 mA.
mended that the SLEEP pin be connected to VIN (Pin 2).
Device Power Dissipation Considerations
Basic Voltage Reference Connections
The REF19x family of references is capable of delivering load
The circuit in Figure 2 illustrates the basic configuration for the
currents to 30 mA with an input voltage that ranges from 3.3 V
REF19x family of references. Note the 10 µF/0.1 µF bypass net-
to 15 V. When these devices are used in applications with large
work on the input and the 1 µF/0.1 µF bypass network on the
input voltages, care should be exercised to avoid exceeding
output. It is recommended that no connections be made to Pins 1,
these devices’ maximum internal power dissipation. Exceeding
5, 7, and 8. If the sleep feature is not required, Pin 3 should be
the published specifications for maximum power dissipation or
connected to VIN.
junction temperature could result in premature device failure.
The following formula should be used to calculate a device’s
maximum junction temperature or dissipation: NC 1 8 NC
VIN
TJ – TA 2 7 NC
PD = REF19x OUTPUT
θ JA 10␮F 0.1␮F
SLEEP 3 6
In this equation, TJ and TA are the junction and ambient tempera- 1␮F 0.1␮F
4 5 NC TANT
tures, respectively, PD is the device power dissipation, and θJA is
the device package thermal resistance. NC = NO CONNECT

Figure 2. Basic Voltage Reference Configuration

REV. E –17–
REF19x Series
Membrane Switch Controlled Power Supply clamps drive to Q1 at about 300 mA of load current with values
With output load currents in the tens of mA, the REF19x family as shown. With this separation of control and power functions,
of references can operate as a low dropout power supply in hand- dc stability is optimum, allowing best advantage use of premium
held instrument applications. In the circuit shown in Figure 3, grade REF19x devices for U1. Of course, load management
a membrane ON/OFF switch is used to control the operation of should still be exercised. A short, heavy, low DCR (dc resistance)
the reference. During an initial power-on condition, the SLEEP conductor should be used from U1–6 to the VOUT sense point
pin is held to GND by the 10 kΩ resistor. Recall that this condition “S,” where the collector of Q1 connects to the load, point “F.”
disables (read: three-state) the REF19x output. When the mem- Because of the current limiting configuration, the dropout voltage
brane ON switch is pressed, the SLEEP pin is momentarily pulled to circuit is raised about 1.1 V over that of the REF19x devices, due
VIN, enabling the REF19x output. At this point, current through to the VBE of Q1 and the drop across current sense resistor R4.
the 10 kΩ is reduced and the internal current source connected However, overall dropout is typically still low enough to allow
to the SLEEP pin takes control. Pin 3 assumes and remains at the operation of a 5 V to 3.3 V regulator/reference using the REF196
same potential as VIN. When the membrane OFF switch is pressed, for U1 as noted, with a VS as low as 4.5 V and a load current
the SLEEP pin is momentarily connected to GND, which once of 150 mA.
again disables the REF19x output.
The requirement for a heat sink on Q1 depends on the maximum
input voltage and short circuit current. With VS = 5 V and a
NC 1 8 NC
VIN
300 mA current limit, the worst case dissipation of Q1 is 1.5 W,
2 7 NC less than the TO-220 package 2 W limit. However, if smaller
REF19x OUTPUT
1k⍀
3 6 TO-39 or TO-5 packaged devices such as the 2N4033 are used,
5%
1␮F the current limit should be reduced to keep maximum dissi-
4 5 NC TANT
ON pation below the package rating. This is accomplished by simply
raising R4.
10k⍀
OFF A tantalum output capacitor is used at C1 for its low ESR
NC = NO CONNECT (Equivalent Series Resistance), and the higher value is required
for stability. Capacitor C2 provides input bypassing and can be
Figure 3. Membrane Switch Controlled Power Supply an ordinary electrolytic.
Current-Boosted References with Current Limiting Shutdown control of the booster stage is shown as an option,
While the 30 mA rated output current of the REF19x series is and when used some cautions are in order. Because of the addi-
higher than typical of other reference ICs, it can be boosted to tional active devices in the VS line to U1, direct drive to Pin 3
higher levels if desired with the addition of a simple external does not work as with an unbuffered REF19x device. To enable
PNP transistor, as shown in Figure 4. Full time current limiting shutdown control, the connection to U1-2 is broken at the “X,”
is used for protection of the pass transistor against shorts. and diode D1 then allows a CMOS control source VC to drive
U1-3 for ON-OFF operation. Startup from shutdown is not as
R4
Q1 clean under heavy load as it is in basic REF19x series and can
TIP32A
+VS = 6V TO 9V
2⍀ (SEE TEXT) OUTPUT TABLE require several milliseconds under load. Nevertheless, it is still
(SEE TEXT)
R1 U1 VOUT (V) effective and can fully control 150 mA loads. When shutdown
1k⍀
Q2 control is used, heavy capacitive loads should be minimized.
2N3906 REF192 2.5
R2 REF193 3.0
1.5k⍀ REF196 3.3
A Negative Precision Reference without Precision Resistors
C2
100␮F/25V
REF194 4.5 In many current-output CMOS DAC applications where the
C3 REF195 5.0
D1 0.1␮F
F output signal voltage must be of the same polarity as the reference
U1 S +VOUT
VC REF196 3.3V
voltage, it is often required to reconfigure a current-switching DAC
1N4148
(SEE TEXT
(SEE TABLE)
C1 @ 150mA into a voltage-switching DAC through the use of a 1.25 V reference,
10␮F/25V
ON SLEEP) (TANTALUM) an op amp, and a pair of resistors. Using a current-switching
R3 R1
1.82k⍀ DAC directly requires an additional operational amplifier at the
S
VS VOUT
output to reinvert the signal. A negative voltage reference is then
COMMON F COMMON desirable from the point that an additional operational amplifier
is not required for either reinversion (current-switching mode) or
Figure 4. A Boosted 3.3 V Reference with Current Limiting amplification (voltage switching mode) of the DAC output voltage.
In general, any positive voltage reference can be converted into
In this circuit, the power supply current of reference U1 flowing a negative voltage reference through the use of an operational
through R1–R2 develops a base drive for Q1, whose collector amplifier and a pair of matched resistors in an inverting configura-
provides the bulk of the output current. With a typical gain of tion. The disadvantage to that approach is that the largest single
100 in Q1 for 100 mA to 200 mA loads, U1 is never required to source of error in the circuit is the relative matching of the
furnish more than a few mA, so this factor minimizes temperature resistors used.
related drift. Short circuit protection is provided by Q2, which

–18– REV. E
 REF19x Series
The circuit illustrated in Figure 5 avoids the need for tightly VOUT2 is the sum of this voltage and the terminal voltage of U2.
matched resistors with the use of an active integrator circuit. In U1 and U2 are simply chosen for the two voltages that supply
this circuit, the output of the voltage reference provides the input the required outputs (see Table I). If, for example, both U1 and
drive for the integrator. The integrator, to maintain circuit equi- U2 are REF192s, the two outputs are 2.5 V and 5.0 V.
librium, adjusts its output to establish the proper relationship While this concept is simple, some cautions are in order. Since
between the reference’s VOUT and GND. Thus, any desired the lower reference circuit must sink a small bias current from
negative output voltage can be chosen by simply substituting for U2 (50 µA to 100 µA), plus the base current from the series PNP
the appropriate reference IC. The sleep feature is maintained in output transistor in U2, either the external load of U1 or R1
the circuit with the simple addition of a PNP transistor and a must provide a path for this current. If the U1 minimum load is
10 kΩ resistor. One caveat with this approach should be men- not well defined, resistor R1 should be used, set to a value that
tioned: although rail-to-rail output amplifiers work best in the will conservatively pass 600 µA of current with the applicable
application, these operational amplifiers require a finite amount VOUT1 across it. Note that the two U1 and U2 reference circuits
(mV) of headroom when required to provide any load current. are locally treated as macrocells, each having its own bypasses at
The choice for the circuit’s negative supply should take this issue input and output for best stability. Both U1 and U2 in this circuit
into account. can source dc currents up to their full rating. The minimum
input voltage, VS, is determined by the sum of the outputs, VOUT2,
VIN
plus the dropout voltage of U2.
10k⍀ A related variation on stacking two three-terminal references
SLEEP 2N3906
TTL/CMOS 2
is shown in Figure 6, where U1, a REF192, is stacked with a
VIN 1␮F
two-terminal reference diode such as the AD589. Like the three-
1k⍀
3 SLEEP VOUT 6 terminal stacked reference above, this circuit provides two outputs,
REF19x
+5V VOUT1 and VOUT2, which are the individual terminal voltages of
GND
D1 and U1 respectively. Here this is 1.235 and 2.5, which pro-
100⍀
4 1␮F A1 –VREF vides a VOUT2 of 3.735 V. When using two-terminal reference
10k⍀ 100k⍀ diodes such as D1, the rated minimum and maximum device
–5V currents must be observed and the maximum load current from
A1 = 1/2 OP295,
1/2 OP291
VOUT1 can be no greater than the current set up by R1 and VO(U1).
In the case with VO(U1) equal to 2.5 V, R1 provides a 500 µA
Figure 5. A Negative Precision Voltage Reference bias to D1, so the maximum load current available at VOUT1 is
Uses No Precision Resistors 450 µA or less.
Stacking Reference ICs for Arbitrary Outputs
+VS
Some applications may require two reference voltage sources that VS > VOUT2 +0.15V
are a combined sum of standard outputs. The circuit of Figure 6 U1 +VOUT2
shows how this “stacked output” reference can be implemented. C1 REF192 C2 R1 3.735V
0.1␮F VO (U1) 1␮F 4.99k⍀
(SEE TEXT)
OUTPUT TABLE
U1/U2 VOUT1 (V) VOUT2 (V)
+VOUT1
REF192/REF192 2.5 5.0 1.235V
REF192/REF194 2.5 7.0 D1 C3
VO (D1) 1␮F
+VS REF192/REF195 2.5 7.5 AD589
VS > VOUT2 +0.15V
C1 VIN VOUT
0.1␮F U2
+VOUT2 COMMON COMMON
REF19x
(SEE TABLE) C2
VO (U2)
1␮F
Figure 7. Stacking Voltage References with the REF19x
A Precision Current Source
C3 Many times, in low power applications, the need arises for a
0.1␮F U1
REF19x +VOUT1 precision current source that can operate on low supply voltages.
(SEE TABLE)
VO (U1)
C4 R1
3.9k⍀
As shown in Figure 8, any one of the devices in the REF19x
1␮F
(SEE TEXT) family of references can be configured as a precision current
VIN
source. The circuit configuration illustrated is a floating current
VOUT
COMMON COMMON source with a grounded load. The reference’s output voltage is
bootstrapped across RSET, which sets the output current into the
Figure 6. Stacking Voltage References with the REF19x load. With this configuration, circuit precision is maintained for
load currents in the range from the reference’s supply current
Two reference ICs are used, fed from a common unregulated
(typically, 30 µA) to approximately 30 mA. The low dropout
input, VS. The outputs of the individual ICs are simply con-
voltage of these devices maximizes the current source’s output
nected in series as shown, which provides two output voltages,
voltage compliance without excess headroom.
VOUT1 and VOUT2. VOUT1 is the terminal voltage of U1, while

REV. E –19–
REF19x Series
VIN OUTPUT TABLE
U1/U2 VC* VOUT (V)
REF195/ HI 5.0
REF196 LO 3.3
VIN
+VS = 6V REF194/ HI 4.5
REF19x REF195 LO 5.0
SLEEP VREF *CMOS LOGIC LEVELS
GND 1 2 3 4 U1
R1 VC REF19x
1␮F RSET
ISY (SEE TABLE)
ADJUST P1 U3A U3B
74HC04 74HC04
IOUT +VOUT
VIN I OUT ⴛ RL (MAX) + VSY (MIN)
V RL
IOUT = OUT + ISY (REF19x) U2
RSET
REF19x C2
VOUT E.G. REF195 : VOUT = 5V 1␮F
>> ISY (SEE TABLE)
RSET IOUT = 5mA
R1 = 953⍀ C1
P1 = 100⍀, 10-TURN 0.1␮F
VIN VOUT
Figure 8. A Low Dropout, Precision Current Source COMMON COMMON

The circuit’s governing equations are:

Figure 9. Switched Output Reference
V IN = IOUT × RL (max)+V SY (min, REF19x) Using dissimilar REF19x series devices with this configuration
V OUT allows logic selection between the U1/U2 specified terminal
IOUT = + I SY (REF19x)
RSET voltages. For example, with U1 (a REF195) and U2 (a REF196),
V OUT as noted in the table, changing the CMOS compatible VC logic
〉〉I (REF19x)
RSET SY control voltage from HI to LO selects between a nominal output
Switched Output 5 V/3.3 V Reference of 5.000 V and 3.300 V and vice versa. Other REF19x family
Applications often require digital control of reference voltages, units can also be used for U1/U2, with similar operation in a
selecting between one stable voltage and a second. With the logic sense, but with outputs as per the individual paired devices
sleep feature inherent to the REF19x series, switched output (see table, again). Of course, the exact output voltage tolerance,
reference configurations are easily implemented with relatively drift, and overall quality of the reference voltage will be consistent
little additional hardware. with the grade of individual U1 and U2 devices.
The circuit of Figure 9 illustrates the general technique, which Because of the nature of the wire–OR, there is one application
takes advantage of the output “wire-OR” capability of the REF19x caveat that should be understood about this circuit. Since U1
device family. When OFF, a REF19x device is effectively an and U2 can only source current effectively, negative going output
open circuit at the output node with respect to the power supply. voltage changes, which require the sinking of current, will neces-
When ON, a REF19x device can source current up to its current sarily take longer than positive going changes. In practice, this
rating, but sink only a few µA (essentially just the relatively low means that the circuit is quite fast when undergoing a transition
current of the internal output scaling divider). As a result, for from 3.3 V to 5 V, but the transition from 5 V to 3.3 V will take
two devices wired together at their common outputs, the output longer. Exactly how much longer will be a function of the load
voltage is simply that of the ON device. The OFF state device resistance, RL, seen at the output and the typical 1 µF value of
will draw a small standby current of 15 µA (max), but otherwise C2. In general, a conservative transition time here will be on the
will not interfere with operation of the ON device, which can order of several milliseconds for load resistances in the range of
operate to its full current rating. Note that the two devices in 100 Ω to 1 kΩ. Note that for highest accuracy at the new output
the circuit conveniently share both input and output capacitors, voltage, several time constants should be allowed (>7.6 time
and with CMOS logic drive, it is power efficient. constants for <1/2 LSB error @ 10 bits, for example).

–20– REV. E
 REF19x Series
Kelvin Connections A Fail-Safe 5 V Reference
In many portable instrumentation applications where PC board Some critical applications require a reference voltage to be main-
cost and area go hand-in-hand, circuit interconnects are very tained constant, even with a loss of primary power. The low standby
often of dimensionally minimum width. These narrow lines power of the REF19x series and the switched output capability
can cause large voltage drops if the voltage reference is required allow a “fail-safe” reference configuration to be implemented
to provide load currents to various functions. In fact, a cir- rather easily. This reference maintains a tight output voltage
cuit’s interconnects can exhibit a typical line resistance of tolerance for either a primary power source (ac line derived) or
0.45 mΩ/square (1 oz. Cu, for example). In those applications a standby (battery derived) power source, automatically switching
where these devices are configured as low dropout voltage regu- between the two as the power conditions change.
lators, these wiring voltage drops can become a large source of The circuit in Figure 11 illustrates the concept, which borrows
error. To circumvent this problem, force and sense connections from the switched output idea of Figure 8, again using the REF19x
can be made to the reference through the use of an operational device family output “wire-OR” capability. In this case, since a
amplifier, as shown in Figure 10. This method provides a means constant 5 V reference voltage is desired for all conditions, two
by which the effects of wiring resistance voltage drops can be REF195 devices are used for U1 and U2, with their ON/OFF
eliminated. Load currents flowing through wiring resistance switching controlled by the presence or absence of the primary
produce an I-R error (ILOAD ⫻ RWIRE) at the load. However, the dc supply source, VS. VBAT is a 6 V battery backup source that sup-
Kelvin connection overcomes the problem by including the plies power to the load only when VS fails. For normal (VS present)
wiring resistance within the forcing loop of the op amp. Since the power conditions, VBAT sees only the 15 µA (max) standby current
op amp senses the load voltage, op amp loop control forces the drain of U1 in its OFF state.
output to compensate for the wiring error and to produce the
correct voltage at the load. Depending on the reference device In operation, it is assumed that for all conditions either U1 or U2
chosen, operational amplifiers that can be used in this application is ON and a 5 V reference output is available. With this voltage
are the OP295, the OP291, and the OP183/OP283. constant, a scaled down version is applied to the comparator IC
U3, providing a fixed 0.5 V input to the (–) input for all power
VIN VIN conditions. The R1–R2 divider provides a signal to the U3 (+)
RLW
+VOUT input proportional to VS, which switches U3 and U1/U2 dependent
SENSE upon the absolute level of VS. Op amp U3 is configured here as
VIN 2
1
RLW
+VOUT
a comparator with hysteresis, which provides for clean, noise free
REF19x A1
SLEEP VOUT
3 FORCE output switching. This hysteresis is important to eliminate rapid
GND
1␮F
RL switching at the threshold due to VS ripple. Further, the device
100k⍀
A1 = 1/2 OP295
chosen is the AD820, a rail-to-rail output device that provides
1/2 OP292 HI and LO output states within a few mV of VS and ground for
1/2 OP283
accurate thresholds and compatible drive for U2 for all VS condi-
Figure 10. A Low Dropout, Kelvin Connected tions. R3 provides positive feedback for circuit hysteresis, changing
Voltage Reference the threshold at the (+) input as a function of U3’s output.

+VBAT
C2
0.1␮F
+VS
U1
R1 REF195
1.1M⍀ R3 R6
10M⍀ 5.000V
100⍀ Q1
C1
2N3904
3 0.1␮F
7
6
2
U3 C3
4 AD820 1␮F
R2 U2
100k⍀ REF195
R4
900k⍀
C4 R5
0.1␮F 100k⍀
VS, VBAT VOUT
COMMON COMMON

Figure 11. A Fail-Safe 5 V Reference

REV. E –21–
REF19x Series
For VS levels lower than the LOWER threshold, U3’s output is 100⍀
low, thus U2 and Q1 are OFF, while U1 is ON. For VS levels 10␮F
higher than the UPPER threshold, the situation reverses, with REF195
U1 OFF and both U2 and Q1 ON. In the interest of battery
10␮F 1␮F
power conservation, all of the comparison switching circuitry
is powered from VS and is arranged so that when VS fails, the
57k⍀
default output comes from U1. 1% 0.1␮F

For the R1–R3 values as shown, the LOWER/UPPER VS switching

thresholds are approximately 5.5 V and 6 V, respectively. These
can obviously be changed to suit other VS supplies, as can the 10k⍀ 1/4
2N2222
0.1␮F 1% OP492
REF19x devices used for U1 and U2, over a range of 2.5 V to
5 V of output. U3 can operate down to a VS of 3.3 V, which is
generally compatible with all family devices.
500⍀
A Low Power, Strain Gage Circuit 0.1%

As shown in Figure 12, the REF19x family of references can be

used in conjunction with low supply voltage operational amplifi-
ers, such as the OP492 and the OP283, in a self-contained strain 10k⍀ 0.01␮F
1%
gage circuit. In this circuit, the REF195 was used as the core of 20k⍀
1%
this low power, strain gage circuit. Other references can be easily
20k⍀
accommodated by changing circuit element values. The references 1%
1/4
play a dual role as the voltage regulator to provide the supply OP492
1/4
voltage requirements of the strain gage and the operational OP492 OUTPUT
2.21k⍀ 10k⍀
amplifiers as well as a precision voltage reference for the current 1%
source used to stimulate the bridge. A distinct feature of the
circuit is that it can be remotely controlled ON or OFF by digital 20k⍀
means via the SLEEP pin. 1/4 1%
OP492
20k⍀
1%

Figure 12. A Low Power, Strain Gage Circuit

–22– REV. E
 REF19x Series
OUTLINE DIMENSIONS
8-Lead Plastic DIP (P Suffix)
(N-8)
Dimensions shown in inches and (millimeters)

0.430 (10.92)
0.348 (8.84)

8 5
0.280 (7.11)
0.240 (6.10)
1 4
0.325 (8.25)
0.300 (7.62)
PIN 1 0.060 (1.52)
0.015 (0.38) 0.195 (4.95)
0.210 (5.33)
MAX 0.115 (2.93)
0.130
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381)
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204)
PLANE
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

8-Lead Narrow Body SOIC (S Suffix)

(SOIC-8)
Dimensions shown in inches and (millimeters)

0.1968 (5.00)
0.1890 (4.80)

8 5
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 4 0.2284 (5.80)

PIN 1 0.0688 (1.75) 0.0196 (0.50)

x 45
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.0040 (0.10)

8
0.0500 0.0192 (0.49) 0
SEATING (1.27) 0.0098 (0.25) 0.0500 (1.27)
PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 0.0160 (0.41)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

8-Lead TSSOP (RU Suffix)

(RU-8)
Dimensions shown in inches and (millimeters)

0.122 (3.10)
0.114 (2.90)

8 5
0.177 (4.50)
0.169 (4.30)

0.256 (6.50)
0.246 (6.25)

1 4

PIN 1
0.0256 (0.65)
0.006 (0.15) BSC
0.002 (0.05) 0.0433
(1.10)
MAX 8 0.028 (0.70)
0.0118 (0.30) 0 0.020 (0.50)
SEATING 0.0079 (0.20)
PLANE 0.0075 (0.19)
0.0035 (0.090)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV. E –23–
REF19x Series
Revision History
Location Page
1/03—Data Sheet changed from REV. D to REV. E.
Changes to TPCs 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Output Short Circuit Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

C00371–0–1/03(E)
Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PRINTED IN U.S.A.

–24– REV. E