a Precision Micropower, Low Dropout,

Voltage References
REF19x Series
FEATURES PIN CONFIGURATIONS
Initial Accuracy: ⴞ2 mV max
Temperature Coefficient: 5 ppm/°C max 8-Lead Narrow-Body SO and TSSOP
Low Supply Current: 45 ␮A max (S Suffix and RU Suffix)
Sleep Mode: 15 ␮A max
Low Dropout Voltage TP 1 8 NC

Load Regulation: 4 ppm/mA VS 2

REF19x 7 NC
SERIES
Line Regulation: 4 ppm/V SLEEP 3 TOP VIEW 6 OUTPUT
High Output Current: 30 mA (Not to Scale)
GND 4 5 TP
Short Circuit Protection
APPLICATIONS
Portable Instrumentation 8-Lead Epoxy DIP (P Suffix)
A-to-D and D-to-A Converters
Smart Sensors TP 1 8 NC
Solar Powered Applications REF19x
VS 2 SERIES 7 NC
Loop Current Powered Instrumentations
SLEEP 3 TOP VIEW 6 OUTPUT
(Not to Scale)
GENERAL DESCRIPTION GND 4 5 TP
REF19x series precision bandgap voltage references use a pat-
ented temperature drift curvature correction circuit and laser NC = NO CONNECT
TP PINS ARE FACTORY TEST POINTS
trimming of highly stable thin film resistors to achieve a very low NO USER CONNECTION
temperature coefficient and a high initial accuracy.
The REF19x series are micropower, Low Dropout Voltage
Table I
(LDV) devices providing a stable output voltage from supplies
as low as 100 mV above the output voltage and consuming less Part Number Nominal Output Voltage (V)
than 45 µA of supply current. In sleep mode, which is enabled
by applying a low TTL or CMOS level to the sleep pin, the REF191 2.048
output is turned off and supply current is further reduced to less REF192 2.50
than 15 µA. REF193 3.00
REF194 4.50
The REF19x series references are specified over the extended REF195 5.00
industrial temperature range (–40°C to +85°C) with typical REF196 3.30
performance specifications over –40°C to +125°C for applica- REF198 4.096
tions such as automotive.
All electrical grades are available in 8-Lead SOIC; the PDIP and
ORDERING GUIDE
TSSOP are only available in the lowest electrical grade. Prod-
ucts are also available in die form. Temperature Package Package
Test Pins (TP) Model Range Description Option1
The test pins, Pin 1 and Pin 5, are reserved for in-package
REF19xGP –40°C to +85°C 8-Lead Plastic DIP2 N-8
zener-zap. To achieve the highest level of accuracy at the out-
REF19xES 3 –40°C to +85°C 8-Lead SOIC SO-8
put, the zener-zapping technique is used to trim the output
REF19xFS3 –40°C to +85°C 8-Lead SOIC SO-8
voltage. Since each unit may require a different amount of ad-
REF19xGS –40°C to +85°C 8-Lead SOIC SO-8
justment, the resistance value at the test pins will vary widely
REF19xGRU –40°C to +85°C 8-Lead TSSOP RU-8
from pin-to-pin as well as from part-to-part. The user should
REF19xGBC +25°C DICE
not make any physical nor electrical connections to Pin 1 and
Pin 5. NOTES
1
N = Plastic DIP, SO = Small Outline, RU = Thin Shrink Small Outline.
2
8-Lead plastic DIP only available in “G” grade.
3
REF193 and REF196 are available in “G” grade only.

REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = +25ⴗC unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1
INITIAL ACCURACY
“E” Grade VO IOUT = 0 mA 2.046 2.048 2.050 V
“F” Grade 2.043 2.053 V
“G” Grade 2.038 2.058 V
LINE REGULATION2
“E” Grade ∆VO /∆VIN 3.0 V ≤ VS ≤ 15 V, I OUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V
LOAD REGULATION2
“E” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA 4 10 ppm/mA
“F & G” Grades 6 15 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 3.15 V, ILOAD = 2 mA 0.95 V
VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 30 mA 1.55 V
LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 20 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +85ⴗC unless otherwise noted)

S A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT 1, 2
“E” Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade 3 10 25 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 3.0 V ≤ VS ≤ 15 V, I OUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA 5 15 ppm/mA
“F & G” Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 3.15 V, ILOAD = 2 mA 0.95 V
VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 25 mA 1.55 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–2– REV. D
 REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V S = 3.3 V, –40ⴗC ≤ TA ≤ +125ⴗC unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade 3 10 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 3.0 V ≤ VS ≤ 15 V, I OUT = 0 mA 10 ppm/V
“F & G” Grades 20 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA 10 ppm/mA
“F & G” Grades 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 20 mA 1.55 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. D –3–
REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V S = 3.3 V, TA = +25ⴗC unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
1
INITIAL ACCURACY
“E” Grade VO IOUT = 0 mA 2.498 2.500 2.502 V
“F” Grade 2.495 2.505 V
“G” Grade 2.490 2.510 V
LINE REGULATION2
“E” Grade ∆VO /∆VIN 3.0 V ≤ VS ≤ 15 V, I OUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V
LOAD REGULATION2
“E” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA 4 10 ppm/mA
“F & G” Grades 6 15 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 3.5 V, ILOAD = 10 mA 1.00 V
VS = 3.9 V, ILOAD = 30 mA 1.40 V
LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 25 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V S = 3.3 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units
TEMPERATURE COEFFICIENT 1, 2
“E” Grade TCVO /°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade 3 10 25 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 3.0 V ≤ VS ≤ 15 V, I OUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA 5 15 ppm/mA
“F & G” Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 3.5 V, ILOAD = 10 mA 1.00 V
VS = 4.0 V, ILOAD = 25 mA 1.50 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–4– REV. D
 REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +125ⴗC unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO /°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade 3 10 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 3.0 V ≤ VS ≤ 15 V, I OUT = 0 mA 10 ppm/V
“F & G” Grades 20 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA 10 ppm/mA
“F & G” Grades 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 3.5 V, ILOAD = 10 mA 1.00 V
VS = 4.0 V, ILOAD = 20 mA 1.50 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 3.3 V, TA = +25ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

1
INITIAL ACCURACY
“G” Grade VO IOUT = 0 mA 2.990 3.0 3.010 V
2
LINE REGULATION
“G” Grades ∆VO/∆VIN 3.3 V, ≤ VS ≤ 15 V, IOUT = 0 mA 4 8 ppm/V
2
LOAD REGULATION
“G” Grade ∆VO/∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA 6 15 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.0 V, ILOAD = 30 mA 1.00 V
LONG-TERM STABILITY 3 ∆VO 1000 Hours @ +125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 30 µV p-p
NOTES
1Initial accuracy includes temperature hysteresis effect.
2Line and load regulation specifications include the effect of self-heating.
3Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

REV. D –5–
REF19x Series
REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V S = 3.3 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
1, 2
TEMPERATURE COEFFICIENT
“G” Grade 3 TCVO/°C IOUT = 0 mA 10 25 ppm/°C
4
LINE REGULATION
“G” Grade ∆VO /∆VIN 3.3 V ≤ VS ≤ 15 V, I OUT = 0 mA 10 20 ppm/V
4
LOAD REGULATION
“G” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA 10 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.1 V, ILOAD = 30 mA 1.10 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –40ⴗC ≤ T ≤ +125ⴗC unless otherwise noted)

S A

Parameter Symbol Condition Min Typ Max Units

1, 2
TEMPERATURE COEFFICIENT
“G” Grade 3 TCVO/°C IOUT = 0 mA 10 ppm/°C
LINE REGULATION4
“G” Grade ∆VO /∆VIN 3.3 V ≤ VS ≤ 15 V, I OUT = 0 mA 20 ppm/V
LOAD REGULATION4
“G” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA 10 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.1 V, ILOAD = 20 mA 1.10 V
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCV is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
O
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

–6– REV. D
 REF19x Series
REF194–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, T = +25ⴗC unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1
INITIAL ACCURACY
“E” Grade VO IOUT = 0 mA 4.498 4.5 4.502 V
“F” Grade 4.495 4.505 V
“G” Grade 4.490 4.510 V
LINE REGULATION2
“E” Grade ∆VO /∆VIN 4.75 V ≤ VS ≤ 15 V, I OUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V
LOAD REGULATION2
“E” Grade ∆VO /∆VLOAD VS = 5.8 V, 0 ≤ IOUT ≤ 30 mA 2 4 ppm/mA
“F & G” Grades 4 8 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 5.00 V, ILOAD = 10 mA 0.50 V
VS = 5.8 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 45 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V S = 5.0 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units
1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO /°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade 3 10 25 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 4.75 V ≤ VS ≤ 15 V, I OUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.80 V, 0 ≤ IOUT ≤ 25 mA 5 15 ppm/mA
“F & G” Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 5.00 V, ILOAD = 10 mA 0.5 V
VS = 5.80 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. D –7–
REF19x Series
REF194–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V S = 5.0 V, –40ⴗC ≤ T A ≤ +125ⴗC unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO /°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade 3 10 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
“F & G” Grades 10 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.80 V, 0 ≤ IOUT ≤ 20 mA 5 ppm/mA
“F & G” Grades 10 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 5.10 V, ILOAD = 10 mA 0.60 V
VS = 5.95 V, ILOAD = 20 mA 1.45 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–8– REV. D
 REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.10 V, T = +25ⴗC unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY1
“E” Grade VO IOUT = 0 mA 4.998 5.0 5.002 V
“F” Grade 4.995 5.005 V
“G” Grade 4.990 5.010 V
LINE REGULATION2
“E” Grade ∆VO /∆VIN 5.10 V ≤ VS ≤ 15 V, I OUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V
LOAD REGULATION2
“E” Grade ∆VO /∆VLOAD VS = 6.30 V, 0 ≤ IOUT ≤ 30 mA 2 4 ppm/mA
“F & G” Grades 4 8 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 5.50 V, ILOAD = 10 mA 0.50 V
VS = 6.30 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 50 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ VS = 5.15 V, TA = –40ⴗC ≤ T A ≤ +85ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO /°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade 3 10 25 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 5.15 V ≤ VS ≤ 15 V, I OUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 6.30 V, 0 ≤ IOUT ≤ 25 mA 5 10 ppm/mA
“F & G” Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 5.50 V, ILOAD = 10 mA 0.50 V
VS = 6.30 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
.

REV. D –9–
REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = +5.20 V, –40ⴗC ≤ T ≤ +125ⴗC unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO /°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade 3 10 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 5.20 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
“F & G” Grades 10 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 6.45 V, 0 ≤ I OUT ≤ 20 mA 5 ppm/mA
“F & G” Grades 10 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 5.60 V, I LOAD = 10 mA 0.60 V
VS = 6.45 V, I LOAD = 20 mA 1.45 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REF196–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = +3.5 V, T = +25ⴗC unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1
INITIAL ACCURACY
“G” Grade VO IOUT = 0 mA 3.290 3.3 3.310 V
2
LINE REGULATION
“G” Grades ∆VO /∆VIN 3.50 V ≤ VS ≤ 15 V, I OUT = 0 mA 4 8 ppm/V
2
LOAD REGULATION
“G” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA 6 15 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 4.1 V, ILOAD = 10 mA 0.80 V
VS = 4.3 V, ILOAD = 30 mA 1.00 V
LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 33 µV p-p
NOTES
1Initial accuracy includes temperature hysteresis effect.
2Line and load regulation specifications include the effect of self-heating.
3Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

–10– REV. D
 REF19x Series
REF196–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V S = +3.5 V, TA = –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
1, 2
TEMPERATURE COEFFICIENT
“G” Grade 3 TCVO/°C IOUT = 0 mA 10 25 ppm/°C
4
LINE REGULATION
“G” Grade ∆VO /∆VIN 3.5 V ≤ VS ≤ 15 V, I OUT = 0 mA 10 20 ppm/V
LOAD REGULATION4
“G” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA 10 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 4.1 V, ILOAD = 10 mA 0.80 V
VS = 4.3 V, ILOAD = 25 mA 1.00 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ VS = +3.50 V, –40ⴗC ≤ T A ≤ +125ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units
1, 2
TEMPERATURE COEFFICIENT
“G” Grade 3 TCVO /°C IOUT = 0 mA 10 ppm/°C
4
LINE REGULATION
“G” Grade ∆VO /∆VIN 3.50 V ≤ VS ≤ 15 V, I OUT = 0 mA 20 ppm/V
4
LOAD REGULATION
“G” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 4.1 V, ILOAD = 10 mA 0.80 V
VS = 4.4 V, ILOAD = 20 mA 1.10 V
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCV is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
O
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

REV. D –11–
REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V S = 5.0 V, TA = +25ⴗC unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
INITIAL ACCURACY1
“E” Grade VO IOUT = 0 mA 4.094 4.096 4.098 V
“F” Grade 4.091 4.101 V
“G” Grade 4.086 4.106 V
LINE REGULATION2
“E” Grade ∆VO /∆VIN 4.5 V ≤ VS ≤ 15 V, I OUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V
LOAD REGULATION2
“E” Grade ∆VO /∆VLOAD VS = 5.4 V, 0 ≤ IOUT ≤ 30 mA 2 4 ppm/mA
“F & G” Grades 4 8 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 4.6 V, ILOAD = 10 mA 0.50 V
VS = 5.4 V, ILOAD = 30 mA 1.30 V
LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 40 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = +5.0 V, –40ⴗC ≤ T ≤ +85ⴗC unless otherwise noted)

S A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT 1, 2
“E” Grade TCVO /°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade 3 10 25 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 4.5 V ≤ VS ≤ 15 V, I OUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.4 V, 0 ≤ IOUT ≤ 25 mA 5 10 ppm/mA
“F & G” Grades 10 20 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 4.6 V, ILOAD = 10 mA 0.50 V
VS = 5.4 V, ILOAD = 25 mA 1.30 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
.
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–12– REV. D
 REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = +5.0 V, –40ⴗC ≤ T A ≤ +125ⴗC unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO /°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade 3 10 ppm/°C
LINE REGULATION4
“E” Grade ∆VO /∆VIN 4.5 V ≤ VS ≤ 15 V, I OUT = 0 mA 5 ppm/V
“F & G” Grades 10 ppm/V
LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.6 V, 0 ≤ IOUT ≤ 20 mA 5 ppm/mA
“F & G” Grades 10 ppm/mA
DROPOUT VOLTAGE V S – VO VS = 4.7 V, ILOAD = 10 mA 0.60 V
VS = 5.6 V, ILOAD = 20 mA 1.50 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCV O = (V max–V min)/V O (TMAX –TMIN ).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. D –13–
REF19x Series
WAFER TEST LIMITS (@ I LOAD = 0 mA, TA = +25°C unless otherwise noted)
Parameter Symbol Condition Limits Units
INITIAL ACCURACY
REF191 VO 2.043/2.053 V
REF192 2.495/2.505 V
REF193 2.990/3.010 V
REF194 4.495/4.505 V
REF195 4.995/5.005 V
REF196 3.290/3.310 V
REF198 4.091/4.101 V
LINE REGULATION ∆VO /∆VIN (VO + 0.5 V) < VIN < 15 V, IOUT = 0 mA 15 ppm/V
LOAD REGULATION ∆VO /∆ILOAD 0 mA < ILOAD < 30 mA, VIN = (VO + 1.3 V) 15 ppm/mA
DROPOUT VOLTAGE VO – V+ ILOAD = 10 mA 1.25 V
ILOAD = 30 mA 1.55 V
SLEEP MODE INPUT
Logic Input High VIH 2.4 V
Logic Input Low VIL 0.8 V
SUPPLY CURRENT VIN = 15 V No Load 45 µA
Sleep Mode No Load 15 µA
NOTE
For proper operation, a 1 µF capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer probe to the limits shown. Due
to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications
based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS 1 DICE CHARACTERISTICS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V
Output to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VS + 0.3 V
OUTPUT OUTPUT
Output to GND Short-Circuit Duration . . . . . . . . . . Indefinite 6 6
Storage Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
REF19x . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Package Type ␪JA2 ␪JC Units
8-Lead Plastic DIP (P) 103 43 °C/W
°C/W
2 3 4
8-Lead SOIC (S) 158 43 V+ SLEEP GND
8-Lead TSSOP 240 43 °C/W
REF19x Die Size 0.041 × 0.057 Inch, 2,337 Sq. Mils
NOTES Substrate Is Connected to V+, Number of Transistors:
1
Absolute maximum rating applies to both DICE and packaged parts, unless Bipolar 25, MOSFET4. Process: CBCMOS1
otherwise noted.
2
θ JA is specified for worst case conditions, i.e., θ JA is specified for device in socket for
P-DIP, and θJA is specified for device soldered in circuit board for SOIC package.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the REF19x features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–14– REV. D
 REF19x Series
5.004 50

3 TYPICAL PARTS 45 BASED ON 600 –408C TA +858C

5.003 5.15V < VIN < 15V UNITS, 4 RUNS
40

PERCENTAGE OF PARTS – %
OUTPUT VOLTAGE – Volts

5.002
35
5.001
30

5.000 25

20
4.999
15
4.998
10
4.997 5

4.996 0
–50 –25 0 25 50 75 100 –20 –15 –10 –5 0 5 10 15 20
TEMPERATURE – 8C TC–VOUT – ppm/8C

Figure 1. REF195 Output Voltage vs. Temperature Figure 4. TC – V OUT Distribution

32 40

28 35
+5.15V VS 15V NORMAL MODE
LINE REGULATION – ppm/V

24 30

SUPPLY CURRENT – mA
–408C
20 25

16 20
+258C

12 15
+858C
8 10

SLEEP MODE
4 5

0 0
0 5 10 15 20 25 30 –50 –25 0 25 50 75 100
ILOAD – mA TEMPERATURE – 8C

Figure 2. REF195 Line Regulation vs. ILOAD Figure 5. Quiescent Current vs. Temperature

20 –6

O IOUT < 25mA

+858C
–5
16
LOAD REGULATION – ppm/mA

SLEEP PIN CURRENT – mA

+258C –4
12
–408C
–3

8
–2
VL
4
–1 VH

0 0
4 6 8 10 12 14 16 –50 –25 0 25 50 75 100
VIN – Volts
TEMPERATURE – 8C

Figure 3. REF195 Load Regulation vs. VIN Figure 6. SLEEP Pin Current vs. Temperature

REV. D –15–
REF19x Series
2
VIN = 15V 6
4 REF19x
0 10mA
1mF
0
–20
RIPPLE REJECTION – dB

Figure 9b. Load Transient Response Measurement Circuit

–40

–60

2V
–80 100

90

–100

–120

1mA
10 100 1k 10k 100k 1M LOAD
30mA
FREQUENCY – Hz LOAD
10

Figure 7a. Ripple Rejection vs. Frequency 0%

2V 100ms

10mF
Figure 10a. Power ON Response Time
1kV 10mF
2 6
VIN = +15V REF19x OUTPUT
1mF 1kV 2 6
10mF 4
4 REF19x
REF VIN = 7.0V 1mF

Figure 7b. Ripple Rejection vs. Frequency

Measurement Circuit Figure 10b. Power ON Response Time Measurement
Circuit

VIN = 7V 2 200V
6 5V
REF19x VG = 2V p-p ON 100

4 1mF 90
1mF OFF
Z VS = 4.00V

VOUT IL = 1mA
4 IL = 10mA

3 10

0%
IO – V

2 1V 2ms

0
Figure 11a. Sleep Response Time
10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz
VIN = 15V
Figure 8. Output Impedance vs. Frequency 2
REF19x 6 VOUT
3

4 1mF
5V
OFF 100

90
ON
Figure 11b. Sleep Response Time Measurement Circuit

10

0%
20mV 100ms

Figure 9a. Load Transient Response

–16– REV. D
 REF19x Series
35

5V
100 30
90

25

LOAD CURRENT – mA
20

15
10

0% 10
200mV 200ms

5
Figure 12. Line Transient Response
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
REF195 DROPOUT VOLTAGE – V

Figure 13. Dropout Voltage vs. Load Current

+V Output Voltage Bypassing

For stable operation, low dropout voltage regulators and refer-
ences, in general, require a bypass capacitor connected from
their VOUT pins to their GND pins. Although the REF19x
VOUT family of references is capable of stable operation with capacitive
loads exceeding 100 µF, a 1 µF capacitor is sufficient to guaran-
tee rated performance. The addition of a 0.1 µF ceramic ca-
SHUTDOWN
pacitor in parallel with the bypass capacitor will improve load
current transient performance. For best line voltage transient
performance, it is recommended that the voltage inputs of these
devices be bypassed with a 10 µF electrolytic capacitor in paral-
lel with a 0.1 µF ceramic capacitor.
GND Sleep Mode Operation
All REF19x devices include a sleep capability that is TTL/CMOS
Figure 14. Simplified Schematic
level compatible. Internal to the REF19x at the SLEEP pin, a
pull-up current source to VIN is connected. This permits the
APPLICATIONS SECTION
SLEEP pin to be driven from an open collector/drain driver.
Output Short Circuit Behavior
A logic LOW or a zero volt condition on the SLEEP pin is re-
The REF19x family of devices is totally protected from damage
quired to turn the output stage OFF. During sleep, the output
due to accidental output shorts to GND or to V+. In the event
of the references becomes a high impedance state where its
of an accidental short circuit condition, the reference device will
potential would then be determined by external circuitry. If the
shutdown and limit its supply current to 100 µA.
sleep feature is not used, it is recommended that the SLEEP pin
Device Power Dissipation Considerations be connected to VIN (Pin 2).
The REF19x family of references is capable of delivering load
Basic Voltage Reference Connections
currents to 30 mA with an input voltage that ranges from 3.3 V
The circuit in Figure 15 illustrates the basic configuration for
to 15 V. When these devices are used in applications with large
the REF19x family of references. Note the 10 µF/0.1 µF bypass
input voltages, care should be exercised to avoid exceeding these
network on the input and the 1 µF/0.1 µF bypass network on the
devices’ maximum internal power dissipation. Exceeding the
output. It is recommended that no connections be made to
published specifications for maximum power dissipation or
Pins 1, 5, 7 and 8. If the sleep feature is not required, Pin 3
junction temperature could result in premature device failure.
should be connected to VIN.
The following formula should be used to calculate a device’s
maximum junction temperature or dissipation:
NC 1 8 NC
VIN
T – TA
= J
2 7 NC
PD REF19x
θ JA 10mF 0.1mF OUTPUT
SLEEP 3 6
1mF 0.1mF
In this equation, TJ and TA are the junction and ambient tem- 4 5 NC TANT
peratures, respectively, PD is the device power dissipation and
θJA is the device package thermal resistance. Figure 15. Basic Voltage Reference Configuration

REV. D –17–
REF19x Series
Membrane Switch Controlled Power Supply In this circuit, the power supply current of reference U1 flowing
With output load currents in the tens of mA, the REF19x family through R1–R2 develops a base drive for Q1, whose collector
of references can operate as a low dropout power supply in provides the bulk of the output current. With a typical gain of
hand-held instrument applications. In the circuit shown in 100 in Q1 for 100 mA–200 mA loads, U1 is never required to
Figure 16, a membrane ON/OFF switch is used to control the furnish more than a few mA, so this factor minimizes tempera-
operation of the reference. During an initial power-on condi- ture related drift. Short circuit protection is provided by Q2,
tion, the SLEEP pin is held to GND by the 10 kΩ resistor. which clamps drive to Q1 at about 300 mA of load current with
Recall that this condition disables (read: three-state) the values as shown. With this separation of control and power
REF19x output. When the membrane ON switch is pressed, functions, dc stability is optimum, allowing best advantage use
the SLEEP pin is momentarily pulled to VIN, enabling the of premium grade REF19x devices for U1. Of course, load
REF19x output. At this point, current through the 10 kΩ is management should still be exercised. A short, heavy, low DCR
reduced and the internal current source connected to the (DC Resistance) conductor should be used from U1–6 to the
SLEEP pin takes control. Pin 3 assumes and remains at the VOUT sense point “S,” where the collector of Q1 connects to the
same potential as VIN. When the membrane OFF switch is load, point “F.”
pressed, the SLEEP pin is momentarily connected to GND, Because of the current limiting configuration, the dropout volt-
which once again disables the REF19x output. age circuit is raised about 1.1 V over that of the REF19x de-
vices, due to the VBE of Q1 and the drop across current sense
NC 1 8 NC resistor R4. However, overall dropout is typically still low
VIN enough to allow operation of a 5 V to 3.3 V regulator/reference
2 7 NC
1kV
REF19x OUTPUT using the REF196 for U1 as noted, with a VS as low as 4.5 V
3 6
5% and a load current of 150 mA.
1mF
4 5 NC TANT
ON The requirement for a heat sink on Q1 depends on the maxi-
mum input voltage and short circuit current. With VS = 5 V
10kV
and a 300 mA current limit, the worst case dissipation of Q1 is
OFF
1.5 W, less than the TO-220 package 2 W limit. However, if
smaller TO-39 or TO-5 packaged devices such as the 2N4033
Figure 16. Membrane Switch Controlled Power Supply are used, the current limit should be reduced to keep maximum
dissipation below the package rating. This is accomplished by
Current-Boosted References with Current Limiting simply raising R 4.
While the 30 mA rated output current of the REF19x series is
A tantalum output capacitor is used at C1 for its low ESR
higher than typical of other reference ICs, it can be boosted to
(Equivalent Series Resistance), and the higher value is required
higher levels if desired, with the addition of a simple external
for stability. Capacitor C2 provides input bypassing and can be
PNP transistor, as shown in Figure 17. Full time current limit-
an ordinary electrolytic.
ing is used for protection of the pass transistor against shorts.
Shutdown control of the booster stage is shown as an option,
Q1 and when used some cautions are in order. Because of the
R4 TIP32A
2V (SEE TEXT) OUTPUT TABLE
additional active devices in the VS line to U1, direct drive to
+VS = 6 TO 9V
(SEE TEXT)
R1 VOUT (V)
Pin 3 does not work as with an unbuffered REF19x device. To
U1
Q2
1kV enable shutdown control, the connection to U1-2 is broken at
REF192 2.5
2N3906
R2 REF193 3.0
the “X,” and diode D1 then allows a CMOS control source VC
C2
1.5kV REF196 3.3 to drive U1-3 for ON-OFF operation. Startup from shutdown is
REF194 4.5
100mF/25V C3 F REF195 5.0 not as clean under heavy load as it is in basic REF19x series and
0.1mF
D1 U1 S +VOUT
can require several milliseconds under load. Nevertheless, it is
VC REF196
(SEE TABLE)
3.3V still effective and can fully control 150 mA loads. When shutdown
1N4148 C1 @ 150mA
(SEE TEXT 10mF/25V control is used, heavy capacitive loads should be minimized.
ON SLEEP) (TANTALUM)
R3 R1
1.82kV S
VS VOUT
COMMON F COMMON

Figure 17. A Boosted 3.3 V Reference with Current

Limiting

–18– REV. D
 REF19x Series
A Negative Precision Reference without Precision Resistors Stacking Reference ICs for Arbitrary Outputs
In many current-output CMOS DAC applications, where the Some applications may require two reference voltage sources
output signal voltage must be of the same polarity as the that are a combined sum of standard outputs. The circuit of
reference voltage, it is often required to reconfigure a cur- Figure 19 shows how this “stacked output” reference can be
rent-switching DAC into a voltage-switching DAC through the implemented.
use of a 1.25 V reference, an op amp and a pair of resistors. OUTPUT TABLE
Using a current-switching DAC directly requires an additional U1/U2 VOUT1 (V) VOUT2 (V)
operational amplifier at the output to reinvert the signal. A REF192/REF192 2.5 5.0
REF192/REF194 2.5 7.0
negative voltage reference is then desirable from the point that REF192/REF195 2.5 7.5
+VS
an additional operational amplifier is not required for either VS > VOUT2 +0.15V
C1
reinversion (current-switching mode) or amplification (voltage 0.1mF U2
switching mode) of the DAC output voltage. In general, any REF19x +VOUT2
(SEE TABLE) C2
positive voltage reference can be converted into a negative volt- VO (U2)
1mF
age reference through the use of an operational amplifier and a
pair of matched resistors in an inverting configuration. The
disadvantage to that approach is that the largest single source of C3
error in the circuit is the relative matching of the resistors used. 0.1mF U1
REF19x +VOUT1
(SEE TABLE) C4 R1
The circuit illustrated in Figure 18 avoids the need for tightly VO (U1) 1mF 3.9kV
(SEE TEXT)
matched resistors with the use of an active integrator circuit. In
this circuit, the output of the voltage reference provides the VIN VOUT
COMMON COMMON
input drive for the integrator. The integrator, to maintain cir-
cuit equilibrium, adjusts its output to establish the proper rela-
Figure 19. Stacking Voltage References with the REF19x
tionship between the reference’s VOUT and GND. Thus, any
desired negative output voltage can be chosen by simply sub-
Two reference ICs are used, fed from a common unregulated
stituting for the appropriate reference IC. The sleep feature is
input, VS . The outputs of the individual ICs are simply con-
maintained in the circuit with the simple addition of a PNP
nected in series as shown, which provides two output voltages,
transistor and a 10 kΩ resistor. One caveat with this approach
VOUT1 and VOUT2 . VOUT1 is the terminal voltage of U1, while
should be mentioned: although rail-to-rail output amplifiers
VOUT2 is the sum of this voltage and the terminal voltage of U2.
work best in the application, these operational amplifiers require
U1 and U2 are simply chosen for the two voltages that supply
a finite amount (mV) of headroom when required to provide
the required outputs (see table). If, for example, both U1 and
any load current. The choice for the circuit’s negative supply
U2 are REF192s, the two outputs are 2.5 V and 5.0 V.
should take this issue into account.
While this concept is simple, some cautions are in order. Since
VIN the lower reference circuit must sink a small bias current from
U2 (50 µA–100 µA), plus the base current from the series PNP
SLEEP
10kV output transistor in U2, either the external load of U1 or R1
2N3906
TTL/CMOS must provide a path for this current. If the U1 minimum load is
VIN
1kV 1mF not well defined, resistor R1 should be used, set to a value that
SLEEP VREF will conservatively pass 600 µA of current with the applicable
+5V VOUT1 across it. Note that the two U1 and U2 reference circuits
REF19x
GND 100V are locally treated as macrocells, each having its own bypasses at
1mF A1 –VREF
input and output for best stability. Both U1 and U2 in this
10kV 100kV circuit can source dc currents up to their full rating. The mini-
–5V
mum input voltage, VS, is determined by the sum of the out-
A1 = 1/2 OP295,
1/2 OP291 puts, VOUT2 , plus the dropout voltage of U2.
A related variation on stacking two three-terminal references is
Figure 18. A Negative Precision Voltage Reference
shown in Figure 19, where U1, a REF192, is stacked with a
Uses No Precision Resistors
two-terminal reference diode such as the AD589. Like the
three-terminal stacked reference above, this circuit provides two
outputs, VOUT1 and VOUT2, which are the individual terminal
voltages of D1 and U1 respectively. Here this is 1.235 and 2.5,
which provides a VOUT2 of 3.735 V. When using two-terminal
reference diodes such as D1, the rated minimum and maximum
device currents must be observed and the maximum load cur-
rent from VOUT1 can be no greater than the current set up by R1
and VO(U1). In the case with VO(U1) equal to 2.5 V, R1 provides
a 500 µA bias to D1, so the maximum load current available at
VOUT1 is 450 µA or less.

REV. D –19–
REF19x Series
Switched Output 5 V/3.3 V Reference
+VS Applications often require digital control of reference voltages,
VS > VOUT2 +0.15V
selecting between one stable voltage and a second. With the
U1 +VOUT2 sleep feature inherent to the REF19x series, switched output
C1 REF192 R1 3.735V
0.1mF VO (U1)
C2
1mF 4.99kV
reference configurations are easily implemented with relatively
(SEE TEXT) little additional hardware.
+VOUT1 The circuit of Figure 22 illustrates the general technique, which
C3
1.235V takes advantage of the output “wire-OR” capability of the
D1 VO (D1)
AD589 1mF REF19x device family. When OFF, a REF19x device is effec-
tively an open circuit at the output node with respect to the
VIN VOUT
COMMON COMMON
power supply. When ON, a REF19x device can source current
up to its current rating, but sink only a few µA (essentially just
Figure 20. Stacking Voltage References with the REF19x the relatively low current of the internal output scaling divider).
As a result, for two devices wired together at their common
outputs, the output voltage is simply that of the ON device.
A Precision Current Source The OFF state device will draw a small standby current of
Many times, in low power applications, the need arises for a 15 µA (max), but otherwise will not interfere with operation of
precision current source that can operate on low supply volt- the ON device, which can operate to its full current rating.
ages. As shown in Figure 21, any one of the devices in the Note that the two devices in the circuit conveniently share
REF19x family of references can be configured as a precision both input and output capacitors, and with CMOS logic
current source. The circuit configuration illustrated is a floating drive, it is power efficient.
current source with a grounded load. The reference’s output
voltage is bootstrapped across RSET, which sets the output cur- Using dissimilar REF19x series devices with this configuration
rent into the load. With this configuration, circuit precision is allows logic selection between the U1/U2 specified terminal
maintained for load currents in the range from the reference’s voltages. For example, with U1 (a REF195) and U2 (a REF196),
supply current (typically, 30 µA) to approximately 30 mA. The as noted in the table, changing the CMOS compatible VC logic
low dropout voltage of these devices maximizes the current control voltage from HI to LO selects between a nominal output
source’s output voltage compliance without excess headroom. of 5.000 V and 3.300 V and vice versa. Other REF19x family
units can also be used for U1/U2, with similar operation in a
VIN logic sense, but with outputs as per the individual paired devices
(see table, again). Of course, the exact output voltage tolerance,
drift and overall quality of the reference voltage will be consis-
VIN tent with the grade of individual U1 and U2 devices.
REF19x
SLEEP VREF OUTPUT TABLE
GND R1 U1/U2 VC* VOUT (V)
1mF RSET
ISY REF195/ HI 5.0
ADJUST P1
REF196 LO 3.3
+VS = 6V REF194/ HI 4.5
IOUT REF195 LO 5.0
VIN IOUT • RL (MAX) + VSY (MIN) * CMOS LOGIC LEVELS
V RL 1 2 3 4 U1
IOUT = OUT + ISY (REF19x) VC REF19x
RSET
(SEE TABLE)
VOUT E.G. REF195 : VOUT = 5V U3A U3B
>> ISY
RSET IOUT = 5mA 74HC04 74HC04
R1 = 953V
P1 = 100V, 10-TURN +VOUT

Figure 21. A Low Dropout, Precision Current Source

U2
REF19x C2
(SEE TABLE) 1mF
The circuit’s governing equations are: C1
0.1mF
VIN
V IN = IOUT × RL (max)+V SY (min, REF19x)
VOUT
COMMON COMMON
V OUT
IOUT = + I SY (REF19x)
RSET Figure 22. Switched Output Reference
V OUT
〉〉I (REF19x)
RSET SY

–20– REV. D
 REF19x Series
There is one application caveat that should be understood about resistance within the forcing loop of the op amp. Since the op
this circuit, which comes about due to the wire-OR nature. amp senses the load voltage, op amp loop control forces the
Since U1 and U2 can only source current effectively, negative output to compensate for the wiring error and to produce the
going output voltage changes, which require the sinking of cur- correct voltage at the load. Depending on the reference device
rent, will necessarily take longer than positive going changes. In chosen, operational amplifiers that can be used in this applica-
practice, this means that the circuit is quite fast when undergo- tion are the OP295, the OP291 and the OP183/OP283.
ing a transition from 3.3 to 5 V, but the transition from 5 to
3.3 V will take longer. Exactly how much longer will be a func- VIN VIN
RLW
tion of the load resistance, R L, seen at the output and the +VOUT
typical 1 µF value of C2. In general, a conservative transition VIN
SENSE
2 RLW
time here will be on the order of several milliseconds for load REF19x A1
1 +VOUT
resistances in the range of 100␣ Ω–1 kΩ. Note that for highest
3 FORCE
SLEEP VOUT
GND RL
accuracy at the new output voltage, several time constants 1mF 100kV
should be allowed (>7.6 time constants for <1/2 LSB error @ A1 = 1/2 OP295
1/2 OP292
10 bits, for example). 1/2 OP283

Kelvin Connections Figure 23. A Low Dropout, Kelvin Connected Voltage

In many portable instrumentation applications where PC board Reference
cost and area go hand-in-hand, circuit interconnects are very
often of dimensionally minimum width. These narrow lines can A Fail-Safe 5 V Reference
cause large voltage drops if the voltage reference is required to Some critical applications require a reference voltage to be
provide load currents to various functions. In fact, a circuit’s maintained constant, even with a loss of primary power. The
interconnects can exhibit a typical line resistance of 0.45 mΩ/ low standby power of the REF19x series and the switched out-
square (1 oz. Cu, for example). In those applications where put capability allow a “fail-safe” reference configuration to be
these devices are configured as low dropout voltage regulators, implemented rather easily. This reference maintains a tight
these wiring voltage drops can become a large source of error. output voltage tolerance for either a primary power source (ac
To circumvent this problem, force and sense connections can be line derived) or a standby (battery derived) power source, auto-
made to the reference through the use of an operational ampli- matically switching between the two as the power conditions
fier, as shown in Figure 23. This method provides a means by change.
which the effects of wiring resistance voltage drops can be elimi-
nated. Load currents flowing through wiring resistance produce The circuit in Figure 24 illustrates the concept, which borrows
an I-R error (ILOAD × RWIRE) at the load. However, the Kelvin from the switched output idea of Figure 21, again using the
connection overcomes the problem by including the wiring REF19x device family output “wire-OR” capability. In this
case, since a constant 5 V reference voltage is desired for all

+VBAT
C2
0.1mF
+VS
U1
R1 REF195
1.1MV R3 R6 +5.000V
10MV 100V Q1
C1
2N3904
3 0.1mF
7
6
2
U3 C3
4 AD820 1mF
R2 U2
100kV REF195
R4
900kV
C4 R5
0.1mF 100kV
VS, VBAT VOUT
COMMON COMMON

Figure 24. A Fail-Safe 5 V Reference

REV. D –21–
REF19x Series
conditions, two REF195 devices are used for U1 and U2, with A Low Power, Strain Gage Circuit
their ON/OFF switching controlled by the presence or absence As shown in Figure 25, the REF19x family of references can
of the primary dc supply source, VS. VBAT is a 6 V battery be used in conjunction with low supply voltage operational
backup source that supplies power to the load only when VS amplifiers, such as the OP492 and the OP283, in a self-con-
fails. For normal (VS present) power conditions, VBAT sees only tained strain gage circuit. In this circuit, the REF195 was used
the 15 µA (max) standby current drain of U1 in its OFF state. as the core of this low power, strain gage circuit. Other refer-
In operation, it is assumed that for all conditions either U1 or ences can be easily accommodated by changing circuit element
U2 is ON and a 5 V reference output is available. With this values. The references play a dual role as the voltage regulator
voltage constant, a scaled down version is applied to the com- to provide the supply voltage requirements of the strain gage
parator IC U3, providing a fixed 0.5 V input to the (–) input for and the operational amplifiers as well as a precision voltage
all power conditions. The R1–R2 divider provides a signal to reference for the current source used to stimulate the bridge. A
the U3 (+) input proportional to VS, which switches U3 and distinct feature of the circuit is that it can be remotely controlled
U1/U2 dependent upon the absolute level of VS. Op amp U3 is ON or OFF by digital means via the SLEEP pin.
configured here as a comparator with hysteresis, which provides 100V
for clean, noise free output switching. This hysteresis is impor-
10mF
tant to eliminate rapid switching at the threshold due to VS REF195
ripple. Further, the device chosen is the AD820, a rail-rail
1mF
output device, which provides HI and LO output states within a 10mF

few mV of VS and ground for accurate thresholds and compat-

ible drive for U2 for all VS conditions. R3 provides positive 57kV
1% 0.1mF
feedback for circuit hysteresis, changing the threshold at the (+)
input as a function of U3’s output.
For VS levels lower than the LOWER threshold, U3’s output is 10kV 1/4
2N2222
0.1mF 1% OP492
low, thus U2 and Q1 are OFF, while U1 is ON. For VS levels
higher than the UPPER threshold, the situation reverses, with
U1 OFF and both U2 and Q1 ON. In the interest of battery
power conservation, all of the comparison switching circuitry is 500V
0.1%
powered from VS and is so arranged that when VS fails the de-
fault output comes from U1.
For the R1–R3 values as shown, the LOWER/UPPER VS 10kV 0.01mF
1%
switching thresholds are approximately 5.5 V and 6 V, respec- 20kV
tively. These can obviously be changed to suit other VS sup- 1%

plies, as can the REF19x devices used for U1 and U2, over a 20kV
1/4 1%
range of 2.5 V to 5 V of output. U3 can operate down to a VS OP492
1/4
of 3.3 V, which is generally compatible with all family devices. OP492 OUTPUT
2.21kV 10kV
1%

20kV
1/4 1%
OP492
20kV
1%

Figure 25. A Low Power, Strain Gage Circuit

–22– REV. D
 REF19x Series
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Plastic DIP (P Suffix)

(N-8)

C1951d–2–3/99
0.430 (10.92)
0.348 (8.84)

8 5
0.280 (7.11)
0.240 (6.10)
1 4 0.325 (8.25)
0.300 (7.62)
PIN 1 0.060 (1.52)
0.015 (0.38) 0.195 (4.95)
0.210 (5.33)
MAX 0.115 (2.93)
0.130
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381)
0.022 (0.558) 0.100 0.070 (1.77) SEATING
PLANE 0.008 (0.204)
0.014 (0.356) (2.54) 0.045 (1.15)
BSC

8-Lead Narrow Body SO (S Suffix)

(SO-8)
0.1968 (5.00)
0.1890 (4.80)

8 5
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 4 0.2284 (5.80)

PIN 1 0.0688 (1.75) 0.0196 (0.50)

x 45°
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.0040 (0.10)

8°
0.0500 0.0192 (0.49) 0°
SEATING (1.27) 0.0138 (0.35) 0.0098 (0.25) 0.0500 (1.27)
PLANE BSC 0.0075 (0.19) 0.0160 (0.41)

8-Lead TSSOP (RU Suffix)

(RU-8)

0.122 (3.10)
0.114 (2.90)

8 5
0.177 (4.50)
0.169 (4.30)

0.256 (6.50)
0.246 (6.25)

PRINTED IN U.S.A.
1
4

PIN 1
0.0256 (0.65)
0.006 (0.15) BSC
0.002 (0.05) 0.0433
(1.10)
MAX 0.028 (0.70)
8°
0.0118 (0.30) 0° 0.020 (0.50)
SEATING 0.0079 (0.20)
PLANE 0.0075 (0.19)
0.0035 (0.090)

REV. D –23–