a Precision Micropower, Low Dropout,

Voltage References
REF19x Series*
PIN CONFIGURATIONS

8-Lead Narrow-Body SO and TSSOP

(S Suffix and RU Suffix)

8-Lead Epoxy DIP (P Suffix)

Table I

Part Number Nominal Output Voltage (V)

REF191 2.048
REF192 2.50
REF193 3.00
REF194 4.50
REF195 5.00
REF196 3.30
REF198 4.096

ORDERING GUIDE

Temperature Package Package

Model Range Description Option
REF19xGP –40°C to +85°C 8-Pin Plastic DIP* N-8
REF19xES† –40°C to +85°C 8-Pin SOIC SO-8
REF19xFS† –40°C to +85°C 8-Pin SOIC SO-8
REF19xGS –40°C to +85°C 8-Pin SOIC SO-8
REF19xGRU –40°C to +85°C 8-Pin TSSOP TSSOP-8
REF19xGBC +25°C DICE
*8-pin plastic DIP only available in “G” grade.
†REF193 and REF196 are available in “G” grade only.

REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = +258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1
INITIAL ACCURACY
“E” Grade VO IOUT = 0 mA 2.046 2.048 2.050 V
“F” Grade 2.043 2.053 V
“G” Grade 2.038 2.058 V
LINE REGULATION2
“E” Grade ∆VO/∆VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V
LOAD REGULATION2
“E” Grade ∆VO/∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA 4 10 ppm/mA
“F & G” Grades 6 15 ppm/mA
DROPOUT VOLTAGE VS – V O VS = 3.0 V, ILOAD = 2 mA 0.95 V
VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 25 mA 1.55 V
LONG-TERM STABILITY 3 ∆VO 1000 Hours @ +125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 20 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –408C ≤ T ≤ +858C unless otherwise noted)

S A

Parameter Symbol Condition Min Typ Max Units

1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO/°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade3 10 25 ppm/°C
LINE REGULATION4
“E” Grade ∆VO/∆VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V
LOAD REGULATION4
“E” Grade ∆VO/∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA 5 15 ppm/mA
“F & G” Grades 10 20 ppm/mA
DROPOUT VOLTAGE VS – V O VS = 3.0 V, ILOAD = 2 mA 0.95 V
VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 25 mA 1.55 V
SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA
SUPPLY CURRENT No Load 45 µA
Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–2– REV. C
 REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –408C ≤ T ≤ +1258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO/°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade3 10 ppm/°C
LINE REGULATION4
“E” Grade ∆VO/∆VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 ppm/V
“F & G” Grades 20 ppm/V
LOAD REGULATION4
“E” Grade ∆VO/∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA 10 ppm/mA
“F & G” Grades 20 ppm/mA
DROPOUT VOLTAGE VS – V O VS = 3.3 V, ILOAD = 10 mA 1.25 V
VS = 3.6 V, ILOAD = 20 mA 1.55 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. C –3–
REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = +258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1
INITIAL ACCURACY
“E” Grade VO IOUT = 0 mA 2.498 2.500 2.502 V
“F” Grade 2.495 2.505 V
“G” Grade 2.490 2.510 V

LINE REGULATION2
“E” Grade ∆VO/∆VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V

LOAD REGULATION2
“E” Grade ∆VO/∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA 4 10 ppm/mA
“F & G” Grades 6 15 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 3.5 V, ILOAD = 10 mA 1.00 V

VS = 3.9 V, ILOAD = 30 mA 1.40 V

LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 1.2 mV

NOISE VOLTAGE eN 0.1 Hz to 10 Hz 25 µV p-p

NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = –408C ≤ T ≤ +858C unless otherwise noted)

S A A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT 1, 2
“E” Grade TCVO /°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade3 10 25 ppm/°C

LINE REGULATION4
“E” Grade ∆VO /∆VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V

LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA 5 15 ppm/mA
“F & G” Grades 10 20 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 3.5 V, ILOAD = 10 mA 1.00 V

VS = 4.0 V, ILOAD = 25 mA 1.50 V

SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–4– REV. C
 REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –408C ≤ T ≤ +1258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO /°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade3 10 ppm/°C

LINE REGULATION4
“E” Grade ∆VO /∆VIN 3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 ppm/V
“F & G” Grades 20 ppm/V

LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA 10 ppm/mA
“F & G” Grades 20 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 3.5 V, ILOAD = 10 mA 1.00 V

VS = 4.0 V, ILOAD = 20 mA 1.50 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 3.3 V, TA = +258C unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

1
INITIAL ACCURACY
“G” Grade VO IOUT = 0 mA 2.990 3.0 3.010 V
LINE REGULATION2
“G” Grades ∆VO/∆VIN 3.3 V, ≤ VS ≤ 15 V, IOUT = 0 mA 4 8 ppm/V
LOAD REGULATION2
“G” Grade ∆VO/∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA 6 15 ppm/mA
DROPOUT VOLTAGE VS – VO VS = 3.8 V, ILOAD = 10 mA 0.80 V
VS = 4.0 V, ILOAD = 30 mA 1.00 V
LONG-TERM STABILITY 3 ∆V O 1000 Hours @ +125°C 1.2 mV
NOISE VOLTAGE eN 0.1 Hz to 10 Hz 30 µV p-p
NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

REV. C –5–
REF19x Series
REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, T = –408C ≤ T ≤ +858C unless otherwise noted)
S A A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT 1, 2
“G” Grade3 TCVO/°C IOUT = 0 mA 10 25 ppm/°C

LINE REGULATION4
“G” Grade ∆VO/∆VIN 3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 20 ppm/V
4
LOAD REGULATION
“G” Grade ∆VO/∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA 10 20 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 3.8 V, ILOAD = 10 mA 0.80 V

VS = 4.1 V, ILOAD = 30 mA 1.10 V

SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 3.3 V, –408C ≤ T ≤ +1258C unless otherwise noted)

S A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT 1, 2
“G” Grade3 TCVO/°C IOUT = 0 mA 10 ppm/°C
4
LINE REGULATION
“G” Grade ∆VO /∆VIN 3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA 20 ppm/V
4
LOAD REGULATION
“G” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA 10 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 3.8 V, ILOAD = 10 mA 0.80 V

VS = 4.1 V, ILOAD = 20 mA 1.10 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–6– REV. C
 REF19x Series
REF194–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, T = +258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY 1
“E” Grade VO IOUT = 0 mA 4.498 4.5 4.502 V
“F” Grade 4.495 4.505 V
“G” Grade 4.490 4.510 V

LINE REGULATION2
“E” Grade ∆VO /∆VIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V

LOAD REGULATION2
“E” Grade ∆VO /∆VLOAD VS = 5.8 V, 0 ≤ IOUT ≤ 30 mA 2 4 ppm/mA
“F & G” Grades 4 8 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 5.00 V, ILOAD = 10 mA 0.50 V

VS = 5.8 V, ILOAD = 30 mA 1.30 V

LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 2 mV

NOISE VOLTAGE eN 0.1 Hz to 10 Hz 45 µV p-p

NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, T = –408C ≤ T ≤ +858C unless otherwise noted)

S A A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT 1, 2
“E” Grade TCVO /°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade3 10 25 ppm/°C

LINE REGULATION4
“E” Grade ∆VO /∆VIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V

LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.80 V, 0 ≤ IOUT ≤ 25 mA 5 15 ppm/mA
“F & G” Grades 10 20 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 5.00 V, ILOAD = 10 mA 0.5 V

VS = 5.80 V, ILOAD = 25 mA 1.30 V

SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. C –7–
REF19x Series
REF194–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, –408C ≤ T ≤ +1258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO /°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade3 10 ppm/°C

LINE REGULATION4
“E” Grade ∆VO /∆VIN 4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
“F & G” Grades 10 ppm/V

LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.80 V, 0 ≤ IOUT ≤ 20 mA 5 ppm/mA
“F & G” Grades 10 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 5.10 V, ILOAD = 10 mA 0.60 V

VS = 5.95 V, ILOAD = 20 mA 1.45 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–8– REV. C
 REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.10 V, T = +258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY 1
“E” Grade VO IOUT = 0 mA 4.998 5.0 5.002 V
“F” Grade 4.995 5.005 V
“G” Grade 4.990 5.010 V

LINE REGULATION2
“E” Grade ∆VO/∆VIN 5.10 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V

LOAD REGULATION2
“E” Grade ∆VO /∆VLOAD VS = 6.30 V, 0 ≤ IOUT ≤ 30 mA 2 4 ppm/mA
“F & G” Grades 4 8 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 5.50 V, ILOAD = 10 mA 0.50 V

VS = 6.30 V, ILOAD = 30 mA 1.30 V

LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 1.2 mV

NOISE VOLTAGE eN 0.1 Hz to 10 Hz 50 µV p-p

NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ V = 5.15 V, T = –408C ≤ T ≤ +858C unless otherwise noted)

S A A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT 1, 2
“E” Grade TCVO /°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade3 10 25 ppm/°C

LINE REGULATION4
“E” Grade ∆VO /∆VIN 5.15 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V

LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 6.30 V, 0 ≤ IOUT ≤ 25 mA 5 10 ppm/mA
“F & G” Grades 10 20 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 5.50 V, ILOAD = 10 mA 0.50 V

VS = 6.30 V, ILOAD = 25 mA 1.30 V

SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.e.
.

REV. C –9–
REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V S = +5.20 V, –408C ≤ TA ≤ +1258C unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
1, 2
TEMPERATURE COEFFICIENT
“E” Grade TCVO /°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade3 10 ppm/°C

LINE REGULATION4
“E” Grade ∆VO /∆VIN 5.20 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
“F & G” Grades 10 ppm/V

LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 6.45 V, 0 ≤ IOUT ≤ 20 mA 5 ppm/mA
“F & G” Grades 10 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 5.60 V, ILOAD = 10 mA 0.60 V

VS = 6.45 V, ILOAD = 20 mA 1.45 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REF196–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = +3.5 V, T = +258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY 1
“G” Grade VO IOUT = 0 mA 3.290 3.3 3.310 V

LINE REGULATION2
“G” Grades ∆VO /∆VIN 3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA 4 8 ppm/V
2
LOAD REGULATION
“G” Grade ∆VO /∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA 6 15 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 4.1 V, ILOAD = 10 mA 0.80 V

VS = 4.3 V, ILOAD = 30 mA 1.00 V

LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 1.2 mV

NOISE VOLTAGE eN 0.1 Hz to 10 Hz 33 µV p-p

NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

–10– REV. C
REF196–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Condition Min Typ Max Units
1, 2
TEMPERATURE COEFFICIENT
“G” Grade3 TCVO/°C IOUT = 0 mA 10 25 ppm/°C

LINE REGULATION4
“G” Grade ∆VO/∆VIN 3.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 10 20 ppm/V

LOAD REGULATION4
“G” Grade ∆VO/∆VLOAD VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA 10 20 ppm/mA

DROPOUT VOLTAGE VS – V O VS = 4.1 V, ILOAD = 10 mA 0.80 V

VS = 4.3 V, ILOAD = 25 mA 1.00 V

SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
Logic Low Input Current IL –8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS
Parameter Symbol Condition Min Typ Max Units
REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 5.0 V, T = +258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY 1
“E” Grade VO IOUT = 0 mA 4.094 4.096 4.098 V
“F” Grade 4.091 4.101 V
“G” Grade 4.086 4.106 V

LINE REGULATION2
“E” Grade ∆VO/∆VIN 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 2 4 ppm/V
“F & G” Grades 4 8 ppm/V

LOAD REGULATION2
“E” Grade ∆VO/∆VLOAD VS = 5.4 V, 0 ≤ IOUT ≤ 30 mA 2 4 ppm/mA
“F & G” Grades 4 8 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 4.6 V, ILOAD = 10 mA 0.50 V

VS = 5.4 V, ILOAD = 30 mA 1.30 V

LONG-TERM STABILITY3 ∆VO 1000 Hours @ +125°C 1.2 mV

NOISE VOLTAGE eN 0.1 Hz to 10 Hz 40 µV p-p

NOTES
1
Initial accuracy includes temperature hysteresis effect.
2
Line and load regulation specifications include the effect of self-heating.
3
Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS (@ VS = +5.0 V, –408C ≤ TA ≤ +858C unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT 1, 2
“E” Grade TCVO /°C IOUT = 0 mA 2 5 ppm/°C
“F” Grade 5 10 ppm/°C
“G” Grade3 10 25 ppm/°C

LINE REGULATION4
“E” Grade ∆VO /∆VIN 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 10 ppm/V
“F & G” Grades 10 20 ppm/V

LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.4 V, 0 ≤ IOUT ≤ 25 mA 5 10 ppm/mA
“F & G” Grades 10 20 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 4.6 V, ILOAD = 10 mA 0.50 V

VS = 5.4 V, ILOAD = 25 mA 1.30 V

SLEEP PIN
Logic High Input Voltage VH 2.4 V
Logic High Input Current IH –8 µA
Logic Low Input Voltage VL 0.8 V
. Logic Low Input Current IL –8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

–12– REV. C
 REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = +5.0 V, –408C ≤ T ≤ +1258C unless otherwise noted)
S A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT 1, 2
“E” Grade TCVO /°C IOUT = 0 mA 2 ppm/°C
“F” Grade 5 ppm/°C
“G” Grade3 10 ppm/°C

LINE REGULATION4
“E” Grade ∆VO /∆VIN 4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA 5 ppm/V
“F & G” Grades 10 ppm/V

LOAD REGULATION4
“E” Grade ∆VO /∆VLOAD VS = 5.6 V, 0 ≤ IOUT ≤ 20 mA 5 ppm/mA
“F & G” Grades 10 ppm/mA

DROPOUT VOLTAGE V S – VO VS = 4.7 V, ILOAD = 10 mA 0.60 V

VS = 5.6 V, ILOAD = 20 mA 1.50 V
NOTES
1
For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2
TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3
Guaranteed by characterization.
4
Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.

REV. C –13–
REF19x Series
WAFER TEST LIMITS (@ ILOAD = 0 mA, TA = +25°C unless otherwise noted)

Parameter Symbol Condition Limits Units

INITIAL ACCURACY
REF191 VO 2.043/2.053 V
REF192 2.495/2.505 V
REF193 2.990/3.010 V
REF194 4.495/4.505 V
REF195 4.995/5.005
REF196 3.290/3.310 V
REF198 4.091/4.101 V
LINE REGULATION ∆VO /∆VIN (VO + 0.5 V) < VIN < 15 V, IOUT = 0 mA 15 ppm/V
LOAD REGULATION ∆VO /∆ILOAD 0 mA < ILOAD < 30 mA, VIN = (VO + 1.3 V) 15 ppm/mA

DROPOUT VOLTAGE VO – V+ ILOAD = 10 mA 1.25 V

ILOAD = 30 mA 1.55 V
SLEEP MODE INPUT
Logic Input High VIH 2.4 V
Logic Input Low VIL 0.8 V
SUPPLY CURRENT VIN = 15 V No Load 45 µA
Sleep Mode No Load 15 µA
NOTE
For proper operation, a 1 µF capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer probe to the limits shown. Due
to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications
based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS 1 DICE CHARACTERISTICS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . Indefinite OUTPUT OUTPUT
Storage Temperature Range 6 6

P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range
REF19x . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Package Type θJA2 θJC Units
8-Pin Plastic DIP (P) 103 43 °C/W
8-Pin SOIC (S) 158 43 °C/W 2 3 4
8-Pin TSSOP 240 43 °C/W V+ SLEEP GND

NOTES
1
Absolute maximum rating apply to both DICE and packaged parts, unless oth- REF19x Die Size 0.041 × 0.057 Inch, 2,337 Sq. Mils
erwise noted. Substrate Is Connected to V+, Number of Transistors:
2
θJA is specified for the worst case conditions, i.e., θJA is specified for device in Bipolar 25, MOSFET4. Process: CBCMOS1
socket for P-DIP, and θJA is specified for device soldered in circuit board for
SOIC package.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the REF19x features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–14– REV. C
 REF19x Series
5.004

5.003
OUTPUT VOLTAGE – Volts

5.002

5.001

5.000

4.999

4.998

4.997

4.996
–50 –25 0 25 50 75 100
TEMPERATURE – °C

REV. C –15–
REF19x Series
2
VIN = 15V 6
4 REF19x
0 10mA
1µF
0
–20
RIPPLE REJECTION – dB

–40
Figure 9b. Load Transient Response Measurement Circuit
–60

2V
–80 100

90

–100

–120

1mA
LOAD
10 100 1k 10k 100k 1M 30mA
FREQUENCY – Hz LOAD
10

0%

Figure 7a. Ripple Rejection vs. Frequency 2V 100µs

10µF
Figure 10a. Power ON Response Time
10µF
1k 2 6
VIN = +15V REF19x OUTPUT 2 6
4 REF19x
10µF 4 1k VIN = 7.0V 1µF
1µF
REF

Figure 7b. Ripple Rejection vs. Frequency Figure 10b. Power ON Response Time Measurement
Measurement Circuit Circuit

VIN = 7V 2 6 200Ω
REF19x VG = 2V p-p
4
1µF 1µF VS = 4.00V
Z

3
IO – Ω

0
10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz

Figure 8. Output Impedance vs. Frequency

5V
OFF 100

90
ON

10

0%
20mV 100µs

Figure 9a. Load Transient Response

–16– REV. C
 REF19x Series
35

5V 30
100

90

LOAD CURRENT – mA
25

20

15

10
10
0%
200mV 200µs
5

Figure 12. Line Transient Response 0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
REF195 DROPOUT VOLTAGE – V

Figure 13. Dropout Voltage vs. Load Current

+V Output Voltage Bypassing

For stable operation, low dropout voltage regulators and refer-
ences, in general, require a bypass capacitor connected from
VOUT
their VOUT pins to their GND pins. Although the REF19x fam-
ily of references are capable of stable operation with capacitive
loads exceeding 100 µF, a 1 µF capacitor is sufficient to guaran-
SHUTDOWN tee rated performance. The addition of a 0.1 µF ceramic ca-
pacitor in parallel with the bypass capacitor will improve load
current transient performance. For best line voltage transient
performance, it is recommended that the voltage inputs of these
devices are bypassed with a 10 µF electrolytic capacitor in paral-
lel with a 0.1 µF ceramic capacitor.
GND
Sleep Mode Operation
All REF19x devices include a sleep capability that is TTL/CMOS
Figure 14. Simplified Schematic level compatible. Internal to the REF19x at the SLEEP pin, a
pull-up current source to VIN is connected. This permits the
APPLICATIONS SECTION SLEEP pin to be driven from an open collector/drain driver.
Output Short Circuit Behavior A logic LOW or a zero volt condition on the SLEEP pin is re-
The REF19x family of devices is totally protected from damage quired to turn the output stage OFF. During sleep, the output
due to accidental output shorts to GND or to V+. In the event of the references becomes a high impedance state where its po-
of an accidental short circuit condition, the reference device will tential would then be determined by external circuitry. If the
shutdown and limit its supply current to 100 µA. sleep feature is not used, it is recommended that the SLEEP pin
be connected to VIN (Pin 2).
Device Power Dissipation Considerations
The REF19x family of references is capable of delivering load Basic Voltage Reference Connections
currents to 30 mA with an input voltage that ranges from 3.3 V The circuit in Figure 15 illustrates the basic configuration for
to 15 V. When these devices are used in applications with large the REF19x family of references. Note the 10 µF/0.1 µF bypass
input voltages, care should be exercised to avoid exceeding these network on the input and the 1 µF/0.1 µF bypass network on the
devices’ maximum internal power dissipation. Exceeding the output. It is recommended that no connections be made to
published specifications for maximum power dissipation or Pins 1, 5, 7, and 8. If the sleep feature is not required, Pin 3
junction temperature could result in premature device failure. should be connected to VIN.
The following formula should be used to calculate a device’s
maximum junction temperature or dissipation: NC 1 8 NC
VIN
2 7 NC
T – TA REF19x OUTPUT
PD = J SLEEP 3 6
θ JA
10µF 0.1µF
1µF 0.1µF
4 5 NC TANT
In this equation, TJ and TA are the junction and ambient tem-
peratures, respectively, PD is the device power dissipation, and
θJA is the device package thermal resistance. Figure 15. Basic Voltage Reference Configuration

REV. C –17–
REF19x Series
Membrane Switch Controlled Power Supply In this circuit, the power supply current of reference U1 flowing
With output load currents in the tens of mA, the REF19x family through R1–R2 develops a base drive for Q1, whose collector
of references can operate as a low dropout power supply in provides the bulk of the output current. With a typical gain of
hand-held instrument applications. In the circuit shown in Fig- 100 in Q1 for 100 mA–200 mA loads, U1 is never required to
ure 16, a membrane ON/OFF switch is used to control the op- furnish more than a few mA, so this factor minimizes tempera-
eration of the reference. During an initial power-on condition,
the SLEEP pin is held to GND by the 10 kΩ resistor. Recall
that this condition disables (read: tristate) the REF19x output.
When the membrane ON switch is pressed, the SLEEP pin is
momentarily pulled to VIN, enabling the REF19x output. At
this point, current through the 10 kΩ is reduced, and the inter-
nal current source connected to the SLEEP pin takes control.
Pin 3 assumes and remains at the same potential as VIN. When
the membrane OFF switch is pressed, the SLEEP pin is mo-
mentarily connected to GND, which disables once again the
REF19x output.

NC 1 8 NC
VIN
2 7 NC
1k REF19x OUTPUT
5% 3 6
1µF
4 5 NC TANT
ON

10kΩ
OFF

Figure 16. Membrane Switch Controlled Power Supply

Current-Boosted References with Current Limiting

While the 30 mA rated output current of the REF19x series is
higher than typical of other reference ICs, it can be boosted to
higher levels if desired, with the addition of a simple external
PNP transistor, as shown in Figure 17. Full time current limit-
ing is used for protection of the pass transistor against shorts.

Q1
R4 TIP32A
2Ω (SEE TEXT) OUTPUT TABLE
+VS = 6 TO 9V
(SEE TEXT)
R1 U1 VOUT (V)
1k
Q2
2N3906 REF192 2.5
R2 REF193 3.0
1.5k REF196 3.3
C2 REF194 4.5
100µF/25V 5.0
2 C3 F REF195
D1 0.1µF
U1 S
VC 3 REF196 6 +VOUT
(SEE TABLE) C1 3.3V
1N4148
10µF/25V @ 150mA
(SEE TEXT 4
ON SLEEP) (TANTALUM)
R3 R1
1.82k S
VS VOUT
COMMON F COMMON

Figure 17. A Boosted 3.3 V Reference with Current

Limiting

–18– REV. C
 REF19x Series
A Negative Precision Reference without Precision Resistors Stacking Reference ICs for Arbitrary Outputs
In many current-output CMOS DAC applications where the Some applications may require two reference voltage sources
output signal voltage must be of the same polarity as the refer- which are a combined sum of standard outputs. The circuit of
ence voltage, it is often required to reconfigure a current-switch- Figure 19 shows how this “stacked output” reference can be
ing DAC into a voltage-switching DAC through the use of a implemented.
1.25 V reference, an op amp and a pair of resistors. Using a
OUTPUT TABLE
current-switching DAC directly requires the need for an addi-
U1/U2 VOUT1 (V) VOUT2 (V)
tional operational amplifier at the output to reinvert the signal.
A negative voltage reference is then desirable from the point that REF192/REF192 2.5 5.0
REF192/REF194 2.5 7.0
an additional operational amplifier is not required for either +VS
REF192/REF195 2.5 7.5
reinversion (current-switching mode) or amplification (voltage VS > VOUT2 +0.15V 2
C1
switching mode) of the DAC output voltage. In general, any 0.1µF U2
3 REF19x 6 +VOUT2
positive voltage reference can be converted into a negative volt- (SEE TABLE) C2
VO (U2)
age reference through the use of an operational amplifier and a 4 1µF
pair of matched resistors in an inverting configuration. The dis-
advantage to that approach is that the largest single source of er-
2
ror in the circuit is the relative matching of the resistors used. C3
0.1µF U1
3 REF19x 6 +VOUT1
The circuit illustrated in Figure 18 avoids the need for tightly R1
(SEE TABLE) C4
matched resistors with the use of an active integrator circuit. In 4
VO (U1)
1µF 3.9kΩ
(SEE TEXT)
this circuit, the output of the voltage reference provides the in-
put drive for the integrator. The integrator, to maintain circuit VIN VOUT
COMMON COMMON
equilibrium, adjusts its output to establish the proper relation-
ship between the reference’s VOUT and GND. Thus, any nega-
tive output voltage desired can be chosen by simply substituting
for the appropriate reference IC. The sleep feature is main- Figure 19. Stacking Voltage References with the REF19x
tained in the circuit with the simple addition of a PNP transistor
and a 10 kΩ resistor. One caveat with this approach should be Two reference ICs are used, fed from a common unregulated
mentioned: although rail-to-rail output amplifiers work best in input, VS. The outputs of the individual ICs are simply con-
the application, these operational amplifiers require a finite nected in series as shown, which provides two output voltages,
amount (mV) of headroom when required to provide any load VOUT1 and VOUT2. VOUT1 is the terminal voltage of U1, while
current. The choice for the circuit’s negative supply should take VOUT2 is the sum of this voltage and the terminal voltage of U2.
this issue into account. U1 and U2 are simply chosen for the two voltages which supply
the required outputs (see table). If for example both U1 and
VIN U2 are REF192s, the two outputs are 2.5 V and 5.0 V.
While this concept is simple, some cautions are in order. Since
10kΩ
SLEEP 2N3906 the lower reference circuit must sink a small bias current from
U2 (50 µA–100 µA), plus the base current from the series PNP
TTL/CMOS
2
VIN output transistor in U2, either the external load of U1 or R1
1kΩ 1µF
3 SLEEP VREF 6
must provide a path for this current. If the U1 minimum load is
REF19x +5V
not well defined, then resistor R1 should be used, set to a value
GND
1µF A1
100Ω which will conservatively pass 600 µA of current, with the appli-
4
–VREF cable VOUT1 across it. Note that the two U1 and U2 reference
10kΩ 100kΩ
–5V
circuits are locally treated as macrocells, each having its own by-
A1 = 1/2 OP295,
passes at input and output for best stability. Both U1 and U2 in
1/2 OP291 this circuit can source dc currents up their full rating. The
minimum input voltage VS is determined by the sum of the out-
puts, VOUT2, plus the dropout voltage of U2.
Figure 18. A Negative Precision Voltage Reference
Uses No Precision Resistors A related variation on stacking two three-terminal references is
shown in Figure 19, where U1, a REF192, is stacked with a
two-terminal reference diode such as the AD589. Like the all
three-terminal stacked reference above, this circuit provides two
outputs, VOUT1 and VOUT2, which are the individual terminal
voltages of D1 and U1 respectively. Here this is 1.235 and 2.5,
which provides a VOUT2 of 3.735 V. When using two-terminal
reference diodes such as D1, the rated minimum and maximum
device currents must be observed, and the maximum load cur-
rent from VOUT1 can be no greater than the current set up by R1
and VO(U1). In the case with VO(U1) equal to 2.5 V, R1 provides
a 500 µA bias to D1, so the maximum load current available at
VOUT1 is 450 µA or less.

REV. C –19–
REF19x Series
+VS
VS > VOUT2 +0.15V 2

3 U1 6
+VOUT2
C1
REF192 3.735V
C2 R1
0.1µF VO (U1) 4.99k
4 1µF
(SEE TEXT)

+VOUT1
1.235V
D1 VO (D1) C3
AD589 1µF

VIN VOUT
COMMON COMMON

Figure 20. Stacking Voltage References with the REF19x

A Precision Current Source

Many times in low power applications, the need arises for a pre-
cision current source that can operate on low supply voltages.
As shown in Figure 21, any one of the devices in the REF19x
family of references can be configured as a precision current
source. The circuit configuration illustrated is a floating current
source with a grounded load. The reference’s output voltage is
bootstrapped across RSET which sets the output current into the
load. With this configuration, circuit precision is maintained for
load currents in the range from the reference’s supply current
(typically, 30 µA) to approximately 30 mA. The low dropout
voltage of these devices maximizes the current source’s output
voltage compliance without excess headroom.
VIN

2
VIN

3 SLEEP REF19x VREF 6

GND 1µF R1
4 RSET
ISY
P1
ADJUST

IOUT

RL

–20– REV. C
 REF19x Series
There is one application caveat which should be understood sistance within the forcing loop of the op amp. Since the op
about this circuit, which comes about due to the wire-OR na- amp senses the load voltage, op amp loop control forces the out-
ture. Since U1 and U2 can only source current effectively, nega- put to compensate for the wiring error and to produce the cor-
tive going output voltage changes which require the sinking of rect voltage at the load. Depending on the reference device
current will necessarily take longer than positive going changes. chosen, operational amplifiers that can be used in this applica-
In practice, this means that the circuit is quite fast when under- tion are the OP295, the OP291, and the OP183/OP283.
going a transition from 3.3 to 5 V, but the transition from 5 to
VIN VIN
3.3 V will take longer. Exactly how much longer will be a func- RLW
+VOUT
tion of the load resistance RL seen at the output, and the typical 2 SENSE
1 µF value of C2. In general, a conservative transition time here VIN 2 RLW
1 +VOUT
will be on the order of several milliseconds for load resistances REF19x 3 A1
FORCE
in the range of 100 Ω–1 kΩ. Note that for highest accuracy at SLEEP 3 VOUT 6
GND 1µF RL
the new output voltage, several time constants should be al- 4 100kΩ
lowed ( >7.6 time constants for <1/2 LSB error @ 10 bits, for A1 = 1/2 OP295
1/2 OP292
example). 1/2 OP283

Kelvin Connections
In many portable instrumentation applications where PC board Figure 23. A Low Dropout, Kelvin Connected Voltage
cost and area go hand-in-hand, circuit interconnects are very of- Reference
ten of dimensionally minimum width. These narrow lines can
cause large voltage drops if the voltage reference is required to A Fail-Safe 5 V Reference
provide load currents to various functions. In fact, a circuit’s Some critical applications require a reference voltage to be
interconnects can exhibit a typical line resistance of 0.45 mΩ/ maintained constant, even with a loss of primary power. The
square (1 oz. Cu, for example). In those applications where low standby power of the REF19x series and the switched out-
these devices are configured as low dropout voltage regulators, put capability allow a “fail-safe” reference configuration to be
these wiring voltage drops can become a large source of error. implemented rather easily. This reference maintains a tight out-
To circumvent this problem, force and sense connections can be put voltage tolerance for either a primary power source (ac line
made to the reference through the use of an operational ampli- derived) or a standby (battery derived) power source, automati-
fier, as shown in Figure 23. This method provides a means by cally switching between the two as the power conditions change.
which the effects of wiring resistance voltage drops can be elimi-
The circuit of Figure 24 illustrates the concept, which borrows
nated. Load currents flowing through wiring resistance produce
from the switched output idea of Figure 21, again using the
an I-R error (ILOAD × RWIRE) at the load. However, the Kelvin
REF19x device family output “wire-OR” capability. In this
connection overcomes the problem by including the wiring re-
case, since a constant 5 V reference voltage is desired for all

+VBAT
C2
0.1µF
+VS 2

3 U1 6
R1 REF195
1.1MΩ R3 R6
10MΩ 4 +5.000V
100k Q1
2N3904 C1
3 7 0.1µF
6
2
2 C3
4 1µF
R2 U3 3 U2 6
100k AD820 REF195
R4
900k 4

C4 R5
0.1µF 100k
VS, VBAT VOUT
COMMON COMMON

Figure 24. A Fail-Safe 5 V Reference

REV. C –21–
REF19x Series
conditions, two REF195 devices are used for U1 and U2, with A Low Power, Strain Gage Circuit
their ON/OFF switching controlled by the presence or absence As shown in Figure 25, the REF19x family of references can
of the primary dc supply source, VS. VBAT is a 6 V battery be used in conjunction with low supply voltage operational am-
backup source, which supplies power to the load only when VS plifiers, such as the OP492 and the OP283, in a self-contained
fails. For normal (VS present) power conditions, VBAT sees only strain gage circuit. In this circuit, the REF195 was used as the
the 15 µA (max) standby current drain of U1 in its OFF state. core of this low power, strain gage circuit. Other references can
In operation, it is assumed that for all conditions either U1 or be easily accommodated by changing circuit element values.
U2 is ON, and a 5 V reference output is available. With this The references play a dual role as the voltage regulator to pro-
voltage constant, a scaled down version is applied to the com- vide the supply voltage requirements of the strain gage and the
parator IC U3, so providing a fixed 0.5 V input to the (–) input operational amplifiers as well as a precision voltage reference for
for all power conditions. The R1–R2 divider provides a signal the current source used to stimulate the bridge. A distinct fea-
to the U3 (+) input proportional to VS, which switches U3 and ture of the circuit is that it can be remotely controlled ON or
U1/U2 dependent upon the absolute level of VS. Op amp U3 is OFF by digital means via the SLEEP pin.
configured here as a comparator with hysteresis, which provides 100Ω
for clean, noise free output switching. This hysteresis is impor-
10µF
tant to eliminate rapid switching at the threshold due to VS REF195
ripple. Further, the device chosen is the AD820, a rail-rail out- 2 6

put device, which provides HI and LO output states within a 4

10µF 1µF
few mV of VS and ground for accurate thresholds, and compat-
ible drive for U2 for all VS conditions. R3 provides positive 57k 1% 0.1µF
feedback for circuit hysteresis, changing the threshold at the (+)
input as a function of U3’s output.
4
For VS levels lower than the LOWER threshold, U3’s output is 3
10k 1/4
low, thus U2 and Q1 are OFF, while U1 is ON. For VS levels 1% OP492
1 2N2222
0.1µF
higher than the UPPER threshold, the situation reverses, with 2 11
U1 OFF, and both U2 and Q1 ON. In the interest of battery
power conservation, all of the comparison switching circuitry is 500Ω
powered from VS, and is so arranged that when VS fails, the de- 0.1%

fault output comes from U1.

For the R1–R3 values as shown, the LOWER/UPPER VS
0.01µF
switching thresholds are approximately 5.5 V and 6 V, respec- 10k 1%
tively. These can obviously be changed to suit other VS sup- 20k 1%

plies, as can the REF19x devices used for U1 and U2, over a
13 20k 1%
range of 2.5 V to 5 V of output. U3 can operate down to a VS 1/4 6
14
of 3.3 V, which is generally compatible with all family devices. OP492
1/4
12 7 OUTPUT
OP492
2.21k 5
10k 1%

9
20k 1%
1/4
8
OP492
10 20k
1%

Figure 25. A Low Power, Strain Gage Circuit

–22– REV. C
 REF19x Series
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Epoxy DIP (P Suffix)

0.430 (10.92)
0.348 (8.84)

8 5
0.280 (7.11)
0.240 (6.10)
1 4 0.325 (8.25)
0.300 (7.62)
PIN 1 0.060 (1.52)
0.015 (0.38) 0.195 (4.95)
0.210 (5.33)
MAX 0.115 (2.93)
0.130
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381)
0.022 (0.558) 0.100 0.070 (1.77) SEATING
PLANE 0.008 (0.204)
0.014 (0.356) (2.54) 0.045 (1.15)
BSC

8-Lead Narrow Body SO (S Suffix)

0.1968 (5.00)
0.1890 (4.80)

8 5
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 4 0.2284 (5.80)

PIN 1 0.0688 (1.75) 0.0196 (0.50)

x 45°
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.0040 (0.10)

8°
0.0500 0.0192 (0.49) 0°
SEATING (1.27) 0.0138 (0.35) 0.0098 (0.25) 0.0500 (1.27)
PLANE BSC 0.0075 (0.19) 0.0160 (0.41)

8-Lead TSSOP (RU Suffix)

0.122 (3.10)
0.114 (2.90)

8 5
0.177 (4.50)
0.169 (4.30)

0.256 (6.50)
0.246 (6.25)

1
4

PIN 1
0.0256 (0.65)
0.006 (0.15) BSC
0.002 (0.05) 0.0433
(1.10)
MAX 0.028 (0.70)
8°
0.0118 (0.30) 0° 0.020 (0.50)
SEATING 0.0079 (0.20)
PLANE 0.0075 (0.19)
0.0035 (0.090)

REV. C –23–
–24–
PRINTED IN U.S.A. C1951b–2–3/96