Application Note AN-43

®
TOPSwitch-HX Family
Design Guide

Introduction up and shutdown of the power supply during line sag or line
surge conditions. Power Integrations’ EcoSmart® technology
The TOPSwitch-HX is a highly integrated monolithic off-line enables supplies designed around the TOPSwitch-HX family to
switcher IC designed for off-line power supplies. TOPSwitch-HX consume less than 200 mW at no load and maintain constant
integrated circuits enable design of power supplies up to 195 W, efficiency over the full line and load range. TOPSwitch-HX family
while providing high efficiency under all load conditions. of solutions easily meets energy efficiency standards such as the
TOPSwitch-HX also provides very good performance at low load California Energy Commission (CEC), European Code of Conduct
and during standby (no load) operation. The TOPSwitch-HX and ENERGY STAR.
family allows the designer to meet the efficiency requirements for
the new energy-efficiency standards. Innovative and proprietary Basic Circuit Configuration
features enable design of compact and cost effective switching
power supplies while reducing overall design cycle time and The discussion of the function of application-specific
system cost. The TOPSwitch-HX family also enables the design requirements, such as constant current, constant power outputs,
of power supplies with robust functionality and provides etc., is beyond the scope of this design guide. However, such
enhanced safety features such as output overvoltage protection, requirements may be satisfied by adding additional circuitry to
overload power limiting and hysteretic thermal protection. the basic converter descriptions shown here. For more
information on additional circuit capabilities, design examples
Each member of the family has a high-voltage power MOSFET and other information, visit the Power Integrations web site or
and its controller combined monolithically. Internal start-up bias contact your PI sales representative.
current is drawn from a high-voltage current source connected to
the DRAIN pin, eliminating the need for external start-up circuitry. Scope
The internal oscillator is frequency modulated (jitter) to reduce
EMI. In addition, the ICs have integrated functions that provide This application note is intended for engineers designing an
system-level protection. The auto-restart function limits power isolated AC-DC flyback power supply using the TOPSwitch-HX
dissipation in the MOSFET, the transformer and the output diode family of devices. It provides guidelines to enable an engineer
during overload, output short-circuit or open-loop conditions. to quickly select key components and also complete a suitable
The auto-recovering hysteretic thermal shutdown function also transformer design. To help simplify the task, the application
disables MOSFET switching if temperature exceeds safe limits. note refers directly to the PI Xls design spreadsheet that is part of
A programmable UV/OV detection feature allows glitch free start- the PI Expert™ design software suite available at no charge from

+
AC DC
IN OUT
RLS -

ROVP VROVP

D V
CONTROL
TOPSwitch-HX C

S X F
RIL

PI-4687-092007

Figure 1. Typical TOPSwitch-HX Flyback Power Supply with Primary Sensed Overvoltage Protection.

www.powerint.com March 2008

 Application Note AN-43

www.powerint.com. The basic configuration used in • Enter efficiency estimate [B9]

TOPSwitch-HX flyback power supplies is shown in Figure 1, 0.8 for universal input voltage (85-265 VAC) or single
which also serves as the reference circuit for component 100/115 VAC (85-132 VAC) and 0.85 for a single 230 VAC
identifications used in descriptions throughout this application (185-265 VAC) design. Adjust the number accordingly
note. based on measurement at peak load and VACMIN.
• Enter loss allocation factor Z [B10]
In addition to this application note, the reader may also find the 0.5 for typical application (adjust the number accordingly
TOPSwitch-HX Reference Design Kits (RDKs) useful. Each after first prototype-board evaluation)
contains a fully functional engineering prototype board, • Enter CIN input capacitance [B13]
engineering report and device samples. Further details on 3 μF/W for universal (85-265 VAC) or single (100/115 VAC)
downloading PI Expert, and obtaining an RDK and updates to Use 1 μF/W single 230 VAC for single (185-265 VAC).
this document can be found at www.powerint.com. • Select the TOPSwitch-HX part from the drop down list or
enter directly [B17]
Quick Start • Select the device in the table below according to output
power and line input voltage
Readers familiar with power supply design and Power • Enter Operating Frequency – [B22]
Integrations design software may elect to skip the step-by-step “H” for 66 kHz operation
design approach described later, and can use the following “F” for 132 kHz operation
information to quickly design the transformer and select the If P, G and M packages are chosen, selecting “H” or “F” in
components necessary for a first prototype. For this approach, cell B22 does not change the design as these
only the information described below needs to be entered into parts only operate at 66 kHz (nominal) frequency.
the PI Xls spreadsheet, other parameters will be automatically • Enter core type (if desired) from drop down menu [B52]
selected based on typical design requirements. References to A suggested core size will be selected automatically if
spreadsheet cell locations are provided in square brackets [cell none is entered
reference]. If any warnings are generated, make changes to the
design by following instructions in spreadsheet column F
• Enter AC input voltage range VACMIN, VACMAX and minimum line • Build transformer
frequency fL [B3, B4, B5] • Select key components
• Enter Nominal Output Voltage VO [B6] See Steps 7 through 12.
• For designs with a peak load condition, enter average output • Build prototype and iterate design as necessary, replacing
power, else enter continuous output power [B7] estimates in the spreadsheets with measured values as
• For designs with a peak load current, enter peak load current appropriate (e.g. efficiency, VMIN).
else leave blank [B8]

Output Power Table

230 VAC ±15%4 85-265 VAC 230 VAC ±15% 85-265 VAC
Product5 Open Open Product5 Open Open
Adapter1 Peak3 Adapter1 Peak3 Adapter1 Adapter1
Frame2 Frame2 Frame2 Frame2
TOP252PN/GN 21 W 13 W TOP252EN 10 W 21 W 6W 13 W
9W 15 W 6W 10 W
TOP252MN 21 W 13 W
TOP253EN 21 W 43 W 13 W 29 W
TOP253PN/GN 38 W 25 W
15 W 25 W 9W 15 W
TOP253MN 43 W 29 W TOP254EN/YN 30 W 62 W 20 W 43 W
TOP254PN/GN 47 W 30 W TOP255EN/YN 40 W 81 W 26 W 57 W
16 W 28 W 11 W 20 W
TOP254MN 62 W 40 W
TOP256EN/YN 60 W 119 W 40 W 86 W
TOP255PN/GN 54 W 35 W
19 W 30 W 13 W 22 W TOP257EN/YN 85 W 157 W 55 W 119 W
TOP255MN 81 W 52 W
TOP256PN/GN 63 W 40 W TOP258EN/YN 105 W 195 W 70 W 148 W
21 W 34 W 15 W 26 W
TOP256MN 98 W 64 W
TOP259EN/YN 128 W 238 W 80 W 171 W
TOP257PN/GN 70 W 45 W
25 W 41 W 19 W 30 W TOP260EN/YN 147 W 275 W 93 W 200 W
TOP257MN 119 W 78 W
TOP258PN/GN 77 W 50 W TOP261EN/YN 177 W 333 W 118 W 254 W
29 W 48 W 22 W 35 W
TOP258MN 140 W 92 W
Table 1. Output Power Table.
Notes:
1. Minimum continuous power in a typical non-ventilated enclosed adapter measured 3. Peak power capability in any design at +50 °C ambient.
at +50 °C ambient. Use of an external heat sink will increase power capability. 4. 230 VAC or 110/115 VAC with doubler.
2. Minimum continuous power in an open frame design at +50 °C ambient. 5. Packages: P: DIP-8C, G: SMD-8C, M: SDIP-10C, Y: TO-220-7C, E: eSIP-7C.
See part ordering information.

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 AN-43 Application Note

• Power Integrations offers a transformer prototyping service Power (W)

and links to other vendors: for details see www.powerint.com/ P3

componentsuppliers.htm

Step-by-Step Transformer Design Procedure

PI-4329-030906
P2
Introduction

The design flow allows for design of power supplies both with or
P1
without a peak output power requirement. This is of particular
relevance when using the P, G or M packages. Here the current
limit enables design of power supplies capable of delivering Δt1 Δt2 Time (t)
peak power for a short duration limited only by thermal T
characteristics of the TOPSwitch-HX package and ratings of
Figure 2. Continuous (average) output power calculation example.
other components in the circuit.

As average power increases, based on the measured Where PX are the different output power conditions, Δt X are the
transformer and device temperature, it may be necessary to durations of each peak power condition and T is the period of
select a larger transformer to allow increased copper area for one cycle of the pulsed load condition
the windings and/or to increase the amount of device heat
sinking The design procedure requires both peak and continuous
(average) powers to be specified. If there is no peak power
The power table (Table 1) provides guidance for peak and requirement for the design, the same value should be used for
continuous (average) power levels obtainable in both sealed continuous as well as peak power.
adapter and open frame applications. For the P, G and M
packages, the power values for Adapter and Open Frame are The peak power is used to select the TOPSwitch-HX device and
thermally limited. The peak values represent the electrically design the transformer for power delivery at minimum input line
limited output power, assuming operation at current limit (ILIM(MIN)). voltage while continuous (or average power if the peak load is
For the Y package, the Adapter power values are also thermally periodic) is used for thermal design and may affect the size of the
limited, however, the Open Frame values are electrically limited transformer and the heat sink.
and therefore also represent the peak output power. As the
continuous power values are thermally limited, they indicate the Step 1. Enter Application Variables VACMIN, VACMAX, fL , VO,
upper limit of continuous power for worst case conditions but PO(AVE), PO(PEAK) , η, Z, VB, tC, CIN
may vary depending on the specific application. For example, if Determine the input voltage range from Table 2.
the peak power condition has a very low duty cycle, such as the
1-second peak required to close the drawer in a DVD player, Nominal Input Voltage (VAC) VACMIN VACMAX
then the thermal rise of the device (and transformer) is only a 100 / 115 85 132
function of the continuous average power. However, if the peak 230 195 265
power is repetitive with a significant duty cycle, then it would
need to be considered as a limiting factor in the design. Universal 85 265
Table 2. Standard Worldwide Input Line Voltage Ranges.
Figure 2 shows how to calculate the average power
Line Frequency, fL
requirements for a design with two different peak load
50 Hz for universal or single 100 VAC, 60 Hz for single 115 VAC
conditions.
input. 50 Hz for single 230 VAC input. These values represent
PAVE = P1 + ] P3 - P1 g # d1 + ] P2 - P1 g # d2 typical line frequencies rather than minimums. For most
Dt Dt applications this gives adequate overall design margin. For
d1 = T 1 , d2 = T 2

Figure 3. Application Variable Section of TOPSwitch-HX Design Spreadsheet.

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 Application Note AN-43

Figure 4. DC Input Voltage Parameters Showing Grey Override Cells for DC Input Designs.

absolute worst case or based on the product specification, Bias Winding Output Voltage (VB)
reduce these numbers by 6% (47 Hz or 56 Hz). For half-wave Enter the voltage at the output of the bias winding output. A
rectification, use FL/2. For DC input, enter the voltage directly value of 15 V is recommended. The voltage may be set to
into Cells B65 and B66. different values, for example, when the bias winding output is
also used as a primary side (non-isolated) auxiliary output.
Nominal Output Voltage, VO (V) Higher voltages increase no-load input power. Values below
Enter the nominal output voltage of the main output during the 10 V are not recommended as at light load there may be
continuous load condition. Generally the main output is the insufficient voltage to correctly bias the optocoupler, causing
output from which feedback is derived. loss of output regulation. A 10 μF, 50 V electrolytic capacitor is
recommended for the bias winding output filter.
Continuous / Average Output Power PO(AVE) (W)
Enter the average output power of the power supply. If the Bridge Diode Conduction Time, tC (ms)
power supply is a multiple output power supply, enter the sum Enter a bridge diode conduction time of 3.00 ms if there is no
total power of all the outputs. better data available.
Peak Output Power PO(PEAK) (W) Total Input Capacitance, CIN (μF)
Enter the peak output power under peak load conditions. If the Table 3 suggests suitable multiplication factors to be used for
design does not have a peak load condition, then leave this calculating input capacitance for different AC input formats.
entry blank and a value equal to PO(AVE) is assumed. PO(PEAK) is
used to calculate the primary inductance value.
Total Input Capacitance per Watt
Output Power (μF/W)
In multiple output designs, the output power of the main output
AC Input Voltage (VAC) Full Wave Rectification
(typically the output from which feedback is taken) should be
increased such that the peak power (or maximum continuous 100/115 3
output power as applicable) matches the sum of the output 230 1
power from all the outputs in the design. The individual output 85-265 3
voltages and currents should then be entered at the bottom of
the spreadsheet (cells [B120 to B166]). Table 3. Suggested Total Input Capacitance for Different Input Voltage Ranges.

Power Supply Efficiency, η The capacitance is used to calculate the minimum and
Enter the estimated efficiency of the complete power supply maximum DC voltage across the bulk capacitor and should be
measured at the output terminals under peak load conditions selected to keep the minimum DC input voltage, VMIN >70 V.
and worst-case line (generally lowest input voltage). Start with a
value of 80% for VACMIN of 85 VAC and 85% for 195 VAC. These Step 2 – Enter TOPSwitch-HX Variables: TOPSwitch-HX
are typical for a design where the majority of the output power is Device, Current Limit, VOR, VDS, VD,
drawn from an output voltage of 12 V and no current sensing is
present on the secondary. Once a prototype has been Select the correct TOPSwitch-HX device
constructed, then measured efficiency can be entered and a First, refer to the TOPSwitch-HX power table and select a
further transformer iteration performed, as appropriate. device based on the peak output power design. Then compare
the continuous power to adapter column numbers in the power
Power Supply Loss Allocation Factor, Z table, if the power supply is of fully enclosed type, or compare
This factor represents the proportion of losses between the to the open-frame column if the power supply is an open-frame
primary and the secondary of the power supply. Z factor is design. If the continuous power exceeds the value given in the
used together with the efficiency number to determine the actual power table (Table 1), then the next largest device should be
power that must be delivered by the power stage. For example, selected. Similarly, if the continuous power is close to the
losses in the input stage (EMI filter, rectification, etc) are not adapter power levels given in the power table, then it may be
processed by the power stage (transferred through the necessary to switch to a larger device based on the measured
transformer) and therefore, although they reduce efficiency, the thermal performance of the prototype.
transformer design is not effected by their effect on efficiency.
Peak power values are only given for P, G and M packages.
Secondary Side Losses
Z= For Y packages, high peak and continuous ratings are the
Total Losses
same. This is due to the power dissipation capability of the Y
For designs that do not have a peak power requirement, a value package. For the P, G and M, the maximum device dissipation
of 0.48 is recommended. For designs with a peak power is limited by both the junction to case and case to ambient
requirement, enter 0.65.

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 AN-43 Application Note

thermal impedance. However, for Y package the junction to Optimal selection of the VOR value depends on the specific
case impedance is low, and the device can be connected to a application and is based on a compromise between the factors
heat sink sized to maintain an acceptable device temperature. mentioned above.

External Current Limit Reduction Factor KI Values below 80 V are not usually recommended. Low VOR may
The factor KI sets the value of the current limit threshold. This cause excessive triggering of the MOSFET self-protection
allows the current limit level to be adjusted slightly above the feature during startup, especially in designs where all
minimum peak current (IP) required for power delivery. This outputs are >5 V.
optimizes the transformer design by limiting the peak flux
density during overload and start-up. TOPSwitch-HX ON State Drain to Source Voltage, VDS (V)
This parameter is the average ON state voltage developed
across the DRAIN and SOURCE pins of TOPSwitch-HX. By
For higher efficiency and improved thermal performance, KI, default, if the grey override cell is left empty, a value of 10 V is
also allows the selection of a larger TOPSwitch-HX device to be assumed. Use the default value if no better data is available.
used than required for power delivery by reducing KI, such that
the current limit of the larger device is equal to the original Output Diode Forward Voltage Drop, VD (V)
smaller part selected. Enter the average forward voltage drop of the (main) output
diode. Use 0.5 V for a Schottky diode or 0.7 V for a PN diode
High Line Operating Mode if no better data is available. By default, a value of 0.5 V is
This parameter confirms the mode of operation of the assumed.
TOPSwitch-HX at high line. It is desirable to operate in full-
frequency mode at high line as the switching frequency jitter Performance Goal VOR Value Comment
feature will be enabled. (See TOPSwitch-HX datasheet for an Suggestion
explanation of operating modes). This provides improved EMI Maximum output power / 135 V Maximizes power from
performance. smallest TOPSwitch-HX given device
Device
Reflected Output Voltage, VOR (V)
Highest Efficiency 100 V - 120 V Gives lowest overall
This parameter is the secondary winding voltage during diode losses between,
conduction, reflected back to the primary through the turns ratio conduction, output diode
of the transformer. The default value is 135 V; however the and leakage inductance
acceptable range for VOR is between 80 V and 135 V, providing
Multiple Output Design 90 V - 110 V Improves cross regulation
no warnings in the spreadsheet are triggered. For design by reducing transformer
optimization purposes, the following should be kept in mind: leakage inductance and
1. Higher VOR allows increased power delivery at VMIN, which peak secondary currents
minimizes the value of the input capacitor and maximizes
Table 4. Suggested Values for VOR.
power delivery from a given TOPSwitch-HX device.
2. Higher VOR reduces the voltage stress on the output diodes, Bias Winding Diode Forward Voltage Drop, VDB (V)
which in some cases may allow the use of a lower forward Enter the average forward voltage drop of the bias winding
drop Schottky diode for higher efficiency. output diode. Use 0.7 V for an ultra-fast recovery diode.
3. Higher VOR increases leakage inductance that reduces
efficiency of the power supply. Ripple to Peak Current Ratio, KP
4. Higher VOR increases peak and RMS current on the Figure 6 shows Kp < 1, indicating continuous conduction mode,
secondary side, which may increase secondary side copper KP is the ratio of ripple to peak primary current.
and diode losses.

Figure 5. TOPSwitch-HX Section of Design Spreadsheet.

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 Application Note AN-43

I
KP / KR = IR
P
Figure 7 shows Kp > 1, indicating discontinuous conduction
mode, KP is the ratio of primary MOSFET off time to the
secondary diode conduction time.

The value of KP should be in the range of 0.3 < KP < 6, and

guidance is given in the comments cell if the value is outside
this range.

A KP value of < 1 will result in higher efficiency by lowering the

primary RMS current. Typically the highest efficiency for a given
core size will be obtained with a KP range of 0.65 to 0.55, but
values outside this range are acceptable.

The spreadsheet will calculate the values of peak primary

current, the RMS ripple current, average primary current and
the maximum duty cycle for the design.
Figure 6. Continuous Mode Current Waveform, Kp≤1.

VOR # ]1 - D MAX g
K P / K DP =
]VMIN - VDS g # D MAX

Figure 7. Discontinuous Mode Current Waveform, Kp≥1.

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 AN-43 Application Note

Figure 8. Circuit Protection Component Section of Design Spreadsheet.

Step 3 – Choose Protection Features, Line Under / reduces by greater than the 4 μA V pin hysteresis requirement. If
Overvoltage, Output Overvoltage and Overload Power the current through the Zener and into the V (or M pin) exceeds
Limiting - Optional 336 μA, the latching shutdown feature of TOPSwitch-HX is
triggered, and the power supply latches off. To reset the latched
The optional line undervoltage lockout feature of TOPSwitch-HX, condition, either the input AC supply has to be removed for long
defines the startup voltage of the supply and prevents the power enough for the control pin capacitor to discharge below VC(RESET)
supply output from gliching when the input voltage is below the (~3 V) or the V (or M pin) can be externally pulled below 1 V.
normal operating range. Connecting a resistor from the input
capacitor to the V pin enables this feature. Enter the desired DC In a typical circuit, a high series resistance ROVP in the order of
voltage across the input capacitor, at which the power supply 5.1 kΩ will result in a non-latching shutdown. A low resistance in
should operate in the cell adjacent to the range of 4.7 Ω to 22 Ω will result in a latching shutdown.
VUV_STARTUP. The spreadsheet calculates the ideal resistor
value RLS. It is recommended that the resistor should be connected to the
V pin and the Zener diode cathode should be connected to the
The value of RLS also defines the line OV threshold. The bias winding output.
calculated voltage (VOV(SHUTDOWN)) at which the power supply will
stop operating due to an input overvoltage condition is Output Power Limiting vs Input Voltage (Optional)
displayed. The X-pin on the TOPSwitch-HX can be used to program a
current limit value lower than the maximum internal current limit
Output Overvoltage Shutdown - Optional for the part selected. A resistor connected from the X-pin to the
The output voltage of the bias winding can be used for primary source pin (RIL in Figure 1) allows selection of a fixed externally
sensed output overvoltage. This is an inexpensive way of programmed current limit. See datasheet for current limit
protecting the power supply should a component in the resistor selection curves.
feedback circuit fail.
The addition of a second resistor connected from the X-pin to
This feature can be enabled by connecting a series combination the DC-Bus (RPL), as shown in Figure 12, allows reduction of the
of a resistor and Zener diode from the bias winding output to the programmed current limit as a function of the line voltage. This
V pin (as shown in Figure 1). The spreadsheet estimates a value is desirable as typical Flyback power supplies that operate in
of the Zener diode required to initiate shutdown in case of loss continuous conduction mode at low line (KP < 1) will have a
of feedback but without false triggering during transient higher overload power capability at high line by 200-300%. In
conditions such as during dynamic load changes. certain applications this may require over design of the output
diode, transformer and output capacitors to handle the
During a fault, the bias winding voltage rises causing the Zener increased dissipation.
diode to conduct and current to flow into the V (or M) pin. If this
current exceeds 112 μA (IOV ) for longer than 100 μs, then The PIXls spreadsheet calculates the values of the two resistors
switching is disabled and the supply enters auto-restart. This required for power limiting vs line based on the choice of the
prevents further increase in output voltage but does not latch off TOPSwitch-HX part and the value of Kp selected. At VMIN the
the power supply. Switching is enabled again when the current target current limit value is equal to ILIMIT(MIN_EXT). At high line the

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 Application Note AN-43

Figure 9. Transformer Core and Construction Variables Section of Spreadsheet.

target current limit value is calculated based on the value size and, each will have different mechanical spacing. Refer to
required for specified PO(PEAK) multiplied by the margin factor, the bobbin datasheet or seek guidance from your safety expert
Overload Current Limit Ratio at VMAX. The recommended or transformer vendor to determine what specific margin is
value of 120% ensures that the MOSFET protection mode is not required.
triggered during startup, especially with high output voltage
designs. Lower values are acceptable, but startup into 66 kHz 132 kHz
maximum (peak) load at high input line voltage must be verified. Output Triple Triple
Power Margin Margin
Insulated Insulated
Wound Wound
Resistor values are calculated using the worst case current limit Wire Wire
reduction curves provided in the TOPSwitch-HX datasheet. EF12.6 EI22 EF12.6 EI22
EE13 EE19 EE13 EE19
Step 4 – Choose Core and Bobbin Based on Output EF16 EI22/19/6 EF16 EI22/19/6
Power and Enter AE, LE, AL , BW, M, L, NS 0 - 10 W EE16 EEL16 EE16 EEL16
EE19 EF20
Core effective cross-sectional area, AE: (cm2) EI22 EI25
Core effective path length, LE: (cm). EI22/19/6 EEL19
Core ungapped effective inductance, AL: (nH/turn2). EF20 EI28 EE19 EF20
Bobbin width, BW: (mm) 10 W - EEL22 EI22 EI25
Tape margin width equal to half the total margin, M (mm) 20 W EF25 EI22/19/6 EEL19
Primary Layers, L EF20
Secondary Turns, NS 20 W -
EF25 EI30 EI28
EPC30
30 W
Core Type EEL25
If the core type cell is left empty, the spreadsheet will default to EI28 E30/15/7 EF25 EEL22
the smallest commonly available core suitable for the continuous EI30 EER28
(average) output power specified. The entire list of cores E30/15/7 ETD29
30 W - EER28 EI35
available can be selected from the drop down list in the tool bar
50 W EI33/29/
of the PIXls design software.
13-Z
The grey override cells can be used to enter the core and EER28L
bobbin parameters directly. This is useful if a core is selected ETD29 EF32 EI28 EEL25
50 W -
that is not on the list, or the specific core or bobbin information EI35 ETD34 E30/15/7
70 W
differs from that referenced by the spreadsheet. EF32 EER28
ETD34 EI40 EI30 ETD29
Table 5 provides a list of commonly available cores and power E36/18/11 E36/18/11 E30/15/7 EI35
levels at which these cores can be used for typical designs. 70 W - EI40 EER35 EER28 EI33/29/
100 W ETD29 13-Z
Safety Margin, M (mm) EER28L
For designs that require safety isolation between primary and EF32
secondary but do not use triple-insulated wire, the width of the ETD39 ETD39 EI35 ETD34
safety margin to be used on each side of the bobbin should be 100 W - EER40 EER40 EF32 EI40
entered here. For universal input designs, a total windings 150 W E42/21/15 ETD34 E36/18/11
margin of 6.2 mm would be required, and a value of 3.1 mm EER35
would be entered into the spreadsheet. For vertical bobbins the E42/21/15 E42/21/20 E36/18/11 ETD39
margin may not be symmetrical. However, if a total margin of E42/21/20 E55/28/21 EI40 EER40
6.2 mm were required, then 3.1 mm would still be entered even E55/28/21 ETD39 E42/21/15
if the physical margin were only on one side of the bobbin. >150 W EER40 E42/21/20
E42/21/15 E55/28/21
For designs using triple insulated wire, it may still be necessary E42/21/20
E55/28/21
to enter a small margin in order to meet the required safety Table
creepage distances. Typically, many bobbins exist for any core Table 5. Transformer Core Table.

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 AN-43 Application Note

As the margin reduces the available area for the windings, the Maximum Operating Flux Density, BM (Gauss)
margin format described above may not be suitable for small A maximum value of 3000 Gauss during normal operation is
core sizes. If after entering the margin, more than 3 primary recommended. This limits transformer core loss and audible
layers (L) are required, it is suggested that either a larger core be noise generated at light load levels. Under these conditions the
selected or switch to a zero margin design approach using output voltage is low, and little reset of the transformer occurs
triple-insulated wire. during the MOSFET off time. This allows the transformer flux
density to staircase above the normal operating level. A value
Primary Layers, L of 3000 Gauss at the peak current limit of the selected device,
Primary layers should be in the range of 1 < L < 3, and in together with the built in protection features of TOPSwitch-HX,
general it should be the lowest number that meets the primary provides sufficient margin to prevent core saturation under
current density limit (CMA). Values of 100 Cmils/Amp for startup or output short circuit conditions.
designs <5 W scaling linearly to 500 Cmils/Amp at 200 W are
typical in designs without forced air cooling. Designs with more The MCM mode of operation used in TOPSwitch-HX can
than 3 layers are possible, but the increased leakage inductance generate audio frequency components in the transformer,
and issues associated with the physical fit of the windings especially if a long core is used. This audible noise generation
should be considered. A split primary construction may be is minimized when a value of 3000 Gauss is used for BM. This
helpful for designs where leakage inductance clamp dissipation results in an operating flux density of 750 Gauss in MCM mode.
is too high. Here half of the primary winding is placed on either Following this guideline and using the standard transformer
side of the secondary (and bias) winding in a sandwich production technique of dip varnishing practically eliminate
arrangement. audible noise. A careful evaluation of the audible noise
performance should be made using production transformer
Secondary Turns, NS samples before approving the design. Ceramic capacitors that
If the grey override cell is left blank, the minimum number of use dielectrics, such as Z5U, when used in clamp circuits may
secondary turns is calculated such that the maximum operating also generate audio noise. If this is the case, a cure may be to
flux density BM is kept below the recommended maximum of replace them with capacitors having a different dielectric, for
3000 Gauss (300 mT). In general, it is not necessary to enter a example a polyester film type.
number in the override cell except in designs where a lower
operating flux density is desired (see the explanation of BM
limits). Peak Flux Density, BP (Gauss)
A maximum value of 4200 Gauss is recommended to limit the
Step 5 – Iterate Transformer Design / Generate maximum flux density under start up and output short circuit
Prototype conditions. This calculation assumes worst-case current limit
and inductance values. In high ambient temperature
Iterate the design making sure that no warnings are displayed. applications, such as sealed adapters, this value may need to
Any parameters outside the recommended range of values can be reduced to 3600 Gauss due to the higher operating ambient
be corrected by following the guidance given in the right hand temperature. It is important to verify that core saturation does
column. not occur at maximum ambient temperature under overload
conditions just prior to loss of regulation.
Once all warnings have been cleared, the output transformer
design parameters can be used to wind a prototype transformer Maximum Primary Wire Diameter, OD (mm)
or sent to a vendor for samples. (See note on transformer By default, if the override cell is empty, double insulated wire is
prototying services in Quick Start section.) assumed and the standard wire diameter is chosen. The grey
override cells can be used to enter the wire diameter directly by
The key transformer electrical parameters are: the user.
Primary Inductance, LP (μH) The other factors automatically calculated by the
This is the target nominal primary inductance of the transformer. spreadsheet include:
Primary Inductance Tolerance, LPTOLERANCE(%)
Estimated Total Insulation Thickness, INS (mm)
This is the assumed primary inductance tolerance. A value of
Primary wire size, DIA: (mm)
10% is used by default; however if specific information is known
Primary wire gauge, AWG
from the transformer vendor, then this may be entered in the
Number of primary layers, L
grey override cell.
Estimated core center leg gap length: Lg: (mm)
Number of Primary Turns, NP Number of secondary turns, Ns
For low leakage inductance applications, a split primary Secondary wire size, DIAs: (mm)
construction may be used, and is recommended for designs Secondary wire gauge, AWG
above 20 W.
In multiple output design NSx, CMSx, AWGSx (where x is the
Gapped Core Effective Inductance, ALG: (nH/N2) output number) should also be used.
Used by the transformer vendor to specify the core center leg air gap.

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 Application Note AN-43

Figure 10. Transformer Primary Design Parameters Section of Spreadsheet.

Figure 11. Transformer Secondary Design Parameters Section of Spreadsheet – Multiple Outputs.

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 AN-43 Application Note

LPF
+ +

VAC CPF VO
-

CIN 470 7 VO = 12 V) CIRCUIT PERFORMANCE

100 7 VO = 5 V) Circuit Tolerance p1%
RD Load Regulation p0.2%
UTV817A RBIAS Line Regulation p0.2%
TOPSwitch-HX
1 k7 RS1
D V
CONTROL
RPL C VO - 2.5
100 nF R= X 10 k7
3.3 k7 2.5
S X F
TL431
Optional 100 nF RS2
10 k7

Feedback Circuit
PI-4836-101507

Figure 12. Typical TOPSwitch-HX Flyback Power Supply Using Optocoupler-TL431 Feedback Circuit.

C6 C7 C12
3.9 nF 2.2 nF R11 470 pF
1 kV 250 VAC 33 7 100 V

D7 C13 C14 C15

R6 T1 SB560 680 MF 680 MF L2 220 MF
22 k7 2 EER28 7 25 V 25 V 3.3 MH 25 V +12 V,
2W 2A
D1 D2 VR1 C16 C18
P6KE200A 470 pF R12 L3 RTN
1N4937 1N4007 33 7 3.3 MH 220 MF
100 V 10 V
3 11 +5 V,
2.2 A
R7 D8
20 7 SB530
4 9
1/2 W RTN
C10 C17
6 2200 MF
10 MF
D5 R10 50 V C11 10 V
D3 D4 R3 D6
2.0 M7 FR106 FR106 4.7 7 2.2 nF R19
1N4937 1N4007 250 VAC
5 10 7
L1 R4
6.8 mH 2.0 M7 VR3
R14 BZX55B8V2
C4 R13 22 7 8.2 V
R1 R2 100 MF 330 7 C19 2%
1 M7 1 M7 400 V VR2 1.0 MF
R5 1N5250B 50 V
5.1 k7 20 V U2B
C3 PS2501- R15
220 nF 1-H-A 1 k7
F1 275 VAC
3.15 A
U2A
TOPSwitch-HX PS2501-
RT1 O D M U1
L 10 7 t 1-H-A R18 R20
CONTROL TOP258PN 196 k7 12.4 k7
E C 1% 1%
R16 R17
10 k7 10 k7
N S R8 D9
C8 6.8 7 1N4148
90 - 265 100 nF C21
VAC 50 V C9 220 nF
47 MF 50 V
16 V C20
10 MF U3 R21
50 V TL431 10 k7
2% 1%
PI-4747-091407

Figure 13. Universal Input, 35 W Power Supply Using TOP258PN.

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 Application Note AN-43

Step 6 – Selection of TOPSwitch-HX External Components output power is reduced, resulting in lower light-load efficiency
and higher no-load consumption.
Control Pin – External Components
The schematic in Figure 12 shows the external components Figure 13 shows an example of an optimized clamp
required for a typical TOPSwitch-HX power supply design. It is arrangement. The clamp ensures that peak drain voltage is
strongly recommended that a 100 nF capacitor be connected limited to an acceptable level under worst-case conditions of
between the CONTROL pin and the SOURCE pin of the maximum input voltage, the overload power or output short
TOPSwitch-HX. This capacitor should be located adjacent to circuit and maximum ambient temperature.
the TOPSwitch-HX with short traces. In designs using surface
mount components, this capacitor should be located directly at
the pins of the TOPSwitch-HX. Rec. Diode VR(V) ID(A) Package Manufacturer
Schottky
In addition to the 100 nF capacitor connected to the CONTROL
1N5819 40 1 Axial General Semi
pin, a series combination of a 6.8 Ω resistor and a 47 μF
electrolytic capacitor is required to be connected between the SB140 40 1 Axial General Semi
CONTROL pin and the SOURCE terminal of the TOPSwitch-HX. SB160 60 1 Axial General Semi
The capacitor provides both timing for auto-restart and, together MBR160 60 1 Axial IR
with the dynamic impedance Zc of the CONTROL pin, sets the
11DQ06 60 1.1 Axial IR
dominant pole for the control loop. The combination of the
capacitor and series resistor adds a zero to the transfer function 1N5822 40 3 Axial General Semi
of the control loop, The resulting phase boost at approximately SB340 40 3 Axial General Semi
200 Hz improves the bandwidth of the power supply. MBR340 40 3 Axial IR

Step 7 – Selection of Line - Undervoltage / Overvoltage SB360 60 3 Axial General Semi

Components MBR360 60 3 Axial IR
SB540 40 5 Axial General Semi
The line undervoltage detection feature prevents the power SB560 60 5 Axial General Semi
supply from starting until the input voltage is above a defined
MBR745 45 7.5 TO-220 General Semi / IR
level. During power-up or when the switching of the power
MOSFET is disabled during auto-restart, the current into the MBR760 60 7.5 TO-220 General Semi
EN/UV pin must exceed 25 μA to initiate switching (lUV in data MBR1045 45 10 TO-220 General Semi / IR
sheet). As a resistor from the DC rail to the V pin is used to MBR1060 60 10 TO-220 General Semi
sense the input voltage, the supply voltage that causes the
MBR10100 100 10 TO-220 General Semi
current into the V pin to exceed 25 μA defines the undervoltage
threshold. The resistor connected to the V pin also sets the MBR1645 45 16 TO-220 General Semi / IR
voltage at which a line input overvoltage condition will be MBR1660 60 16 TO-220 General Semi
detected. MBR2045CT 45 20(2×10) TO-220 General Semi / IR
MBR2060CT 60 20(2×10) TO-220 Genreal Semi
The sense resistor should be rated above 400 V, generally
requiring either a single 0.5 W or two 0.25 W devices connected MBR20100 100 20(2×10) TO-220 General Semi / IR
in series. A typical value of 4 MΩ is suggested for use as line UFR
sense resistor for Universal input applications. Additional UF4002 100 1 Axial General Semi
guidance is provided by the design spreadsheet.
UF4003 200 1 Axial General Semi
If the undervoltage (UV) or the overvoltage (OV) functions are MUR120 200 1 Axial General Semi
to be used selectively, a number of circuits are provided in the EGP20D 200 2 Axial General Semi
TOPSwitch-HX family datasheet to ease the selection of external BYV27-200 200 2 Axial General Semi /
components. If the V pin function is not used, the V pin should Philips
be connected to the source pin. The V pin should not be left
UF5401 100 3 Axial General Semi
unconnected.
UF5402 200 3 Axial General Semi
Step 8 – Selection of Primary Clamp Components EGP30D 200 3 Axial General Semi
BYV28-200 200 3.5 Axial General Semi /
It is recommended that either a Zener clamp or an RCD Philips
combined with a Zener clamp be used in TOPSwitch-HX
MUR420 200 4 TO-220 General Semi
designs. This is to ensure that the peak drain voltage is limited
to below the BVDSS of the internal MOSFET while still maximizing BYW29-200 200 8 TO-220 General Semi
efficiency and minimizing no-load consumption. Philips
BYV32-200 200 18 TO-220 General Semi /
A standard RCD clamp designed to limit the peak drain voltage Philips
under peak load conditions represents a significant load as the Table 6. List of Diodes Suitable for use as the output rectifier.

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 AN-43 Application Note

The peak drain voltage should be limited to a maximum of 650 V Step 9 – Select Output Rectifier Diode
under these conditions to provide a margin for component
variation. In the design shown in Figure 13, the peak drain For each output use the values of peak inverse voltage (VR) and
voltage was limited to 600 V. The clamp diode (D5) must be a output current (IO) provided in the design spreadsheet to select
fast or an ultra-fast recovery type with a reverse recovery time the output diodes. Table 6 shows some commonly available
<500 ns. Under no circumstances should a standard recovery types.
rectifier diode be used. The high dissipation that may result
during startup or an output short circuit can cause failure of the VR ≥ 1.25 x PIVS: where PIVS is taken from the Voltage Stress
diode. Resistor R7 damps ringing for reduced EMI. Parameters section of the spreadsheet and Transformer
Secondary Design Parameters (Multiple Outputs).
Power supplies using different members of the TOPSwitch-HX
family will have different peak primary currents and leakage ID ≥ 2 x IO: where ID is the diode rated DC current, and IO is the
inductances, and therefore different leakage energy. Capacitor average output current. Depending on the temperature rise
C6 and R6 must be optimized for each design. As a general and the duration of the peak load condition, it may be
rule, minimize the value of capacitor C6 and maximize the value necessary to increase the diode current rating once a prototype
of resistor R6 while still meeting the recommended 650 V peak has been built. This also applies to the amount of heatsinking
drain voltage limit. required.

LPF
+ +

VAC CPF VO
-

CIN CIRCUIT PERFORMANCE

47 7 RBIAS Circuit Tolerance p5%
RD 470 7 Load Regulation p1%
Line Regulation p0.5%
TOPSwitch-HX
D V LTV817A

CONTROL
C
Feedback Circuit
S X F
DZ
Optional 100 nF Zener
2%

PI-4837-092107
* 47 7 is suitable for VO upto 7.5 V. For VO >7.5 V, a higher value may be required for optimum transient response.
**470 7 is good for Zeners with IZT = 5 mA. Lower values are needed for Zeners with higher IZT. (E.g. 150 7 for IZT = 20 mA).

Figure 14. Typical Zener Feedback Circuit.

LPF
+ +

VAC CPF VO
-

CIN 470 7 VO = 12 V) CIRCUIT PERFORMANCE

100 7 VO = 5 V) Circuit Tolerance p1%
RD Load Regulation p0.2%
UTV817A RBIAS Line Regulation p0.2%
TOPSwitch-HX RS1
D V 1 k7

CONTROL
C VO - 2.5
100 nF R= X 10 k7
3.3 k7 2.5
S X F
TL431
Optional 100 nF RS2
10 k7

Feedback Circuit
PI-4836-092107

Figure 15. Optocoupler-TL431 Feedback Circuit.

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 Application Note AN-43

Step 10 – Select Output Capacitor P/N CTR(%) BVCEO Manufacturer

Ripple Current Rating 4 Pin DIP
The spreadsheet calculates output capacitor ripple current using PC123Y6 80-160 70 V Sharp
the average output power. Therefore the actual rating of the
PC817X1 80-160 70 V Sharp
capacitor will depend on the peak to average power ratio of the
design. In most cases this assumption will be valid as capacitor SFH615A-2 63-125 70 V Vishay, Isocom
ripple rating is a thermal limitation, and most peak load durations SFH617A-2 63-125 70 V Vishay, Isocom
are shorter than the thermal time constant of the capacitor SFH618A-2 63-125 55 V Vishay, Isocom
(< 1 s). For such designs, select the output capacitor(s) such
ISP817A 80-160 35 V Vishay, Isocom
that the ripple rating is greater than the calculated value of IRIPPLE
from the spreadsheet. However, in designs with high peak to LTV817A 80-160 35 V Liteon
continuous (average) power and long duration peak load LTV816A 80-160 80 V Liteon
conditions, the capacitor rating may need to be increased based LTV123A 80-160 70 V Liteon
on the measured capacitor temperature rise under worst-case K1010A 60-160 60 V Cosmo
load and ambient conditions.
6 Pin DIP
In either case, if a suitable individual capacitor cannot be found, LTV702FB 63-125 70 V Liteon
then two or more capacitors may be used in parallel to achieve a LTV703FB 63-125 70 V Liteon
combined ripple current rating equal to the sum of the individual LTV713FA 80-160 35 V Liteon
capacitor ratings.
K2010 60-160 60 V Cosmo
Many capacitor manufacturers provide factors that increase the PC702V2NSZX 63-125 70 V Sharp
ripple current rating as the capacitor operating temperature is PC703V2NSZX 63-125 70 V Sharp
reduced from its data sheet maximum. This should also be PC713V1NSZX 80-160 35 V Sharp
considered to ensure that the capacitor is not oversized.
PC714V1NSZX 80-160 35 V Sharp
ESR Specification MOC8102 73-117 30 V Vishay, Isocom
The switching ripple voltage is equal to the peak secondary MOC8103 108-173 30 V Vishay, Isocom
current multiplied by the ESR of the output capacitor. It is
MOC8105 63-133 30 V Vishay, Isocom
therefore important to select low ESR capacitor types to reduce
the ripple voltage. In general, selecting a capacitor rated for the CNY17F-2 63-125 70 V Vishay, Isocom,
output ripple, will result in an acceptable value of ESR. Liteon

Table 7. Optocouplers.
Voltage Rating
Select a voltage rating such that VRATED≥1.25 x VO
For improved accuracy, Figure 15 shows a typical implemen-
Step 11 – Select Feedback Circuit Components tation using a reference IC. A TL431 is used to set the output
voltage and is programmed via a resistor divider RS1 and RS2.
The choice of the feedback circuit for a power supply is Resistor RBIAS provides the minimum operating current for the
governed by the desired output regulation. A simple feedback TL431 while RD sets the DC gain. The 100 nF capacitor and
circuit can be configured using a Zener diode in series with the series resistor roll off the gain of TL431 so that it does not
optocoupler diode. Though this method is inexpensive, it relies respond to cycle-by-cycle output ripple voltage. AC feedback
on the Zener diode to control the output voltage, which limits is provided directly through the optocoupler. An RC circuit
performance due to the device’s typically poor tolerance and placed across the resistor RD can provide additional phase
temperature coefficient. boost to improve control loop bandwidth.

Figure 14 shows a typical implementation of Zener feedback. A post filter (LPF and CPF) is typically added to reduce high
The drop across the Zener diode DZ, optocoupler series resistor frequency switching noise and ripple. Inductor LPF should be in
RFB1 and the optocoupler LED determine the output voltage. the range of 1 μH – 3.3 μH with a current rating above the peak
Resistor RBIAS provides a 1 mA bias current so that the Zener output current. Capacitor CPF should be in the range of 100 μF
diode is operating close to its knee voltage. Resistor RD sets the to 330 μF with a voltage rating ≥1.25 x VOUT. If a post filter is
DC gain of the feedback. Both these can be 0.125 W or 0.25 W, used then the optocoupler should be connected as shown,
5% types. Selecting a Zener with a low test current before the post filter inductor and the sense resistors, after the
(lZT ≤5 mA) is recommended to minimize the current needed to post filter inductor (when applicable).
bias the feedback network, reducing no-load input power
consumption. Table 7 is a list of commonly used optocouplers for feedback
control of isolated switching power supplies. Use of an
optocoupler with a CTR of 0.8 to 2 is recommended.

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 AN-43 Application Note

Isolation Barrier

Optional PCB slot for external C2 Y1-

heatsink in contact with R4 Capacitor
C6
SOURCE pins T1

Input Filter R3 C10 R9

VR1
Capacitor Output
Rectifier
D1
J1
D3 Output Filter
+ Transformer C7 Capacitor
S D
HV S
U1
- C1 S C
L1
S M
JP1

C3 C4
R8 C5
C8
R1 R2
D2 J2

R14
R13
R6

R11
R7

JP2 U3
R8 R10
Maximize hatched copper C9
areas ( ) for optimum U2
VR2
heat sinking R12

DC
- +
Out PI-4753-070307

Figure 16. PCB Layout Example Using P-Package.

Isolation Barrier

C2
Y1-
Optional PCB slot for external Capacitor
heatsink in contact with R6 C6 T1
SOURCE pins
Input Filter R5 R12 Output
VR1

Capacitor Rectifier
J1 D1
+ D3 Output Filter
HV Transformer C7 Capacitor
-
S D
S
S U1 C L1
C1 S X
S V

JP1
R7 C4
C5 C9 R13
R8
C3 R14
D2 C8
R1 R2 U3
R9
R10

R15
R11

R3 R4 JP2 J2
VR2 R16
Maximize hatched copper U2
areas ( ) for optimum R17
heat sinking

- DC +
Out PI-4752-070307

Figure 17. PCB Layout Example Using M-package.

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 Application Note AN-43

Isolation Barrier

C2
Y1-
R4 Capacitor
C6 T1
Input Filter

VR1
R3 R12
Capacitor Output
C10 Rectifier
D1
J1 Output Filter
+ Transformer
D3 Capacitor
HV HS1
U1 D
- S C7
F
C L1
C1 V
X

JP1
C4
R7 R10
R13
R1 R2 C5 C9
R8
D2 U3
C8

R14
JP2

R16
R11
R3 R4 J2
R9

R15
U2
R17
VR2 R12

- DC +
Out
PI-4751-070307

Figure 18a. PCB Layout Example Using Y-package.

Isolation Barrier

Y1-
Capacitor
Input Filter C6 R7
C7
Capacitor T1 C16 R12
J1 HS1 R6 D5
C4
+
D8
HV
-
Output
H52 Rectifier
U1 VR1 Transformer
C8 S D Output Filter
C17 Capacitor
F R8
C R22
X
R4
V L3
R3
R11 C10 C18
D6
R5 R14 U4
C9 C19
R10 C21
VR2 R20

R9
R17 J2
U2
JP2 R13
R15 R21

- DC +
Out PI-4975-022108

Figure 18b. Layout Considerations for TOPSwitch-HX Using E-Package and Operating at 66 KHz.

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 AN-43 Application Note

Isolation Barrier

Y1-
Input Filter C6 R7 Capacitor
C7
Capacitor C16 R12
R6
J1 H51 D5
C4
+ D8
HV H52 Output
-
Rectifier

U1 VR1 Transformer Output Filter

C8 S
D Capacitor
C9 C17
F R22
C L3
X
R4
V
R3
R11 C10 C18
R8 D6
R5 U4
R14
R10 C21 C19
R20
VR2
R9
R17 J2
U2
JP2 R13
R15 R21

- DC +
Out PI-4976-022108

Figure 18c. Layout Considerations for TOPSwitch-HX Using E-Package and Operating at 132 KHz.

Tips for Designs • The CONTROL pin bypass capacitor should be located as
close as possible to the SOURCE and CONTROL pins and its
Design Recommendations: SOURCE connection trace should not be shared by the main
• A soft finish circuit is recommended for high output voltage MOSFET switching currents or bias winding return connection.
designs ( >12 V). This ensures startup with full load at low • All SOURCE pin referenced components connected to the
line. In Figure 22, R23, D6 and C19 show one implementa- MULTI-FUNCTION (M), VOLTAGE MONITOR (V) or EXTERNAL
tion of the soft finish circuit. CURRENT LIMIT (X) pins should also be located closely
• A 10 μF, 50 V electrolytic capacitor is recommended for the between that pin and the SOURCE pin. The SOURCE
bias winding output filter to ensure appropriate bias voltage connection trace of these components should not be shared
for the optocoupler when the power supply is unloaded. The by the main MOSFET switching or bias winding return
bias winding output voltage should be a minimum of 10 V or currents. It is very critical that the SOURCE pin switching
higher. current is returned to the input capacitor negative terminal
through a separate trace that is not shared by the compo-
Circuit Board Layout nents connected to CONTROL, MULTI-FUNCTION,
TOPSwitch-HX is a highly integrated power supply solution that VOLTAGE-MONITOR or EXTERNAL CURRENT LIMIT pins.
integrates on a single die both the controller and the high This is because the SOURCE pin is also the controller ground
voltage MOSFET. The presence of high switching currents and reference pin. Any traces to the M, V or X pins should be kept
voltages together with analog signals makes it especially as short as possible and physically away from the DRAIN
important to follow good PCB design practice to ensure stable node, clamp components or any node with high di/dt or
and trouble free operation of the power supply. dv/dt, to prevent noise coupling.
• The LINE-SENSE resistor should be located close to the M or
When designing a PCB for the TOPSwitch-HX based power V pin to minimize the trace length on the high impedance M or
supply, it is important to follow the following guidelines: V pin side. The DC bus side of the V pin resistor should be
connected as close to the bulk capacitor as possible.
Primary Side Connections
• In addition to the 47 μF CONTROL pin capacitor, a high
• Use a single point (Kelvin) connection at the negative terminal
frequency 0.1 μF bypass capacitor in parallel should be used
of the input filter capacitor for the TOPSwitch-HX SOURCE
for local decoupling (C4 in Figures 16, 17 and 18).
pin and bias winding return. This improves surge capabilities
• The feedback optocoupler output should be routed away from
by returning surge currents from the bias winding directly to
any high voltage or high current traces to prevent noise
the input filter capacitor.
coupling.

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 Application Note AN-43

✓ Recommended Layout Preferred Y capacitor

✘ Poor Bias Winding Return Connection
placement CY1
(B+ to output RTN)
B+
B+

CLAMP
Line sense resistor CLAMP
(RLS) connected at
input capacitor

RLS placed CY2

physically
close to V-pin

IBIAS
RLS +
ICY2
D V TOPSwitch-HX
D V TOPSwitch-HX
CONTROL
Y capacitor and bias
RIL placed C CONTROL
return connected C
physically
with dedicated trace
close to X-pin Bias winding return and
S X F directly to PRI RTN
Kelvin connect at at input capacitor S X
primary to secondary
F
SOURCE pin, no displacement currents (via CY2)
RIL CONTROL pin decoupling flow through signal traces.
power currents flow
in signal traces capacitor placed directly Voltage drop ($VS) across trace
between CONTROL and impedances modulates source
SOURCE pins PRI RTN reference of controller
PRI RTN
PI-4838-092407 PI-4839-092407
$VS

For correct device operation ensure that good layout practices are followed Poor layout may cause higher output ripple or prevent proper device operation

✘ Poor Signal Source Connection ✘ Poor Line Sense Resistor Location and Connection
B+ IB+
B+

CLAMP $VB+
Voltage drop across CLAMP
trace impedance ($VB+)
modulates V-pin current
RLS placed away from
device. Increases V-pin
node area, increasing RLS
potential noise coupling

V-pin trace routed in

close proximity to
D V TOPSwitch-HX
Without Kelvin connection drain node causing
CONTROL noise coupling D V TOPSwitch-HX
at SOURCE pin, power
current (IS) creates voltage C CONTROL
drop in trace ($VS), which C
modulates source reference S X F
of controller
S X F

IS
PRI RTN
PRI RTN
PI-4840-092407
$VS PI-4841-092407

Poor layout may cause higher output ripple or prevent proper device operation Poor layout may cause changes in UV/OV thresholds and higher output ripple

Figure 19. Layout Considerations (Shown Schematically) and Common Mistakes.

Y-Capacitor Secondary
The preferred Y-capacitor connection is close to the transformer To minimize leakage inductance and EMI, the area of the loop
secondary output return pin(s) and the positive primary DC input connecting the secondary winding, the output diode and the
pin of the transformer. If the Y capacitor is connected between output filter capacitor should be minimized. In addition, sufficient
primary and secondary RTN, then the primary connection copper area should be provided at the anode and cathode
should be made via a dedicated trace from the Y-capacitor to terminal of the diode for heatsinking. A larger area is preferred at
the negative input capacitor terminal. This ensures that surge the quiet cathode terminal as a large anode area can increase
currents across the isolation barrier are routed away from traces high frequency radiated EMI.
connected to the TOPSwitch-HX.

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 AN-43 Application Note

ROVP VROVP RBIAS 1N4148 ROVP VROVP RBIAS

D V D V 0 to 47 7
CONTROL CONTROL
C C
100 nF

S X F S X F

PI-4822-022008 PI-4821-022008

Figure 20. Primary Sensed OVP circuit for TOPSwitch-HX based Flyback Figure 21. Primary Sensed Overvoltage Protection Circuit for a Flyback
Power Supply. Power Supply Using TOPSwitch-HX with Additional V-pin
Noise Decoupling.

Common Layout Problems to Avoid consumption. This results in the V pin node having a relatively
A poor layout will often result in performance issues that may high impedance, and it is therefore susceptible to noise. See
be time consuming to analyze, and they may occur at the end the layout guidline section for more detailed information. If the
of development, when PCB design changes are difficult. value of the series resistor ROVP is very small (in the range of
Figure 19 will help quickly identify the root cause of a problem 5 Ω to 22 Ω), the change of V-pin voltage in response to the
and correct the layout. The figure schematically shows injected current reaching 112 μA is often adequate to cause a
common layout mistakes and the reasons they should be current in excess of 336 μA to flow which results in latched
avoided overvoltage condition, requiring a reset.

Implementing Overvoltage Protection Feature In some designs the Zener diode connected from the bias
Using the TOPSwitch-HX winding may become a source of noise injected into the V-pin.
This happens when the bias winding output ripple is high, or
The bias winding output tracks the changes in the output the circuit board layout allows noise from adjacent circuits to
voltage for the flyback topology. If the feedback loop fails and be coupled in the trace connecting the Zener diode to the
results in an increase in output voltage, the output voltage of V-pin. In such a situation, the solution shown in Figure 21
the bias winding will also increase. This can be used to detect should be used.
an output overvoltage condition.
The circuit shown in Figure 21 is also useful in situations where
A suitable Zener diode with a series resistor connected it is difficult to achieve a latched shutdown due to slow rise in
between the bias winding output and the V pin can be selected power supply and bias winding output voltages after the
such that the Zener diode conducts once the bias winding feedback loop opens. Power supplies with large output
voltage rises significantly (typically 20% to 30%) above the capacitance and/or high output load may have this issue
highest voltage at the output of the bias winding during normal during an open loop fault. If necessary, RBIAS can be added to
operation (or under a transient loading condition during normal provide additional filtering of the bias output to prevent false
operation). A current injected in the V-pin in excess of 112 μA triggering of the OVP function.
will result in the switching cycle being terminated
instantaneously. If the injected current remains higher than Designing With the Y-Package (TOP259-TOP261)
112 μA for over 100 μS, the part will enter hysteretic OV
shutdown. In such a situation, switching will resume as soon The Y-Package option is offered for devices capable of
as the injected current reduces below the hysteresis point after delivering high power. Operation at high power involves high
completing an auto-restart cycle. drain switching currents, which can lead to a considerable
amount of switching noise that can affect device operation. The
If the injected current exceeds 112 μA, the V-pin responds by use of a dedicated pin for signal return (G pin) on the Y-Package
dropping the V-pin voltage by 0.5 V. If the drop in V-pin voltage reduces noise coupling and ensures stable operation.
causes the V-pin current to jump to a value higher than 336 uA,
the part enters a state of latched shutdown. In this state the The circuit on page 20 shows the standard configuration with
operation will not resume unless input is cycled and the C-pin the Y-Package parts (TOP259-TOP261).
capacitor is allowed to discharge, thereby resetting the part. In
addition the latched state may be reset by pulling the V-pin Note: The shorter pin length of the E package reduces noise
below 1 V with an external transistor. Care must be taken when coupling. For this reason, TOPSwitch-HX devices using the
designing external circuits connected to the V-pin. The V-pin E packages do not require a dedicated G pin.
operates at very low currents to reduce no-load power

19
www.powerint.com Rev. D 03/08
 Application Note AN-43

+V

10 μF
50 V

TOPSwitch-HX
D V
RPL CONTROL
C

S X G
Optional 6.8 Ω
100 nF
0V 4.7 μF

PI-5006-022908

Figure 22. Recommended Circuit Configuration for TOP259YN - TOP261YN with G Pin.

Designing High-Power Power Supplies Using 4. Minimize the length and loop area of PCB traces that carry
TOPSwitch – HX large switching currents and voltages as these can be a
source of radiated EMI.
At high power levels, design of power supplies using a flyback
topology presents the following challenges. For high power designs using any TOPSwitch-HX, and especially
for designs that use TOP259 – TOP261, it is recommended that
1. Proximity losses in the transformer can be significant and provision is made on the PCB board for a small RC network
make design of flyback transformers at high power levels positioned between the DRAIN and SOURCE terminals. This
very sensitive to the construction method with respect to reduces switching noise from affecting power supply operation
winding configuration and the choice of the number of and also helps in reduction of EMI. A 22 Ω to 150 Ω network
strands in multi wire configuration. The choice of wire size in resistor and a 1 kV rated ceramic capacitor in the range of
a high frequency transformer is dependent on switching 10 pF to 33 pF will be suitable for most applications. See
frequency. Skin depth is proportional to switching frequency Figure 27.
and limits the usable cross sectional area of each conductor.
Multi strand (filar) windings and litz wires are commonly used
to reduce conduction losses in high frequency transformers. Quick Design Checklist
To further reduce skin effects, the use of foil windings is
recommended for low voltage high current outputs. As with any power supply, all TOPSwitch-HX designs should be
2. Slight increases in leakage inductance of the transformer and verified with actual hardware to ensure that component
PCB traces can lead to a large increase in dissipation in the specifications are not exceeded under worst-case conditions.
snubber circuit. To reduce leakage inductance, it is important The following minimum set of tests is strongly recommended:
to use sandwich winding construction in the transformer and
minimize PCB trace lengths, especially the loop formed by 1. Maximum drain voltage – Verify that peak VDS does not
the secondary winding, output diode and output capacitors. exceed 675 V at highest input voltage and maximum
Design of the snubber circuit is critical in achieving high overload output power. Maximum overload output power
efficiency; typically, at high power levels a correctly sized occurs when the output is overloaded to a level just before
RCD clamp will ensure that the drain source voltage does not the power supply goes into auto-restart (loss of regulation).
exceed 650 V. 2. Maximum drain current – At maximum ambient temperature,
3. At high output currents, the secondary ripple current maximum input voltage and maximum output load, verify
increases and may be above the rating of a single very low drain current waveforms at start-up for any signs of trans-
ESR output capacitor. It is therefore common to use multiple former saturation and excessive leading edge current spikes.
capacitors in parallel. In this case, special attention must be TOPSwitch-HX has a minimum leading edge blanking time of
paid to equalize the trace length to all capacitors to give even 180 ns to prevent premature termination of the ON-cycle.
distribution of the ripple current. This ensures equal dissipa- Verify that the leading edge current spike is below the
tion and temperature rise, critical to ensure an acceptable allowed current limit envelope for the drain current waveform
operating life. Even with multiple capacitors, a second-stage at the end of the 180 ns minimum blanking period.
LC filter is required to reduce switching frequency ripple. 3. Thermal check – At maximum output power, minimum and
maximum input voltage and maximum ambient temperature;

20
Rev. D 03/08 www.powerint.com
 AN-43 Application Note

verify that temperature limits are not exceeded for the enough to ensure that the output diode and capacitors are
TOPSwitch-HX, transformer, output diodes and output reasonably sized. In this example, the TOP258YN is close to
capacitors. Enough thermal margin should be allowed for the upper limit of its power capability.
the part-to-part variation in the RDS(ON) of TOPSwitch-HX, as
specified in the data sheet. A maximum source pin tempera- Resistors R3, R6 and R7 provide power limiting, maintaining
ture for the P/G and M packages or tab temperature for Y/E relatively constant overload power with input voltage. Line
packages of 110 °C is recommended to allow for these sensing is implemented by connecting a 4 MΩ resistor from the
variations. Alternatively, the design margin can be verified by V pin to the DC rail. Resistors R4 and R5 together form the
connecting an external resistance that is in series with the 4 MΩ line sense resistor. If the DC input rail rises above
DRAIN pin and is attached to the same heat sink. The 450 VDC, then TOPSwitch-HX will stop switching until the
resistance selected would be equal to the difference between voltage returns to normal, preventing device damage.
the measured RDS(ON) of the device under test and the worst
case maximum specification. Due to the high primary current, a low leakage inductance
transformer is essential. Therefore, a sandwich winding with a
Appendix A copper foil secondary is used. Even with this technique, the
leakage inductance energy is beyond the power capability of a
Application Examples simple Zener clamp. Therefore, R1, R2 and C3 are added in
parallel to VR1 and VR3, two series Zener diodes being used to
A High Efficiency, 150 W, 250 – 380 VDC
share dissipation. During normal operation, very little power is
Input Power Supply
dissipated by VR1 and VR3, the leakage energy instead being
dissipated by R1 and R2. However, VR1 and VR3 are essential
The circuit shown in Figure 23 delivers 150 W (19 V at 7.7 A) at
to limit the peak drain voltage during start-up and/or overload
84% efficiency using a TOP258YN from a 250 VDC to 380 VDC
conditions to below the 700 V rating of the TOPSwitch-HX
input. A DC input is shown, as typically at this power level a
MOSFET. The schematic shows an additional snubber circuit,
power factor correction stage would precede the power supply.
consisting of R20, R21, R22, D5 and C18. This reduces turn-off
Capacitor C1 provides local decoupling, necessary when the
losses in the TOPSwitch-HX.
supply is remote from the main PFC output capacitor.
The secondary is rectified and smoothed by D2, D3 and C5,
Flyback topology is still usable at this power level due to the
C6, C7 and C8. Two windings are used and rectified with
high output voltage, keeping the secondary peak currents low

C4 R14 C14
2.2 nF 22 7 47 pF
R1 R2 250 VAC 0.5 W 1 kV C5-C8 C15-C16
250 - 380 68 k7 68 k7 820 MF 820 MF +19 V,
VDC 2W 2W 25 V L1 25 V 7.7 A

F1 RT1 O 1 13,14 3.3 MH

4A 57t R6 R4 C3
4.7 M7 2.0 M7 4.7 nF D2
1 kV MBR20100CT
11
D1 12
BYV26C D3 RTN
R7 R5 4 MBR20100CT
4.7 M7 2.0 -7
VR1, VR3
P6KE100A 9,10
7
C1 D4
22 MF 1N4148 R18 C17
400 V R20 5 22 7 47 pF
0.5 W 1 kV C20
1.5 k7 T1 R8 R12 1 MF
2W EI35 4.7 7 240 7 50 V
0.125 W
C9
D5 10 MF
VR2 50 V R24
1N4937 30 7
R21 1N5258B
R19 R23 0.125 W R16
1.5 k7 4.7 7 36 V 15 k7 U2 31.6 k7
2W 0.125 W PC817A 1%
TOPSwitch-HX R11 C12 R17
U1 U2 1 k7 4.7 nF
D V 0.125 W 562 7
TOP258YN PC817B 50 V 1%
R22
CONTROL
1.5 k7 C
2W C13
R13
56 k7 100 nF
S X F R10 D6 0.125 W 50 V
6.8 7 1N4148
C11 C19
100 nF 10 MF
C18 C10
50 V 50 V U3
120 pF 47 MF R15
R3 1 kV TL431 4.75 k7
8.06 k7 10 V
OV 2% 1%
1%
PI-4795-022908

Figure 23. 150 W, 19.5 V Power Supply using TOP258YN.

21
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 Application Note AN-43

separate diodes D2 and D3 to limit diode dissipation. Four The M-package part has an optimized current limit to enable
capacitors are used to ensure their individual maximum ripple design of power supplies capable of delivering high power for
current limits are not exceeded. Inductor L1 and capacitors a short duration.
C15 and C16 provide switching noise filtering.
Resistor R12 programs the current limit of the TOPSwitch-HX.
Output voltage is controlled using a TL431 reference IC. Resistors R11 and R14 provide a signal that reduces the current
Resistor R15, R16 and R17 form a potential divider to sense the limit with increasing DC bus voltage, thereby maintaining a
output voltage. Resistor R12 and R24 together limit the constant overload power level with increasing line voltage.
optocoupler LED current and set overall control loop DC gain. Resistors R1 and R2 implement the line undervoltage and
Control loop compensation is achieved using additional overvoltage function and also provide feed forward compen-
components, C12, C13, C20 and R13. Diode D6 and capacitor sation for reducing line frequency ripple in output. The
C19 form a soft finish network. This feeds current into the overvoltage feature stops TOPSwitch-HX switching during a line
control pin prior to output regulation, preventing output surge, extending the high voltage withstand voltage to 700 V
overshoot and ensuring startup under low line, full load without device damage.
conditions.
The snubber circuit comprising VR7, R17, R25, C5 and D2 limits
Sufficient heat sinking is required to keep the TOPSwitch-HX the maximum drain voltage and dissipates energy stored in the
device below 110 οC when operating under full load, low line leakage inductance of transformer T1. This clamp configuration
and maximum ambient temperature. Airflow may also be maximizes energy efficiency by preventing C5 from discharging
required if a large heat sink area is not acceptable. below the value of VR7 during the lower frequency operating
modes of TOPSwitch-HX. Resistor R25 damps high frequency
A High Efficiency, 20 W Continuous – 80 W Peak, ringing for reduced EMI.
Universal Input Power Supply
A combined output overvoltage and over power protection
The circuit shown in Figure 24 takes advantage of several of circuit is provided via the latching shutdown feature of
TOPSwitch-HX features to reduce system cost, power supply TOPSwitch-HX and R20, C9, R22 and VR5. Should the bias
size and improve power supply efficiency while delivering winding output voltage across C13 rise due to output overload
significant peak power. This design delivers 20 W continuous or an open loop fault (optocoupler failure), then VR5 conducts,
and 80 W peak at 32 V from an 85 VAC to 265 VAC input. A triggering the latching shutdown. To prevent false triggering
nominal efficiency of 82% at full load is achieved using due to short duration overload, a delay is provided by R20,
TOP258MN. R22 and C9.

C8 R19 C26
1 nF 68 7 100 pF
250 VAC 0.5 W 1 kV
C20 C31 32 V
330 MF 22 MF
50 V L2 50 V L3 625 mA, 2.5 APK
1 10
3.3 MH
D6-D7
D8 D9 VR7 2 STPS3150 RTN
R25 9
1N4007 1N4007 BZY97C150
C3 100 7 47 MH
120 MF 150 V 5
400 V C29
to R11
3
NC
C13
10 MF 220 nF
R1 C10
RT1 2 M7 3.6 M7 R17 C5 50 V 50 V
D11 D10 1 nF
1N4007 1N4007 10 7 1 k7 10 nF 4 250 VAC
0.5 W 1 kV
T1 D5
EF25 LL4148 R10
56 7 R8
L1 1.5 k7
5.3 mH D2
R2 R14 1N4007GP C28
D13 2 M7 3.6 M7 330 nF
1N4007 50 V
R23 R24 VR3
1N5255B
1 M7 1 M7 28 V
U2A
VR5 R20 PC817D
R3 1N5250B C9
R22 1 MF 130 k7
2 M7 20 V
C1 D V 2 M7 100 V
F1 R21
220 nF 3.15 A CONTROL R9
275 VAC 1 M7 2 k7
R4 0.125 W
2 M7
C
90 - 264 PI-4793-091207
VAC S X
R15
1 k7 R6
R12 TOPSwitch-HX
Q1 U4 C6 6.8 7
7.5 k7 100 nF
C30 2N3904 1% TOP258MN
50 V
100 nF
400 V Q2
Q3 C7
2N3904
2N3904 47 MF
R26 16 V
68 k7 R18
39 k7

Figure 24. 20 W Continuous, 80 W Peak, Universal Input Power Supply.

22
Rev. D 03/08 www.powerint.com
 AN-43 Application Note

To reset the supply following a latching shutdown, the V pin TOP Switch-HX features to reduce system cost and power
must fall below the reset threshold. To prevent the long reset supply size and to improve efficiency. This design delivers
delay associated with the input capacitor discharging, a fast 35 W total output power from a 90 VAC to 265 VAC input at an
AC reset circuit is used. The AC input is rectified and filtered by ambient of 50º C in an open frame configuration. A nominal
D13 and C30. While the AC supply is present, Q3 is on and efficiency of 84 % at full load is achieved using TOP258PN.
Q1 is off, allowing normal device operation. However when With a DIP-8 package, this design provides 35 W continuous
AC is removed, Q1 pulls down the V pin and resets the latch. output power using only the copper area on the circuit board
The supply will then return to normal operation when AC is underneath the part as heat sink. The different operating
again applied. modes of the TOPSwitch-HX provide significant improvement in
the no-load, standby, and light load performance of the power
Transistor Q2 provides an additional lower UV threshold to the supply as compared to previous generations of TOPSwitch.
level programmed via R1, R2 and the V pin. At low input AC
voltage, Q2 turns off, allowing the X pin to float, and thereby Resistors R1 and R2 provide line sensing, setting UV at 95 VDC
disables switching. and OV at 445 VDC.

A simple feedback circuit automatically regulates the output Diode D5, together with resistors R7, R6, capacitor C6 and
voltage. Zener VR3 sets the output voltage together with the Zener VR1, forms a clamp network that limits the drain voltage
voltage drop across series resistor R8, which sets the DC gain after the MOSFET inside the TOPSwitch turns OFF. Zener VR1
of the circuit. Resistors R10 and C28 provide a phase boost to provides a defined maximum clamp voltage and typically only
improve loop bandwidth. conducts during fault conditions such as overload. This allows
the RCD clamp (R6, R7, C6 and D5) to be sized for normal
Diode D6 is a low loss Schottky rectifier, and capacitor C20 is operation, thereby maximizing efficiency at light load.
the output filter capacitor. Inductor L3 is a common mode
inductor to limit radiated EMI when long output cables are Should the feedback circuit fail, output of the power supply will
used and the output return is connected to safety earth ground. exceed regulation limits. This increased voltage at output will
Examples of this include PC peripherals such as inkjet printers. also result in an increased voltage at the output of the bias
winding. Zener VR2 will break down, and current will flow into
A High Efficiency, 35 W, Dual Output - Universal Input the “M” pin of the TOPSwitch, initiating hysteretic overvoltage
Power Supply protection. Resistor R5 will limit the current into the M pin; if
latching OVP is desired, the value of R5 can be reduced to 20 Ω.
The circuit in Figure 25 takes advantage of several of the

C6 C7 R11 C12
3.9 nF 2.2 nF 33 7 470 pF
1 kV 250 VAC 100 V

D7 C13 C14 C15

R6 T1 SB560 680 MF 680 MF L2 220 MF
22 k7 2 EER28 7 25 V 25 V 3.3 MH 25 V +12 V,
2W 2A
D1 D2 VR1 C16 C18
P6KE200A 470 pF R12 L3 RTN
1N4937 1N4007 33 7 3.3 MH 220 MF
100 V 10 V
3 11 +5 V,
2.2 A
R7 D8
20 7 SB530
4 9
1/2 W RTN
C10 C17
6 2200 MF
10 MF
D5 R10 50 V C11 10 V
D3 D4 R3 D6
2.0 M7 FR106 FR106 4.7 7 2.2 nF R19
1N4937 1N4007 250 VAC
5 10 7
L1 R4
6.8 mH 2.0 M7 VR3
R14 BZX55B8V2
C4 R13 22 7 8.2 V
R1 R2 100 MF 330 7 C19 2%
1 M7 1 M7 400 V VR2 1.0 MF
R5 1N5250B 50 V
5.1 k7 20 V
C3 R15
220 nF 1 k7
F1 275 VAC
3.15 A
U2B U2A
TOPSwitch-HX PS2501- PS2501-
RT1 O D M U1
L 10 7 t 1-H-A 1-H-A R18 R20
CONTROL TOP258PN 196 k7 12.4 k7
E C 1% 1%
R16 R17
10 k7 10 k7
N S R8 D9
C8 6.8 7 1N4148
90 - 265 C21
VAC 100 nF
50 V C9 220 nF
47 MF 50 V
16 V C20
10 MF U3 R21
50 V TL431 10 k7
2% 1%
PI-4747-020508

Figure 25. Universal Input, 35W Power Supply Using TOP258PN.

23
www.powerint.com Rev. D 03/08
 Application Note AN-43

Output voltage is controlled using the amplifier TL431. Diode the V pin to the DC rail. Resistors R3 and R4 together form the
D9, capacitor C20 and resistor R16 form the soft finish circuit. 4 MΩ line sense resistor. If the DC input rail rises above
At start, capacitor C20 is discharged. As the output voltage 450 VDC, then TOP Switch-HX will stop switching until the
starts rising, current flows through the optocoupler diode inside voltage returns to normal, preventing device damage.
U2A, resistor R13 and diode D9 to charge capacitor C20. This
provides feedback to the primary circuit. The current in the This circuit features a high efficiency clamp network, consisting
optocoupler diode U2A gradually decreases as the capacitor of diode D1, zener VR1 and capacitor C5, together with
C20 becomes charged and the control amplifier IC U3 resistors R8 and R9. The snubber clamp is used to dissipate
becomes operational. This ensures that the output voltage the energy into the leakage reactance of the transformer. At
increases gradually and settles to the final value without any light load levels, very little power is dissipated by VR1, improving
overshoot. Diode D9 ensures that the capacitor C23 is efficiency as compared to a conventional RCD clamp network.
maintained charged at all times after startup, which effectively The secondary output from the transformer is rectified by diode
isolates C20 from the feedback circuit after start-up. Capacitor D2 and filtered by capacitors C13 and C14. Ferrite Bead L3 and
C23 discharges via R16 when the power supply shuts down. capacitor C15 form a second stage filter and effectively reduce
Resistor R18, R20 and R21 form a voltage divider network. the switching noise to the output.
The output of this divider network is primarily dependent on the
divider circuit formed using R20 and R21 but modified by Output voltage is controlled using a LM431 reference IC.
changes in voltage at the 12 V output due to the connection of Resistors R19 and R20 form a potential divider to sense the
resistor R18 to the output of the divider network. output voltage. Resistor R16 limits the optocoupler LED current
and sets the overall control loop DC gain. Control loop
Resistor R19 and VR3 improve cross regulation in case only the compensation is achieved using C18 and R21. The components
5 V output is loaded, which results in the 12 V output operating connected to the control pin on the primary side, C8, C9 and
at the higher end of the specification. R15, set the low frequency pole and zero to further shape the
control loop response. Capacitor C17 provides a soft finish
during startup. Optocoupler U2 is used for isolation of the
A High Efficiency, 65 W, Universal Input Power Supply feedback signal.
The circuit shown in Figure 26 delivers 65 W (19 V @ 3.42 A) at
88% efficiency using a TOP260EN operating over an input Diode D4 and capacitor C10 form the bias winding rectifier and
voltage range of 90 VAC to 265 VAC. filter. Should the feedback loop break due to a defective
component, a rising bias winding voltage will cause the Zener
Capacitors C1 and C6 and inductors L1 and L2 provide VR2 to break down and trigger the over voltage protection,
common mode and differential mode EMI filtering. Capacitor C2 which will inhibit switching.
is the bulk filter capacitor that ensures low ripple DC input to the
flyback converter stage. Capacitor C4 provides decoupling for An optional secondary side over voltage protection feature that
switching currents, reducing differential mode EMI. offers higher precision (as compared to sensing via the bias
winding) is implemented using VR2, R14 and U2. Excess
In this example, the TOP260EN is used at reduced current limit voltage at the output will cause current to flow through the
to improve efficiency. optocoupler U3 LED, which in turn will inject current in the V-pin
through resistor R13, thereby triggering the over voltage
Resistors R5, R6 and R7 provide power limiting, maintaining protection feature.
relatively constant overload power with input voltage. Line
sensing is implemented by connecting a 4 MΩ impedance from

24
Rev. D 03/08 www.powerint.com
 AN-43 Application Note

C6 C12
2.2 nF 1 nF R16
250 VAC 100 V 33 7
C5 VR1 C13 C14 L3 C15
2.2 nF BZY97C180 T1 470 MF 470 MF Ferrite 47 MF
1 kV 25 V 25 V Bead 25 V 19 V, 3.42 A
180 V 4 RM10 FL1

D2
3KBP08M MBR20100CT
BR1 5 FL2
R8 R9 RTN
100 7 1 k7
C10 VR2
6 22 MF R10 VR3
1N5248B
R3 R5 3 50 V 73.2 k7 18 V BZX79-C22
2.0 M7 5.1 M7 22 V
C11
D1 100 nF
DL4937 50 V
2
D4 BAV19WS R11
L1 2 M7
12 mH R16 R18
R4 R6
2.0 M7 6.8 M7 680 7 47 7
R12
C2 D5 5.1 k7 U3B
R1 R2 120 MF BAV19WS C7 PC357A
2.2 M7 2.2 M7 400 V 100 nF U3A
C4
100 nF D3 25 V PC357A
400 V BAV19WS
C1 U2A
F1 330 nF LTY817C
U2B
4A 275 VAC TOPSwitch-HX R13 LTY817C
U1 5.1 7
D V TOP260EN
L R14
CONTROL D6 R19
100 7 1N4148
E C 68.1 k7
C18
100 nF
N R15
S X F
6.8 7 C16
90 - 265 R21
VAC C8 1 MF 1 k7
R7 100 nF C9 50 V
C3 15 k7 47 MF
470 pF 50 V
1% 16 V C17 U4
250 VAC 33 MF LM431
35 V 2% R20
L2 10 k7
Ferrite Bead

PI-4998-021408

Figure 26. 65 W, 19 V Power Supply Using TOP260EN.

Appendix B shape. Since the current wave shapes are assumed to be the
same for all outputs, their ratio of RMS to average currents must
Multiple Output Flyback Power Supply Design also be identical. Therefore, with the output average current
known, the RMS current for each output winding can be
The only difference between a multiple output flyback power calculated as
supply and a single output flyback power supply of the same I
ISRMS ] n g = IO ] n g # SRMS
total output power is on the secondary side design. IO
Design with Lumped Output Power where ISRMS(n) and IO(n) are the secondary RMS current and
A simple multiple output flyback design is described in detail in output average current of the nth output, and ISRMS and IO are the
AN-22, “Designing Multiple Output Flyback Power Supplies with secondary RMS current and output average current for the
TOPSwitch.” The design method starts with a single output lumped single output equivalent design.
equivalent by lumping output power of all outputs to one main
output. Secondary peak current ISP and RMS current ISRMS are Customization of Secondary Designs for Each Output
derived. Output average current IO, corresponding to the The turns for each secondary winding are calculated based on
lumped power, is also calculated. the respective output voltage VO(n):
Assumption for Simplification
VO ] n g + V D ] n g
The current waveforms in the individual output windings are NS ] n g = NS #
determined by the impedance in each circuit, which is a V + VD
function of leakage inductance, rectifier characteristics,
Output rectifier maximum inverse voltage is
capacitor value and output load. Although this current wave-
form may not be exactly the same from output to output, it is
reasonable to assume that, to the first order, all output currents NS ] n g
PIVS ] n g = VMAX # N + VO ] n g
have the same shape as for the single output equivalent of P

combined circuit.
With output RMS current ISRMS(n), secondary number of turns
Output RMS Current vs. Average Current NS(n) and output rectifier maximum inverse voltage PIVS(n) known,
The output average current is always equal to the DC load the secondary side design for each output can now be carried
current, while the RMS value is determined by current wave out exactly the same way as for the single output design.

25
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 Application Note AN-43

Secondary Winding Wire Size

The TOPSwitch-HX design spreadsheet assumes a CMA of 200
when calculating secondary winding wire diameters. This gives
D V
the minimum wire sizes required for the RMS currents of each 22 7 - 150 7
R
CONTROL
output using separate windings. Designers may wish to use 1/2 W C
larger size wire for better thermal performance. Other
considerations, such as skin effect and bobbin coverage, may S X F
10 pF - 33 pF C
suggest the use of a smaller wire by using multiple strands 1 kV
RIL
wound in parallel. In addition, practical considerations in
transformer manufacturing may also dictate the wire size.
PI-5004-022908

Figure 27. Recommended Snubber for Larger (TOP259-TOP261)

TOPSwitch-HX Devices.

26
Rev. D 03/08 www.powerint.com
 AN-43 Application Note

Notes

27
www.powerint.com Rev. D 03/08
Revision Notes Date
A Initial Release 9/07
B Text changes 9/07
C Style, formatting and renumbering 10/07
D Added high-power TOPSwitch-HX information 03/08

For the latest updates, visit our website: www.powerint.com

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Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

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injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert
and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
©2007, Power Integrations, Inc.

Power Integrations Worldwide Sales Support Locations

World Headquarters Germany Japan Taiwan

5245 Hellyer Avenue Rueckertstrasse 3 Kosei Dai-3 Bldg. 5F, No. 318, Nei Hu Rd., Sec. 1
San Jose, CA 95138, USA. D-80336, Munich 2-12-11, Shin-Yokomana, Nei Hu Dist.
Main: +1-408-414-9200 Germany Kohoku-ku Taipei, Taiwan 114, R.O.C.
Customer Service: Phone: +49-89-5527-3910 Yokohama-shi Kanagwan Phone: +886-2-2659-4570
Phone: +1-408-414-9665 Fax: +49-89-5527-3920 222-0033 Japan Fax: +886-2-2659-4550
Fax: +1-408-414-9765 e-mail: eurosales@powerint.com Phone: +81-45-471-1021 e-mail: taiwansales@powerint.com
e-mail: usasales@powerint.com Fax: +81-45-471-3717
India e-mail: japansales@powerint.com Europe HQ
China (Shanghai) #1, 14th Main Road 1st Floor, St. James’s House
Rm 807-808A Vasanthanagar Korea East Street, Farnham
Pacheer Commercial Centre, Bangalore-560052 India RM 602, 6FL Surrey GU9 7TJ
555 Nanjing Rd. West Phone: +91-80-4113-8020 Korea City Air Terminal B/D, 159-6 United Kingdom
Shanghai, P.R.C. 200041 Fax: +91-80-4113-8023 Samsung-Dong, Kangnam-Gu, Phone: +44 (0) 1252-730-141
Phone: +86-21-6215-5548 e-mail: indiasales@powerint.com Seoul, 135-728, Korea Fax: +44 (0) 1252-727-689
Fax: +86-21-6215-2468 Phone: +82-2-2016-6610 e-mail: eurosales@powerint.com
e-mail: chinasales@powerint.com Italy Fax: +82-2-2016-6630
Via De Amicis 2 e-mail: koreasales@powerint.com Applications Hotline
China (Shenzhen) 20091 Bresso MI World Wide +1-408-414-9660
Rm A, B & C 4th Floor, Block C, Italy Singapore
Electronics Science and Phone: +39-028-928-6000 51 Newton Road Applications Fax
Technology Bldg., 2070 Fax: +39-028-928-6009 #15-08/10 Goldhill Plaza World Wide +1-408-414-9760
Shennan Zhong Rd, e-mail: eurosales@powerint.com Singapore, 308900
Shenzhen, Guangdong, Phone: +65-6358-2160
China, 518031 Fax: +65-6358-2015
Phone: +86-755-8379-3243 e-mail: singaporesales@powerint.com
Fax: +86-755-8379-5828
e-mail: chinasales@powerint.com