For Audio Equipment

MN6474A
D/A Converter for Digital Audio Equipment

Overview Pin Assignment

The MN6474A is a CMOS digital-to-analog converter
with a built-in 16-bit digital filter for pulse code
modulation (PCM) digital audio equipment.

ZFLGB

DVDD2

DVDD1
AVDD1
NSUB
DVSS2

DVSS1
192FS

N.C.
It uses noise shaping technology to convert a digital

X1
X2
signal into a PWM signal.
It contains a 4-fold oversampling digital filter that

32
31
30
29
28
27
26
25
24
23
22
LRPOL 33 21 OUTR(–)
permits simplification of the low pass filter after the D/A LRCLK 34 20 AVSS1
converter, thus greatly reducing the power consumption BCLK 35 19 AVSS2
of the entire D/A conversion system. SRDATA 36 18 OUTR(+)
DVSS3 37 17 AVDD2
The chip provides both regular and inverted phase DVDD 38 16 N.C.
outputs for both channels. 384FS 39 15 AVDD3
PD 40 14 OUTL(+)
The chip contributes to cost and size reductions for CD MDATA 41 13 AVSS3
players and other digital audio equipment. MCLK 42 12 AVSS4
11 OUTL(–)

10
1
2
3
4
5
6
7
8
9
Features
MLD
RSTB
IE
TP1
TP2
TEST1
TEST2
N.C.
N.C.
AVDD4
Built-in 4-fold oversampling digital filter
(ripple of only ±0.0072 dB within the supported
band and attenuation of 62.7 dB within the cutoff
band) (TOP VIEW)
Internal resolution of 18 bits
QFP042-P-1414A
Two's complement input (I2S input code also supported)
Built-in overflow limiter
No zero cross distortion
Sample-and-hold circuit is unnecessary
Output pin for detecting zero input
Single 5V power supply

Applications
CD players and other digital audio equipment
MN6474A For Audio Equipment

Block Diagram

ZFLGB
TEST2
TEST1

384FS

192FS
TP2
TP1

X1

X2
7
6
5
4
31

39

32

26

25
Timing Generator

33
LRPOL
34
LRCLK
35 S/P 21
BCLK FIR 1 FIR 2 PWM Analog OUTR(–)
36 Converter
SRDATA Logics Block
18
3 (R) (R) OUTR(+)
IE Noise
Shaping
Logics
14
PWM Analog OUTL(+)
Logics Block
11
Microcomputer Interface (L) (L) OUTL(–)
40
41
42
1
PD
MDATA
MCLK
MLD
For Audio Equipment MN6474A

Pin Descriptions
Pin No. Symbol Function Description
1 MLD Microcomputer command load input ("L" level to load)
2 RSTB Reset pin (active "L").
Always pull this pin low after applying the power.
3 IE Input format selection pin. "H" level; I 2S format
"L" level; signal processing LSI format.
4 TP1 Digital filter test output pin 1. Leave this pin open.
5 TP2 Digital filter test output pin 2. Leave this pin open.
6 TEST1 Digital filter test input pin 1. Keep this pin at "L" level.
7 TEST2 Digital filter test input pin 2. Keep this pin at "L" level.
8 N.C. No connection Leave these pins open.
9 N.C. No connection Leave these pins open.
10 AV DD4 Power supply pin 4 for analog circuits. (+5V)
11 OUTL(–) Left channel inverted phase PWM output pin.
12 AV SS4 Ground pin 4 for analog circuits.
13 AV SS3 Ground pin 3 for analog circuits.
14 OUTL(+) Left channel normal phase PWM output pin.
15 AV DD3 Power supply pin 3 for analog circuits. (+5V)
16 N.C. No connection Leave this pin open.
17 AV DD2 Power supply pin 2 for analog circuits. (+5V)
18 OUTR(+) Right channel through phase PWM output pin.
19 AV SS2 Ground pin 2 for analog circuits.
20 AV SS1 Ground pin 1 for analog circuits.
21 OUTR(–) Right channel inverted phase PWM output pin.
22 AV DD1 Power supply pin 1 for analog circuits. (+5V)
23 DV DD1 Power supply pin 1 for digital circuits. (+5V) (Power supply for oscillator circuit)
24 DV SS1 Ground pin 1 for digital circuits. (Ground for oscillator circuit)
25 X2 Crystal oscillator pin.
26 X1 Crystal oscillator pin. (External clock input pin)
27 N.C. No connection Leave this pin open.
28 DV DD2 Power supply pin 2 for analog circuits. (+5V)
29 DV SS2 Ground pin 2 for digital circuits.
30 NSUB Connect to D-VDD. (Silicon substrate potential fixing pin)
31 ZFLGB Output pin for detecting zero input.
32 192FS 192fs(=9.216 MHz)output pin. Max. load capacity: 30 pF.
33 LRPOL LRCLK polarity selection pin. "H" level; selects the left channel
"L" level; the right channel.
34 LRCLK LRCLK pin. When the LRPOL pin is at "H" level, "H" level in this pin indicates left
channel data input; "L" level indicates right channel data input. When the LRPOL pin
is at "L" level, "L" level in this pin indicates left channel data input; "H" level input
indicates right channel data input.
35 BCLK Serial input bit clock
36 SRDATA Serial input data (digital) input pin.
37 DV SS3 Ground pin 3 for digital circuits.
MN6474A For Audio Equipment

Pin Descriptions (continued)

Pin No. Symbol Function Description
38 DVDD Power supply pin for digital circuits. (Silicon substrate potential fixing pin.) (+5V)
39 384FS 384fs (=18.432 MHz) output pin. Max. load capacitance: 30 pF.
40 PD Power down pin. (active "H")
41 MDATA Microcomputer command data input pin.
42 MCLK Clock input pin for microcomputer command.

Conversion Characteristics
DV DD=5.0V, DVSS=0V, AVDD=5.0V, AVSS=0V, f=33.8688MHz, Ta=25˚C
Parameter Symbol Test Conditions min typ max Unit
Analog characteristics
Signal-to-noise ratio S/N EIAJ (1kHz) 95 106 dB
Dynamic range D.R. EIAJ (1kHz) 90 98 dB
Total harmonic distortion THD+N EIAJ (1kHz) 0.003 0.005 %
Crosstalk EIAJ (1kHz) 90 98 dB
Output level *1 1kHz F.S. 1.4 1.7 Vrms
Note*1: These analog characteristics are for circuits equivalent to the suggested application circuit.
 DVSS DVDD AVDD AVSS –15 E 15

R1 *C1
10W 100µF
+
7th order L.P.F(HAF 0079)
C14 47µF

R3 330W
1 2 3 4 5 6 7 8 9 10
+

R4 330W
R5 1kW
R7 1kW
R32

C4
C15 47µF

R6 1kW
R8 1kW
470W R23

C3 5pF
+ 22W
For Audio Equipment

C28

*C5 10µF
*C6 0.56µF

MHz
+ 220µF
+

33.8688
5pF R24.7kW
C10 + + C13 C26 2200pF
Application Circuit Example

22µF + + 22µF C22

32
31
30
29
28
27
26
25
24
23
22
C11 C12 47pF R19

X1
X2
22µF 22µF R17 220W N

N.C.
R9

192fs
NSUB
DVSS2
DVSS1
47kW

DVDD2
DVDD1
AVDD1
10µF R34

ZFLGB
R32 OUTR(–) 21 R13 47kW
470W 47pF 33kW C24 470kW R27
33 LRPOL AVSS1 20 C16 N 330W R ch
34 LRCLK AVSS2 19 R24 C29 C32
C17 47pF 8 – + 8 – + 22W 220µF 10µF C34 R29
35 BCLK OUTR(+) 18 + 330pF 100kW
C7 R10 IC4 +
36 SRDATA AVDD2 17 + 47kW C35
C2 1 – + 1 – + R26 R30
37 DVSS3 MN6474A N.C. 16 330µF 330pF 100kW
470W IC2 22W C31
+ R11
38 DVDD AVDD3 15 220µF
R33 100µF 47kW N R28
39 384FS OUTL(+) 14 + R14 33kW C20 47pF L ch
C27 2200pF C33 330W
40 PD 13 C8 C18 R21 10µF
AVSS3
330µF 47pF 47pF
47kW C23 R20
41 MDATA AVSS4 12 R35
C19 47pF 220W N 470kW
42 MCLK OUTL(–) 11 R15
R12 33kW R18 47kW 10µF
47kW C25 + C32
R25
22W 220µF

MLD 1
RSTB 2
IE 3
TP1 4
TP2 5
TEST1 6
TEST2 7
N.C. 8
N.C. 9
AVDD4 10
*C9
0.56µF 8 – + 8 – +
IC1 IC3
1 – + 1 – + 1 2 3 4 5 6 7 8 9 10
S2 S3 S1 S4 S5 S6
7th order L.P.F(HAF 0079)
VDD C21
VSS R16 47pF
33kW
R22
*C1,C5,C6 and C9 are attached to the rear of the P base. 47kW
IC1 to 4
AN6558
PD(S3) RSTB(S1) IE(S4)

– Signal processing
"L" Reset
LSI format

Power –
"H" I2S format
down mode
MN6474A
MN6474A For Audio Equipment

Package Dmensions (Unit: mm)

QFP042-P-1414A

18.7±0.4
14.0±0.2

32 22

21
33

(0.65)
14.0±0.2
18.7±0.4
42
11

1 10
2.6max.

(1.92) 1.27 0.4±0.1 (2.35)

2.2±0.2

0.15 -0.05
+0.10

0 to 10°
0.1±0.1

0.15 (1.5±0.2)

SEATING PLANE