MCT8315Z

SLVSH53 – DECEMBER 2023

MCT8315Z Sensored Trapezoidal Integrated FET BLDC Motor Driver

1 Features 3 Description
• Three-phase BLDC motor driver with integrated The MCT8315Z provides a single-chip, code-
Sensored Trapezoidal control free sensored trapezoidal solution for customers
– Hall sensor based trapezoidal (120°) driving 12-V/24-V brushless-DC motors; no external
commutation microcontroller is needed to spin the BLDC motor.
– Supports analog or digital hall inputs The MCT8315Z integrates three ½ -bridges with 40-
– Configurable PWM modulation: synchronous/ V absolute maximum capability and a low RDS(ON)
asynchronous of 275 mΩ (HS+ LS) to enable high power drive
– Cycle-by-cycle current limit to limit phase capability. The integrated current limiting feature
current limits motor currents during start-up or high load
– Supports up to 200-kHz PWM frequency conditions while eliminating the need for external
– Active demagnetization to reduce power losses sense resistors. MCT8315Z provides an output
• 4.5-V to 35-V operating voltage (40-V abs max) voltage adjustable buck regulator and an LDO that
• High output current capability: 4-A Peak can be used to power external circuits. MCT8315Z
• Low MOSFET on-state resistance integrates three analog hall comparators for position
– 275-mΩ (typ.) RDS(ON) (HS + LS) at TA = 25°C sensing to achieve sensored trapezoidal BLDC motor
• Low power sleep mode control. The control scheme is highly configurable
– 2.5-µA (max.) at VVM = 24-V, TA = 25°C through hardware pins or register settings ranging
• Integrated current limiting eliminates external from motor current limiting behavior to advance angle.
current sense resistors The speed can be controlled through a PWM input.
• Flexible device configuration options A number of protection features including supply
– MCT8315ZR: 5-MHz 16-bit SPI interface for undervoltage lockout (UVLO), overvoltage protection
device configuration and fault status (OVP), charge pump undervoltage (CPUV),
– MCT8315ZH: Hardware pin based overcurrent protection (OCP), over-temperature
configuration with buck warning (OTW) and over-temperature shutdown
– MCT8315ZT: Hardware pin based configuration (TSD) are integrated into MCT8315Z to protect the
without buck device, motor, and system against fault events. Fault
• Supports 1.8-V, 3.3-V and 5-V logic inputs conditions are indicated by the nFAULT pin.
• Built-in 3.3-V/5-V, 200-mA buck regulator
Refer Application Information for design consideration
• Built-in 3.3-V, 30-mA LDO regulator
and recommendation on device usage.
• Delay compensation reduces duty cycle distortion
• Suite of integrated protection features Package Information
– Supply undervoltage lockout (UVLO) PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
– Charge pump undervoltage (CPUV) MCT8315ZR(3) WQFN (32) 6 mm x 4 mm
– Overcurrent protection (OCP) MCT8315ZH WQFN (32) 6 mm x 4 mm
– Motor lock protection MCT8315ZT(3) WQFN (32) 6 mm x 4 mm
– Thermal warning and shutdown (OTW/TSD)
– Fault condition indication pin (nFAULT) (1) For more information, see Section 13.
– Optional fault diagnostics over SPI interface (2) The package size (length × width) is a nominal value and
includes pins, where applicable.
2 Applications (3) Device available for preview only.

• Brushless-DC (BLDC) Motor Modules

LDO out
3.3-V, up to 30-mA

Buck out 4.5V to 35V (40V abs max) 4-A peak output current,
• CPAP machines 3.3 or 5.0-V, up to 200-mA
typically 12- to 24-V,
MCT8315Z
• Printers
A Buck/LDO out
SPEED
PWM input
DIRECTION Sensored H
• Robotic vacuums Trap B
MOSFETs

BRAKE Control H
FGOUT
• Small home appliances Speed feedback

nFAULT Buck/LDO Regulator

C
H

• Office automation machines SPI

Only on SPI
variant Integrated Current Sensing Hall inputs support:
Differen al Hall elements

• Factory automation and robotics Differen al analog output Hall-effect sensors

Digital output Hall-effect sensors
Single-ended analog output Hall-effect sensors

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.5 SPI Communication.................................................. 60
2 Applications..................................................................... 1 8.6 Register Map.............................................................63
3 Description.......................................................................1 9 Application and Implementation.................................. 79
4 Revision History.............................................................. 2 9.1 Application Information............................................. 79
5 Device Comparison Table ..............................................3 9.2 Hall Sensor Configuration and Connection...............80
6 Pin Configuration and Functions...................................4 9.3 Typical Applications.................................................. 84
7 Specifications.................................................................. 7 10 Power Supply Recommendations..............................89
7.1 Absolute Maximum Ratings........................................ 7 10.1 Bulk Capacitance.................................................... 89
7.2 ESD Ratings............................................................... 7 11 Layout........................................................................... 90
7.3 Recommended Operating Conditions.........................7 11.1 Layout Guidelines................................................... 90
7.4 Thermal Information....................................................8 11.2 Layout Example...................................................... 91
7.5 Electrical Characteristics.............................................8 11.3 Thermal Considerations.......................................... 92
7.6 SPI Timing Requirements......................................... 15 12 Device and Documentation Support..........................93
7.7 SPI Secondary Device Mode Timings.......................15 12.1 Documentation Support.......................................... 93
7.8 Typical Characteristics.............................................. 16 12.2 Support Resources................................................. 93
8 Detailed Description......................................................17 12.3 Trademarks............................................................. 93
8.1 Overview................................................................... 17 12.4 Electrostatic Discharge Caution..............................93
8.2 Functional Block Diagram......................................... 18 12.5 Glossary..................................................................93
8.3 Feature Description...................................................21 13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes..........................................59 Information.................................................................... 93

4 Revision History
DATE REVISION NOTES
December 2023 * Initial release.

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5 Device Comparison Table

Note
MCT8315ZR and MCT8315ZT variants are preview only, in pre-production status

DEVICE PACKAGES INTERFACE BUCK REGULATOR

MCT8315ZR SPI
Yes
MCT8315ZH 32-pin WQFN (6x4 mm) Hardware
MCT8315ZT Hardware No

Table 5-1. MCT8315ZR vs MCT8315ZH vs MCT8315ZT configuration comparison

Parameters MCT8315ZR (SPI variant) MCT8315ZH(Hardware variant) MCT8315ZT(Hardware variant,
no buck)
PWM control mode settings PWM_MODE (4 settings) MODE pin (7 settings) MODE pin (7 settings)
Slew rate settings SLEW (4 settings) SLEW pin (4 settings) SLEW pin (4 settings)
Direction settings DIR (2 settings) DIR pin (2 settings) DIR pin (2 settings)
DRVOFF pin configuration DRV_OFF (2 settings) Enabled Enabled
Current limit threshold ILIM pin: (AVDD/2 to AVDD/ ILIM pin: (AVDD/2 to AVDD/ ILIM pin: (AVDD/2 to AVDD/
2-0.32)V 2-0.32)V 2-0.32)V
Current limit configuration ILIM_RECIR (2 settings), Recirculation fixed to Brake mode Recirculation fixed to Brake mode
PWM_100_DUTY_SEL and PWM frequency for 100% and PWM frequency for 100%
duty fixed to 20 kHz duty fixed to 20 kHz
Lead angle ADVANCE_LVL (8 settings) ADVANCE pin (7 settings) ADVANCE pin (7 settings)
Buck enable BUCK_DIS (2 settings) Enabled N/A
Buck output BUCK_SEL (4 settings) Always set to 5-V N/A
Buck configuration: power BUCK_PS_DIS (2 settings) and Power sequencing enabled, N/A
sequencing, current limit BUCK_CL(2 settings) current limit: 600 mA
FGOUT configuration FGOUT_SEL (4 settings) Fixed to 3x commutation Fixed to 3x commutation
frequency frequency
Motor lock configuration: mode, MTR_LOCK_MODE (4 settings), Enabled with 500-ms automatic Enabled with 500-ms automatic
detection and retry timing MTR_LOCK_TDET (4 settings), retry time and detection time of retry time and detection time of
MTR_LOCK_RETRY (2 settings) 1000-ms 1000-ms
Active demagnetization EN_AAR (2 settings) and MODE pin (7 settings) MODE pin (7 settings)
EN_ASR (2 settings)
OCP configuration: Mode, level, OCP_MODE (2 Enabled with latched shutdown Enabled with latched shutdown
deglitch time and retry time settings) , OCP_LVL (2 mode, level is fixed to 9-A with mode, level is fixed to 9-A with
settings) ,OCP_DEG (4 settings) 0.6-µs deglitch time 0.6-µs deglitch time
and OCP_RETRY (2 settings)
Overvoltage protection OVP_EN (2 settings) , OVP_SEL Enabled and level is fixed to 34-V Enabled and level is fixed to 34-V
configuration (2 settings) (typ) (typ)
Driver delay compensation DLYCMP_EN (2 settings), Disabled Disabled
configuration DLY_TARGET (16 settings)
SDO pin configuration SDO_MODE (2 settings) N/A N/A

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6 Pin Configuration and Functions

ADVANCE
BRAKE

SCLK
nSCS
PWM

BRAKE
ILIM

SDI

SLEW
PWM

ILIM

DIR
30

27
32

31

29

28

32

31

30

29

28

27
FGOUT 1 26 SDO
FGOUT 1 26 MODE
FB_BK 2 25 HNC
FB_BK 2 25 HNC
GND_BK 3 24 HPC
GND_BK 3 24 HPC
SW_BK 4 23 HNB
SW_BK 4 23 HNB
CPL 5 22 HPB
CPL 5 22 HPB
CPH 6 21 HNA
CPH 6 21 HNA
CP 7 20 HPA
CP 7 20 HPA
VM 8 19 AVDD
VM 8 19 AVDD
VM 9 18 AGND
Thermal Pad VM 18 AGND
9
Thermal Pad
PGND 10 17 nSLEEP
PGND 10 17 nSLEEP
11

12

13

14

15

16

15
11

12

13

14

16
OUTB
OUTA

PGND

DRVOFF
OUTC

nFAULT

OUTB
OUTA

PGND

DRVOFF
OUTC

nFAULT
Figure 6-1. MCT8315ZR 32-Pin WQFN With
Exposed Thermal Pad Top View Figure 6-2. MCT8315ZH 32-Pin WQFN With
Exposed Thermal Pad Top View
ADVANCE
BRAKE

SLEW
PWM

ILIM

DIR
31
32

30

29

27
28

FGOUT 1 26 MODE

NC 2 25 HNC

NC 3 24 HPC

NC 4 23 HNB

CPL 5 22 HPB

CPH 6 21 HNA

CP 7 20 HPA

VM 8 19 AVDD

VM 9 18 AGND
Thermal Pad

PGND 10 17 nSLEEP
11

12

13

14

15

16
OUTB
OUTA

PGND

DRVOFF
OUTC

nFAULT

Figure 6-3. MCT8315ZT 32-Pin WQFN With Exposed Thermal Pad Top View

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Table 6-1. Pin Functions

PIN 32-pin package
TYPE(1) DESCRIPTION
NAME MCT8315ZR MCT8315ZH MCT8315ZT
Advance angle level setting. This pin is a 7-level input pin set
ADVANCE — 28 28 I
by an external resistor.
Device analog ground. Refer Section 11.1 for connections
AGND 18 18 18 GND
recommendation.
3.3-V internal regulator output. Connect an X5R or X7R, 1-µF,
AVDD 19 19 19 PWR O 6.3-V ceramic capacitor between the AVDD and AGND pins.
This regulator can source up to 30 mA externally.
High → Brake the motor by turning all low side MOSFETs ON
BRAKE 31 31 31 I
Low → normal operation
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V
CP 7 7 7 PWR O
ceramic capacitor between the CP and VM pins.
CPH 6 6 6 PWR Charge pump switching node. Connect a X5R or X7R, 47-
nF, ceramic capacitor between the CPH and CPL pins. TI
CPL 5 5 5 PWR recommends a capacitor voltage rating at least twice the
normal operating voltage of the device.
Direction pin for setting the direction of the motor rotation to
DIR — 29 29 I
clockwise or counterclockwise.
When this pin is pulled high, the six MOSFETs in the power
DRVOFF 15 15 15 I
stage are turned OFF making all outputs Hi-Z.
Feedback for buck regulator. Connect to buck regulator output
FB_BK 2 2 — PWR I
after the inductor/resistor.
Motor speed indicator output. Open-drain output requires an
FGOUT 1 1 1 O external pull-up resistor to 3.3-V to 5-V. It can be set to
different division factor of Hall signals (see Section 8.3.15)
Buck regulator ground. Refer Section 11.1 for connections
GND_BK 3 3 3 GND
recommendation.
Phase A hall element positive input. Noise filter capacitors
HPA 20 20 20 I may be desirable, connected between the positive and
negative hall inputs.
Phase B hall element positive input. Noise filter capacitors
HPB 22 22 22 I may be desirable, connected between the positive and
negative hall inputs.
Phase C hall element positive input. Noise filter capacitors
HPC 24 24 24 I may be desirable, connected between the positive and
negative hall inputs.
Phase A hall element negative input. Noise filter capacitors
HNA 21 21 21 I may be desirable, connected between the positive and
negative hall inputs.
Phase B hall element negative input. Noise filter capacitors
HNB 23 23 23 I may be desirable, connected between the positive and
negative hall inputs.
Phase C hall element negative input. Noise filter capacitors
HNC 25 25 25 I may be desirable, connected between the positive and
negative hall inputs.
Set the threshold for phase current used in cycle by cycle
ILIM 30 30 30 I
current limit.
PWM input mode setting. This pin is a 7-level input pin set by
MODE — 26 26 I
an external resistor.
Pins 2, 4: No connection, open
NC — — 2, 3, 4 —
Pin 3: Tie to PGND
Fault indicator. Pulled logic-low with fault condition; Open-
drain output requires an external pull-up resistor to 3.3-V to
nFAULT 16 16 16 O 5-V. If external supply is used to pull-up nFAULT, make sure
that it is pulled to >2.2-V on power up, or the device may
enter test mode.

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Table 6-1. Pin Functions (continued)

PIN 32-pin package
TYPE(1) DESCRIPTION
NAME MCT8315ZR MCT8315ZH MCT8315ZT
Serial chip select. A logic low on this pin enables serial
nSCS 29 — — I
interface communication.
Driver nSLEEP. When this pin is logic low, the device goes
nSLEEP 17 17 17 I into a low-power sleep mode. An 20 to 40-µs low pulse can
be used to reset fault conditions without entering sleep mode.
OUTA 11 11 11 PWR O Half-bridge output A
OUTB 12 12 12 PWR O Half-bridge output B
OUTC 13 13 13 PWR O Half-bridge output C
Device power ground. Refer Section 11.1 for connections
PGND 10, 14 10, 14 10, 14 GND
recommendation.
PWM input for motor control. Set the duty cycle and switching
PWM 32 32 32 I
frequency of the phase voltage of the motor.
Serial clock input. Serial data is shifted out and captured on
SCLK 28 — — I the corresponding rising and falling edge on this pin (SPI
devices).
Serial data input. Data is captured on the falling edge of the
SDI 27 — — I
SCLK pin (SPI devices).
Serial data output. Data is shifted out on the rising edge of the
SDO 26 — — O SCLK pin. This pin requires an external pullup resistor (SPI
devices).
Slew rate control setting. This pin is a 4-level input pin set by
SLEW — 27 27 I
an external resistor (Hardware devices).
SW_BK 4 4 — PWR O Buck switch node. Connect this pin to an inductor or resistor.
Power supply. Connect to motor supply voltage; bypass to
PGND with two 0.1-µF capacitors (for each pin) plus one bulk
VM 8, 9 8, 9 8, 9 PWR I capacitor rated for VM. TI recommends a capacitor voltage
rating at least twice the normal operating voltage of the
device.
Thermal
GND Must be connected to AGND
pad

(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect

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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply pin voltage (VM) –0.3 40 V
Power supply voltage ramp (VM) 4 V/µs
Voltage difference between ground pins (GND_BK, PGND, AGND) –0.3 0.3 V
Charge pump voltage (CPH, CP) –0.3 VM + 6 V
Charge pump negative switching pin voltage (CPL) –0.3 VM + 0.3 V
Switching regulator pin voltage (FB_BK) –0.3 6 V
Switching node pin voltage (SW_BK) –0.3 VM + 0.3 V
Analog regulator pin voltage (AVDD) –0.3 4 V
Logic pin input voltage (BRAKE, DIR, DRVOFF, PWM, nSCS, nSLEEP, SCLK, SDI) –0.3 5.75 V
Logic pin output voltage (nFAULT, SDO) –0.3 5.75 V
Output pin voltage (OUTA, OUTB, OUTC) –1 VM + 1 V
Ambient temperature, TA –40 125 °C
Junction temperature, TJ –40 150 °C
Storage tempertaure, Tstg –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE UNIT

Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

V(ESD) V
discharge Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VVM Power supply voltage VVM 4.5 24 35 V
fPWM Output PWM frequency OUTA, OUTB, OUTC 200 kHz
IOUT (1) Peak output winding current OUTA, OUTB, OUTC 4 A
BRAKE, DIR, DRVOFF, PWM, nSCS,
VIN Logic input voltage –0.1 5.5 V
nSLEEP, SCLK, SDI
VOD Open drain pullup voltage nFAULT, SDO, FGOUT –0.1 5.5 V
VSDO Push-pull voltage SDO 2.2 5.5 V
IOD Open drain output current nFAULT, SDO, FGOUT 5 mA
TA Operating ambient temperature –40 125 °C
TJ Operating junction temperature –40 150 °C

(1) Power dissipation and thermal limits must be observed

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7.4 Thermal Information

MCT8315ZR,
MCT8315ZT, MCT8315ZH
THERMAL METRIC(1) UNIT
WQFN (RRY)
32 Pins
RθJA Junction-to-ambient thermal resistance 30.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 19.4 °C/W
RθJB Junction-to-board thermal resistance 9.0 °C/W
ΨJT Junction-to-top characterization parameter 0.3 °C/W
ΨJB Junction-to-board characterization parameter 9.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Electrical Characteristics

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
VVM > 6 V, nSLEEP = 0, TA = 25 °C 1.5 2.5 µA
IVMQ VM sleep mode current
nSLEEP = 0 2.5 5 µA
nSLEEP = 1, PWM = 0, SPI =
4 10 mA
VM standby mode current 'OFF', BUCK_DIS = 1;
IVMS
(Buck regulator disabled) VVM > 6 V, nSLEEP = 1, PWM = 0, SPI =
4 5 mA
'OFF', TA = 25 °C, BUCK_DIS = 1;
VVM > 6 V, nSLEEP = 1, PWM = 0, SPI =
'OFF', IBK = 0, TA = 25 °C, BUCK_DIS = 5 6.5 mA
VM standby mode current 0;
IVMS
(Buck regulator enabled)
nSLEEP = 1, PWM= 0, SPI = 'OFF', IBK
6 10 mA
= 0, BUCK_DIS = 0;
VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz,
10 13 mA
TA = 25 °C, BUCK_DIS = 1
VVM > 6 V, nSLEEP = 1, fPWM = 200 kHz,
18 21 mA
VM operating mode current TA = 25 °C, BUCK_DIS = 1
IVM
(Buck regulator disabled) nSLEEP =1, fPWM = 25 kHz, BUCK_DIS
11 15 mA
=1
nSLEEP =1, fPWM = 200 kHz,
17 24 mA
BUCK_DIS = 1
VVM > 6 V, nSLEEP = 1, fPWM =
25 kHz, TA = 25 °C, BUCK_DIS = 11 13 mA
0; BUCK_PS_DIS = 0
VVM > 6 V, nSLEEP = 1, fPWM =
VM operating mode current 200 kHz, TA = 25 °C, BUCK_DIS = 19 22 mA
IVM 0; BUCK_PS_DIS = 0
(Buck regulator enabled)
nSLEEP =1, fPWM = 25 kHz, BUCK_DIS
12 16 mA
= 0; BUCK_PS_DIS = 0
nSLEEP =1, fPWM = 200 kHz,
18 27 mA
BUCK_DIS = 0; BUCK_PS_DIS = 0
VAVDD Analog regulator voltage 0 mA ≤ IAVDD ≤ 30 mA 3.1 3.3 3.465 V
IAVDD External analog regulator load 30 mA
VVCP Charge pump regulator voltage VCP with respect to VM 3.6 4.7 5.2 V
VVM > VUVLO, nSLEEP = 1 to outputs
tWAKE Wakeup time 1 ms
ready and nFAULT released

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7.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSLEEP Sleep Pulse time nSLEEP = 0 period to enter sleep mode 120 µs
tRST Reset Pulse time nSLEEP = 0 period to reset faults 20 40 µs
BUCK REGULATOR
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
3.1 3.3 3.5 V
BUCK_SEL = 00b
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
4.6 5.0 5.4 V
BUCK_SEL = 01b
Buck regulator average voltage VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
3.7 4.0 4.3 V
VBK (LBK = 47 µH, CBK = 22 µF) BUCK_SEL = 10b
(SPI Device)
VVM > 6.7 V, 0 mA ≤ IBK ≤ 200 mA,
5.2 5.7 5.8 V
BUCK_SEL = 11b
VVM–
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
IBK*(RLBK+ V
10b. 11b), 0 mA ≤ IBK ≤ 200 mA
2)(1)
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
3.1 3.3 3.5 V
BUCK_SEL = 00b
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
4.6 5.0 5.4 V
BUCK_SEL = 01b
Buck regulator average voltage VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
3.7 4.0 4.3 V
VBK (LBK = 22 µH, CBK = 22 µF) BUCK_SEL = 10b
(SPI Device)
VVM > 6.7 V, 0 mA ≤ IBK ≤ 50 mA,
5.2 5.7 5.8 V
BUCK_SEL = 11b
VVM–
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
IBK*(RLBK+ V
10b, 11b), 0 mA ≤ IBK ≤ 50 mA
2) (1)
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
3.1 3.3 3.5 V
BUCK_SEL = 00b
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
4.6 5.0 5.4 V
BUCK_SEL = 01b
Buck regulator average voltage VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
3.7 4.0 4.3 V
VBK (RBK = 22 Ω, CBK = 22 µF) BUCK_SEL = 10b
(SPI Device)
VVM > 6.7 V, 0 mA ≤ IBK ≤ 40 mA,
5.2 5.7 5.8 V
BUCK_SEL = 11b
VVM–
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
IBK*(RBK+2 V
10b, 11b), 0 mA ≤ IBK ≤ 40 mA
)(1)
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA 4.6 5.0 5.4
Buck regulator average voltage
VBK (LBK = 47 µH, CBK = 22 µF) VVM–
(HW Device) VVM < 6.0 V, 0 mA ≤ IBK ≤ 200 mA IBK*(RLBK+ V
2)(1)
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA 4.6 5.0 5.4 V
Buck regulator average voltage
VBK (LBK = 22 µH, CBK = 22 µF) VVM–
(HW Device) VVM < 6.0 V, 0 mA ≤ IBK ≤ 50 mA IBK*(RLBK+ V
2)(1)
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA 4.6 5.0 5.4 V
Buck regulator average voltage
VBK (RBK = 22 Ω, CBK = 22 µF) VVM–
(HW Device) VVM < 6.0 V, 0 mA ≤ IBK ≤ 40 mA IBK*(RBK+2 V
)(1)

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7.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, Buck
regulator with inductor, LBK = 47 uH, CBK –100 100 mV
= 22 µF
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck
VBK_RIP Buck regulator ripple voltage regulator with inductor, LBK = 22 uH, CBK –100 100 mV
= 22 µF
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck
regulator with resistor; RBK = 22 Ω, CBK –100 100 mV
= 22 µF
LBK = 47 uH, CBK = 22 µF,
200 mA
BUCK_PS_DIS = 1b
LBK = 47 uH, CBK = 22 µF, 200 –
mA
BUCK_PS_DIS = 0b IAVDD
LBK = 22 uH, CBK =
50 mA
22 µF, BUCK_PS_DIS = 1b
IBK External buck regulator load
LBK = 22 uH, CBK = 22 µF, 50 –
mA
BUCK_PS_DIS = 0b IAVDD
RBK = 22 Ω, CBK =
40 mA
22 µF, BUCK_PS_DIS = 1b
RBK = 22 Ω, CBK = 22 µF, 40 –
mA
BUCK_PS_DIS = 0b IAVDD
Regulation Mode 20 535 kHz
fSW_BK Buck regulator switching frequency
Linear Mode 20 535 kHz
VBK rising, BUCK_SEL = 00b 2.7 2.8 2.9 V
VBK falling, BUCK_SEL = 00b 2.5 2.6 2.7 V
VBK rising, BUCK_SEL = 01b 4.2 4.4 4.55 V

Buck regulator undervoltage lockout VBK falling, BUCK_SEL = 01b 4.0 4.2 4.35 V
VBK_UV
(SPI Device) VBK rising, BUCK_SEL = 10b 2.7 2.8 2.9 V
VBK falling, BUCK_SEL = 10b 2.5 2.6 2.7 V
VBK rising, BUCK_SEL = 11b 4.2 4.4 4.55 V
VBK falling, BUCK_SEL = 11b 4 4.2 4.35 V
Buck regulator undervoltage lockout
VBK_UV VBK rising 4.2 4.4 4.55 V
(HW Device)
Buck regulator undervoltage lockout
VBK_UV VBK falling 4.0 4.2 4.35 V
(HW Device)
Buck regulator undervoltage lockout
VBK_UV_HYS Rising to falling threshold 90 200 320 mV
hysteresis

Buck regulator current limit threshold BUCK_CL = 0b 360 600 900 mA

IBK_CL
(SPI Device) BUCK_CL = 1b 80 150 250 mA
Buck regulator current limit threshold
IBK_CL 360 600 900 mA
(HW Device)
Buck regulator overcurrent protection trip
IBK_OCP 1.6 2.1 3 A
point
tBK_RETRY Overcurrent protection retry time 0.7 1 1.3 ms
LOGIC-LEVEL INPUTS (BRAKE, DIR, DRVOFF, nSLEEP, PWM, SCLK, SDI)
VIL Input logic low voltage 0 0.6 V
Other Pins 1.5 5.5 V
VIH Input logic high voltage
nSLEEP 1.6 5.5 V

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7.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Other Pins 180 300 420 mV
VHYS Input logic hysteresis
nSLEEP 95 250 420 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V –1.6 1 µA
nSLEEP, VPIN (Pin Voltage) = 5 V 10 30 µA
IIH Input logic high current
Other pins, VPIN (Pin Voltage) = 5 V 30 75 µA
nSLEEP 150 200 425 kΩ
RPD Input pulldown resistance
Other pins 70 100 130 kΩ
CID Input capacitance 30 pF
LOGIC-LEVEL INPUTS (nSCS)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 180 300 420 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V 75 µA
IIH Input logic high current VPIN (Pin Voltage) = 5 V –1 66 µA
RPU Input pullup resistance 80 100 130 kΩ
CID Input capacitance 30 pF
FOUR-LEVEL INPUTS (SLEW)
0.2*AVD
VL1 Input mode 1 voltage Tied to AGND 0 V
D
0.27*AV 0.52*AV
VL2 Input mode 2 voltage Hi-Z 0.5*AVDD V
DD DD
0.62*AV 0.88*AV
VL3 Input mode 3 voltage 47 kΩ +/- 5% tied to AVDD 0.75*AVDD V
DD DD
0.97*AV
VL4 Input mode 4 voltage Tied to AVDD AVDD V
DD
RPU Input pullup resistance To AVDD 70 100 130 kΩ
RPD Input pulldown resistance To AGND 70 100 130 kΩ
SEVEN-LEVEL INPUTS (ADVANCE, MODE)
0.06*AV
VL1 Input mode 1 voltage Tied to AGND 0 V
DD
0.13*AV 0.2*AVD
VL2 Input mode 2 voltage 22 kΩ ± 5% to AGND 0.15*AVDD V
DD D
0.27*AV 0.38*AV
VL3 Input mode 3 voltage 100 kΩ ± 5% to AGND 0.33*AVDD V
DD DD
0.47*AV 0.52*AV
VL4 Input mode 4 voltage Hi-Z 0.5*AVDD V
DD DD
0.62*AV 0.7*AVD
VL5 Input mode 5 voltage 100 kΩ ± 5% to AVDD 0.66*AVDD V
DD D
0.8*AVD 0.88*AV
VL6 Input mode 6 voltage 22 kΩ ± 5% to AVDD 0.84*AVDD V
D DD
0.97*AV
VL7 Input mode 7 voltage Tied to AVDD AVDD V
DD
RPU Input pullup resistance To AVDD 80 100 120 kΩ
RPD Input pulldown resistance To AGND 80 100 120 kΩ
OPEN-DRAIN OUTPUTS (FGOUT, nFAULT)
VOL Output logic low voltage IOD = 5 mA 0.4 V
IOH Output logic high current VOD = 5 V –1 1 µA

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7.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COD Output capacitance 30 pF
PUSH-PULL OUTPUTS (SDO)
VOL Output logic low voltage IOP = 5 mA 0 0.4 V
VOH Output logic high voltage IOP = 5 mA 2.2 5.5 V
IOL Output logic low leakage current VOP = 0 V –1 1 µA
IOH Output logic high leakage current VOP = 5 V –1 1 µA
COD Output capacitance 30 pF
DRIVER OUTPUTS
VVM > 6 V, IOUT = 1 A, TA = 25°C 275 295 mΩ

Total MOSFET on resistance (High-side VVM < 6 V, IOUT = 1 A, TA = 25°C 285 305 mΩ
RDS(ON)
+ Low-side) VVM > 6 V, IOUT = 1 A, TJ = 150 °C 415 455 mΩ
VVM < 6 V, IOUT = 1 A, TJ = 150 °C 425 465 mΩ
VVM = 24 V, SLEW = 00b or SLEW pin
15 25 45 V/us
tied to AGND
VVM = 24 V, SLEW = 01b or SLEW pin in
Phase pin slew rate switching low to high Hi-Z 30 50 80 V/us
SR (Rising from 20 % to 80 %)
VVM = 24 V, SLEW = 10b or SLEW pin to
80 125 210 V/us
47 kΩ +/- 5% to AVDD
VVM = 24 V, SLEW = 11b or SLEW pin
130 200 315 V/us
tied to AVDD
VVM = 24 V, SLEW = 00b or SLEW pin
15 25 50 V/us
tied to AGND
VVM = 24 V, SLEW = 01b or SLEW pin in
Phase pin slew rate switching high to low Hi-Z 30 50 95 V/us
SR (Falling from 80 % to 20 %
VVM = 24 V, SLEW = 10b or SLEW pin to
80 125 235 V/us
47 kΩ +/- 5% to AVDD
VVM = 24 V, SLEW = 11b or SLEW pin
130 200 345 V/us
tied to AVDD
Leakage current on OUTx VOUTx = VVM, nSLEEP = 1 5 mA
ILEAK
Leakage current on OUTx VOUTx = 0 V, nSLEEP = 1 1 µA
VVM = 24 V, SR = 25 V/µs, HS driver ON
1800 3400 ns
to LS driver OFF
VVM = 24 V, SR = 50 V/µs, HS driver ON
1100 1550 ns
to LS driver OFF
tDEAD Output dead time
VVM = 24 V, SR = 125 V/µs, HS driver
650 1000 ns
ON to LS driver OFF
VVM = 24 V, SR = 200 V/µs, HS driver
500 750 ns
ON to LS driver OFF
VVM = 24 V, PWM = 1 to OUTx
2000 4550 ns
transisition, SR = 25 V/µs
VVM = 24 V, PWM = 1 to OUTx
1200 2150 ns
transisition, SR = 50V/µs
tPD Propagation delay
VVM = 24 V, PWM = 1 to OUTx
800 1350 ns
transisition, SR = 125 V/µs
VVM = 24 V, PWM= 1 to OUTx
650 1050 ns
transisition, SR = 200 V/µs
tMIN_PULSE Minimum output pulse width SR = 200 V/µs 600 ns
HALL COMPARATORS

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7.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD –
VICM Input common mode voltage (Hall) 0.5 V
1.2
HALL_HYS = 0 1.5 5 8 mV
Voltage hysteresis (SPI Device)
VHYS HALL_HYS = 1 35 50 80 mV
Voltage hysteresis (HW Device) 1.5 5 8 mV
Between Hall A, Hall B and Hall C
ΔVHYS Hall comparator hysteresis difference –8 8 mV
comparator
VH(MIN) Minimum Hall differential voltage 40 mV
II Input leakage current HPX = HNX = 0 V –1 1 μA
tHDG Hall deglitch time 0.6 1.15 1.7 μs
tE_HDG Hall enable deglitch time During power up 1.4 μs
CYCLE-BY-CYCLE CURRENT LIMIT
Voltage on ILIM pin for cycle by cycle AVDD/2–
VILIM AVDD/2 V
current limit 0.32
Current
Current limit corresponding to ILIM pin
ILIMIT limit 4 A
voltage range
disabled
ILIM_AC Current limit accuracy(2) ILIMIT ≥ 1A –14 14 %
tBLANK Cycle by cycle current limit blank time 5 µs
ADVANCE ANGLE
ADVANCE_LVL = 000 b 0 1 °
ADVANCE_LVL = 001 b 3 4 5 °
ADVANCE_LVL = 010 b 6 7 8 °

Advance Angle Setting ADVANCE_LVL = 011 b 10 11 12 °

θADV
(SPI Device) ADVANCE_LVL = 100 b 13.5 15 16.5 °
ADVANCE_LVL = 101 b 18 20 22 °
ADVANCE_LVL = 110 b 22.5 25 27.5 °
ADVANCE_LVL = 111 b 27 30 33 °
Advance pin tied to AGND 0 1 °
Advance pin tied to 22 kΩ ± 5% to
3 4 5 °
AGND
Advance pin tied to 100 kΩ ± 5% to
10 11 12 °
AGND
Advance Angle Setting
θADV
(HW Device) Advance pin in Hi-Z 13.5 15 16.5 °
Advance pin tied to 100 kΩ ± 5% to
18 20 22 °
AVDD
Advance pin tied to 22 kΩ ± 5% to AVDD 22.5 25 27.5 °
Advance pin tied to AVDD 27 30 33 °
PROTECTION CIRCUITS
VM rising 4.3 4.4 4.5 V
VUVLO Supply undervoltage lockout (UVLO)
VM falling 4.1 4.2 4.3 V
VUVLO_HYS Supply undervoltage lockout hysteresis Rising to falling threshold 140 200 350 mV
tUVLO Supply undervoltage deglitch time 3 5 7 µs

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7.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply rising, OVP_EN = 1, OVP_SEL =
32.5 34 35 V
0
Supply falling, OVP_EN = 1, OVP_SEL
31.8 33 34.3 V
Supply overvoltage protection (OVP) =0
VOVP
(SPI Device) Supply rising, OVP_EN = 1, OVP_SEL =
20 22 23 V
1
Supply falling, OVP_EN = 1, OVP_SEL
19 21 22 V
=1

Supply overvoltage protection (OVP) Rising to falling threshold, OVP_SEL = 1 0.9 1 1.1 V
VOVP_HYS
(SPI Device) Rising to falling threshold, OVP_SEL = 0 0.7 0.8 0.9 V
tOVP Supply overvoltage deglitch time 2.5 5 7 µs

Charge pump undervoltage lockout Supply rising 2.3 2.5 2.7 V

VCPUV
(above VM) Supply falling 2.2 2.4 2.6 V
VCPUV_HYS Charge pump UVLO hysteresis Rising to falling threshold 75 100 140 mV
Supply rising 2.7 2.85 3 V
VAVDD_UV Analog regulator undervoltage lockout
Supply falling 2.4 2.65 2.8 V
VAVDD_ Analog regulator undervoltage lockout
Rising to falling threshold 180 200 240 mV
UV_HYS hysteresis

Overcurrent protection trip point (SPI OCP_LVL = 0b 5.5 9 12 A

Device) OCP_LVL = 1b 9 13 18 A
IOCP
Overcurrent protection trip point (HW
5.5 9 12 A
Device)
OCP_DEG = 00b 0.02 0.2 0.4 µs

Overcurrent protection deglitch time OCP_DEG = 01b 0.2 0.6 1.2 µs

(SPI Device) OCP_DEG = 10b 0.5 1.2 1.8 µs
tOCP
OCP_DEG = 11b 0.9 1.6 2.5 µs
Overcurrent protection deglitch time
0.2 0.6 1.2 µs
(HW Device)

Overcurrent protection retry time OCP_RETRY = 0 4 5 6 ms

tRETRY
(SPI Device) OCP_RETRY = 1 425 500 575 ms
MOTOR_LOCK_TDET = 00b 270 300 330 ms

Motor lock detection time MOTOR_LOCK_TDET = 01b 450 500 550 ms

tMTR_ LOCK
(SPI Device) MOTOR_LOCK_TDET = 10b 900 1000 1100 ms
MOTOR_LOCK_TDET = 11b 4500 5000 5500 ms
Motor lock detection time
tMTR_ LOCK 900 1000 1100 ms
(HW Device)

tMTR_LOCK_R Motor lock retry time MOTOR_LOCK_RETRY = 0b 450 500 550 ms

ETRY (SPI Device) MOTOR_LOCK_RETRY = 1b 4500 5000 5500 ms
tMTR_LOCK_R Motor lock retry time
450 500 550 ms
ETRY (HW Device)
TOTW Thermal warning temperature Die temperature (TJ) 135 145 155 °C
TOTW_HYS Thermal warning hysteresis Die temperature (TJ) 15 20 30 °C
TTSD Thermal shutdown temperature (Buck) Die temperature (TJ) 170 180 190 °C
TTSD_HYS Thermal shutdown hysteresis (Buck) Die temperature (TJ) 15 20 30 °C
TTSD_FET Thermal shutdown temperature (FET) Die temperature (TJ) 165 175 185 °C

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7.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TTSD_FET_HY
Thermal shutdown hysteresis (FET) Die temperature (TJ) 15 20 30 °C
S

(1) RLBK is resistance of inductor LBK

(2) Current limit accuracy depends on blanking time, motor parameters and VM

7.6 SPI Timing Requirements

MIN NOM MAX UNIT
tREADY SPI ready after power up 1 ms
tHI_nSCS nSCS minimum high time 300 ns
tSU_nSCS nSCS input setup time 25 ns
tHD_nSCS nSCS input hold time 25 ns
tSCLK SCLK minimum period 100 ns
tSCLKH SCLK minimum high time 50 ns
tSCLKL SCLK minimum low time 50 ns
tSU_SDI SDI input data setup time 25 ns
tHD_SDI SDI input data hold time 25 ns
tDLY_SDO SDO output data delay time 25 ns
tEN_SDO SDO enable delay time 50 ns
tDIS_SDO SDO disable delay time 50 ns

7.7 SPI Secondary Device Mode Timings

tHI_nSCS tSU_nSCS tHD_nSCS

tSCLK

tSCLKH tSCLKL

X MSB LSB X

tDLY_SDO tDIS_SDO
tSU_SDI tHD_SDI

Z MSB LSB Z

tEN_SDO

Figure 7-1. SPI Secondary Device Mode Timing Diagram

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7.8 Typical Characteristics

17 425

16 400

15 375
FPWM = 200 kHz
14
Active Current (mA)

350
13

RDS(ON), m
TJ = -40 C 325
12 TJ = 25 C
TJ = 150 C 300
11
10 275

9 FPWM = 25 kHz 250

8 225
7
6 9 12 15 18 21 24 27 30 33 36 200
-40 -20 0 20 40 60 80 100 120 140 160
Supply Voltage (V) Junction Temperature, oC
Figure 7-2. Supply current over supply voltage Figure 7-3. RDS(ON) (high and low side combined) for MOSFETs
over temperature
100 5.75
TJ = -40 C
97.5 5.5
TJ = 25 C
95 TJ = -150 C 5.25

Buck Output Voltage (V)

5
92.5
Buck Efficiency (%)

4.75
90 BUCK_SEL = 00b
4.5
87.5 BUCK_SEL = 01b
4.25 BUCK_SEL = 10b
85 BUCK_SEL = 11b
4
82.5 3.75
80 3.5
77.5 3.25
75 3
4 8 12 16 20 24 28 32 36 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Supply Voltage (V) Buck Output Load Current (A)
Figure 7-4. Buck regulator efficiency over supply voltage Figure 7-5. Buck regulator output voltage over load current

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8 Detailed Description
8.1 Overview
The MCT8315Z device is an integrated 275-mΩ (high-side + low-side MOSFET's on-state resistance) driver
for 3-phase motor-drive applications. The device reduces system component count, cost, and complexity
by integrating three half-bridge MOSFETs, gate drivers, charge pump, linear regulator and buck regulator
for external loads. A standard serial peripheral interface (SPI) provides a simple method for configuring the
various device settings and reading fault diagnostic information through an external microcontroller. Alternatively,
hardware interface (pin) variants allow for configuring the most commonly used settings through fixed external
resistors.
The architecture uses an internal state machine to protect against short-circuit events and dv/dt parasitic turn-on
of the internal power MOSFETs.
The MCT8315Z device integrates three-phase sensored trapezoidal commutation using analog or digital hall
sensors for position detection.
In addition to the high level of device integration, MCT8315Z provides a wide range of integrated protection
features. These features include power-supply undervoltage lockout (UVLO), charge-pump undervoltage lockout
(CPUV), overcurrent protection (OCP), AVDD undervoltage lockout (AVDD_UV), buck regulator UVLO and
overtemperature warning and shutdown (OTW and TSD). Fault events are indicated by the nFAULT pin with
detailed information available in the SPI registers on the SPI variant.
The MCT8315ZR, MCT8315ZT and MCT8315ZH devices are available in a 0.5-mm pin pitch, WQFN surface-
mount package. The WQFN package size is 6 mm × 4 mm.

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8.2 Functional Block Diagram

VVM

+
CFLY CCP CVM1 CVM2
Replace Resistor (RBK)
CPH CPL CP VM
with Inductor (LBK) for
larger external load
To AVDD and
Buck Regulator or to reduce power
dissipaon
Regulators Ext.
AVDD Load

Charge Pump VVM CAVDD1

AVDD Linear Regulator AGND

LBK Ext.
SW_BK Load

RBK CBK
I/O Control
VVM GND_BK
Buck Regulator

DRVOFF
FB_BK

Protection
nSLEEP
Differential Comparators
HPC
Overcurrent +
Protection HNC (Optional)
Input -
PWM Control
Thermal Warning HPB
To
Digital +
Thermal Shutdown HNB (Optional)
Control -
BRAKE
HPA
+
(Optional)
- HNA

AVDD
Output Predriver Stage Power Stage
RnFAULT
VCP VM

nFAULT
HS Pre-
AVDD driver
RFGOUT OUTA
VLS
FGOUT
LS Pre-
driver Current
Sense for
PGND Phase - A

Interface Digital Control

Predriver Stage Power Stage ISEN_A

SCLK
VCP VM
SPI
AVDD or
SDI Buck Output
AVDD HS Pre-
driver
Hall A
OUTB
SDO** Hall B
VLS

AVDD Hall C
LS Pre-
driver Current
nSCS Sense for
PGND Phase - B
AVDD

RCL1
ILIM Predriver Stage Power Stage ISEN_B
+
RCL2 - VCP VM
ISEN_A
AV
SOA HS Pre-
driver
ISEN_B Output SOB
AV OUTC
Offset
Bias VLS
SOC
ISEN_C
AV LS Pre-
driver Current
AVDD Sense for
PGND Phase - C
Current Sense and Current Limit

ISEN_C

** SDO can be con
gured to open drain or push TPAD PGND PGND PGND
pull con guraon

Figure 8-1. MCT8315ZR Block Diagram

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VVM

+
CFLY CCP CVM1 CVM2

CPH CPL CP VM Replace Resistor (RBK)

with Inductor (LBK) for
To AVDD and larger external load
Buck Regulator or to reduce power
dissipa on
Regulators Ext.
AVDD Load

Charge Pump VVM CAVDD1

AVDD Linear Regulator AGND

LBK Ext.
SW_BK Load

RBK CBK
I/O Control
VVM GND_BK
Buck Regulator

nSLEEP FB_BK

Protection

Differential Comparators
PWM
HPC
Overcurrent +
Protection HNC (Optional)
-
DIR Thermal Warning HPB
To
Digital +
Thermal Shutdown HNB (Optional)
Control -

BRAKE HPA
+
(Optional)
- HNA
Input
Control
DRVOFF

AVDD Predriver Stage Power Stage

VCP VM
ADVANCE

HS Pre-
AVDD driver

OUTA
MODE VLS

LS Pre-
AVDD driver Current
Sense for
PGND Phase - A
SLEW

Digital Control

AVDD Predriver Stage Power Stage ISEN_A

RnFAULT Output VCP VM

AVDD or
nFAULT HS Pre- Buck Output
driver
AVDD Hall A
OUTB
RFGOUT Hall B
VLS
Hall C
FGOUT
LS Pre-
driver Current
Sense for
PGND Phase - B
AVDD

RCL1
ILIM Predriver Stage Power Stage ISEN_B
+
RCL2 - VCP VM
ISEN_A
AV
SOA HS Pre-
driver
ISEN_B Output SOB
AV OUTC
Offset
Bias VLS
SOC
ISEN_C
AV LS Pre-
driver Current
AVDD Sense for
PGND Phase - C
Current Sense and Current Limit

ISEN_C

TPAD PGND PGND PGND

Figure 8-2. MCT8315ZH Block Diagram

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VVM

+
CFLY CCP CVM1 CVM2

CPH CPL CP VM

To AVDD Regulator

Ext.
AVDD Load

Charge Pump VVM CAVDD1

AVDD Linear Regulator AGND

I/O Control

nSLEEP

Protection

Differential Comparators
PWM
HPC
Overcurrent +
Protection HNC (Optional)
-
DIR Thermal Warning HPB
To
Digital +
Thermal Shutdown HNB (Optional)
Control -

BRAKE HPA
+
(Optional)
- HNA
Input
DRVOFF Control

Predriver Stage Power Stage

AVDD VCP VM

ADVANCE HS Pre-
driver
AVDD OUTA
VLS
MODE
LS Pre-
AVDD driver Current
Sense for
PGND Phase - A
SLEW
Digital Control

AVDD Predriver Stage Power Stage ISEN_A

RnFAULT Output VCP VM

AVDD or
nFAULT HS Pre- Buck Output
driver
AVDD Hall A
OUTB
RFGOUT Hall B
VLS
Hall C
FGOUT
LS Pre-
driver Current
Sense for
PGND Phase - B
AVDD

RCL1
ILIM Predriver Stage Power Stage ISEN_B
+
RCL2 - VM
VCP
ISEN_A
AV
SOA HS Pre-
driver
RCL1 ISEN_B Output SOB
AV OUTC
Offset
Bias VLS
SOC
ISEN_C
AV LS Pre-
driver Current
AVDD Sense for
PGND Phase - C
Current Sense and Current Limit

ISEN_C

TPAD PGND PGND PGND

Figure 8-3. MCT8315ZT Block Diagram

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8.3 Feature Description

Table 8-1 lists the recommended values of the external components for the driver.
Table 8-1. MCT8315Z External Components
COMPONENTS PIN 1 PIN 2 RECOMMENDED
X5R or X7R, 0.1-µF, TI recommends a capacitor
CVM1 VM PGND voltage rating at least twice the normal operating
voltage of the device
≥ 10-µF, TI recommends a capacitor voltage rating at
CVM2 VM PGND
least twice the normal operating voltage of the device
CCP CP VM X5R or X7R, 16-V, 1-µF capacitor
X5R or X7R, 47-nF, TI recommends a capacitor
CFLY CPH CPL voltage rating at least twice the normal operating
voltage of the pin
X5R or X7R, 1-µF, ≥ 6.3-V. In order for AVDD to
accurately regulate output voltage, capacitor should
CAVDD AVDD AGND
have effective capacitance between 0.7-µF to 1.3-µF
at 3.3-V across operating temperature.
X5R or X7R, 22-µF, buck-output rated capacitor. TI
CBK FB_BK GND_BK recommends a capacitor voltage rating at least twice
the normal operating voltage of the pin
LBK SW_BK FB_BK Output inductor
RnFAULT VCC nFAULT 5.1-kΩ, Pullup resistor
RMODE MODE AGND or AVDD MCT8315Z hardware interface
RSLEW SLEW AGND or AVDD MCT8315Z hardware interface
RADVANCE ADVANCE AGND or AVDD MCT8315Z hardware interface
CILIM ILIM AGND X5R or X7R, 0.1-µF, AVDD-rated capacitor (optional)

Note
TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into
internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on
power up or the device will enter internal test mode.

8.3.1 Output Stage

The MCT8315Z device consists of an integrated 275-mΩ (combined high-side and low-side FETs' on-state
resistance) NMOS FETs connected in a three-phase H-bridge configuration. A doubler charge pump provides
the proper gate-bias voltage to the high-side NMOS FETs across a wide operating-voltage range in addition to
providing 100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side
MOSFETs. The device has two VM motor power-supply pins which are to be connected together to the motor-
supply voltage.
8.3.2 PWM Control Mode (1x PWM Mode)
The MCT8315Z family of devices provides seven different control modes to support various commutation and
control methods. The MCT8315Z device provides a 1x PWM control mode for driving the BLDC motor in
trapezoidal current-control mode. The MCT8315Z device uses 6-step block commutation tables that are stored
internally. This feature lets a three-phase BLDC motor be controlled using a single PWM sourced from a simple
controller. The PWM is applied on the PWM pin and determines the output frequency and duty cycle of the
half-bridges.
The MCT8315Z family of devices supports both analog and digital hall inputs by changing mode input setting.
Differential hall inputs should be connected to HPx and HNx pins (see Figure 8-4). Digital hall inputs should be
connected to the HPx pins while keeping the HNx pins floating (see Figure 8-5).

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The half-bridge output states are managed by the HPA, HNA, HPB, HNB, HPC and HNC pins in analog mode
and HPA, HPB, HPC in digital mode which are used as state logic inputs. The state inputs are the position
feedback of the BLDC motor. The 1x PWM mode usually operates with synchronous rectification (low-side
MOSFET recirculation); however, the mode can be configured to use asynchronous rectification (MOSFET body
diode freewheeling) as shown below
Table 8-2. PWM_MODE Configuration
MODE Pin (Hardware
MODE Type Hall Configuration Modulation ASR and AAR Mode
Variant)
Mode 1 Connected to AGND Analog Hall Input Asynchronous ASR and AAR Disabled
Connected to AGND with
Mode 2 Digital Hall Input Asynchronous ASR and AAR Disabled
RMODE1
Connected to AGND with
Mode 3 Analog Hall Input Synchronous ASR and AAR Disabled
RMODE2
Mode 4 Hi-Z Digital Hall Input Synchronous ASR and AAR Disabled
Connected to AVDD with
Mode 5 Analog Hall Input Synchronous ASR and AAR Enabled
RMODE2
Connected to AVDD with
Mode 6
RMODE1 Digital Hall Input Synchronous ASR and AAR Enabled
Mode 7 Connected to AVDD

Note
Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during
operation of the power MOSFETs. Set PWM to a low level before changing the PWM_MODE register.

8.3.2.1 Analog Hall Input Configuration

Figure 8-4 shows the connection of Analog Hall inputs to the driver. Analog hall elements are fed to the hall
comparators, which zero crossing is used to generate the commutation logic.

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MCT8315Z
HPC
(Optional)
HNC

HPB
Analog Hall (Optional)
Comparator Input HNB

HPA
MCU_PWM PWM (Optional)
HNA
MCU_GPIO DIR

MCU_GPIO OUTA
BRAKE

Hall A

Hall B
OUTB
Hall C

OUTC

Figure 8-4. 1x PWM Mode with Analog Hall Input

Note
Texas Instruments recommends motor direction (DIR) change when the motor is stationary.

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8.3.2.2 Digital Hall Input Configuration

Figure 8-5 shows the connection of Digital Hall inputs to the driver.

MCT8315Z
HPC

HNC X
HPB
Digital Inputs
HNB X

HPA
MCU_PWM PWM
HNA X
MCU_GPIO DIR

MCU_GPIO OUTA
BRAKE

Hall A

Hall B
OUTB
Hall C

OUTC

Figure 8-5. 1x PWM Mode with Digital Hall Input

8.3.2.3 Asynchronous Modulation

The DIR pin controls the direction of BLDC motor in either clockwise or counter-clockwise direction. Tie the DIR
pin low if this feature is not required.
The BRAKE input halts the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled high. This brake is independent of the states of the other input pins. Tie the BRAKE pin low if
this feature is not required.
Table 8-3 shows the configuration in 1x PWM mode with asynchronous modulation.
Table 8-3. Asynchronous Modulation
HALL INPUTS DRIVER OUTPUTS
DIR = 0 DIR = 1 PHASE A PHASE B PHASE C
STATE HALL_A HALL_B HALL_C HALL_A HALL_B HALL_C High Low High Low High Low DESCRIPTION
/HPA /HPB /HPC /HPA /HPB /HPC Side Side Side Side Side Side
Stop 0 0 0 0 0 0 L L L L L L Stop
Align 1 1 1 1 1 1 PWM L L H L H Align
1 1 1 0 0 0 1 L L PWM L L H B→C
2 1 0 0 0 1 1 PWM L L L L H A→C
3 1 0 1 0 1 0 PWM L L H L L A→B
4 0 0 1 1 1 0 L L L H PWM L C→B
5 0 1 1 1 0 0 L H L L PWM L C→A
6 0 1 0 1 0 1 L H PWM L L L B→A

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8.3.2.4 Synchronous Modulation

Table 8-4 shows the configuration in 1x PWM mode with synchronous modulation.
Table 8-4. Synchronous Modulation
HALL INPUTS DRIVER OUTPUTS
DIR = 0 DIR = 1 PHASE A PHASE B PHASE C
STATE HALL_A HALL_B HALL_C HALL_A HALL_B HALL_C High Low High Low High Low DESCRIPTION
/HPA /HPB /HPC /HPA /HPB /HPC Side Side Side Side Side Side
Stop 0 0 0 0 0 0 L L L L L L Stop
Align 1 1 1 1 1 1 PWM !PWM L H L H Align
1 1 1 0 0 0 1 L L PWM !PWM L H B→C
2 1 0 0 0 1 1 PWM !PWM L L L H A→C
3 1 0 1 0 1 0 PWM !PWM L H L L A→B
4 0 0 1 1 1 0 L L L H PWM !PWM C→B
5 0 1 1 1 0 0 L H L L PWM !PWM C→A
6 0 1 0 1 0 1 L H PWM !PWM L L B→A

8.3.2.5 Motor Operation

Figure 8-6 and Figure 8-7 shows the BLDC motor commutation with direction setting (DIR) as 0 and 1
respectively.

Hall A Hall A
&t &t

Hall B Hall B
&t &t

Hall C Hall C
&t &t

Idc Idc
Van Van
ia ia
0 0
&t 2Œ/3 &t
2Œ/3

Vbn Vbn
ib ib

0 0
&t 2Œ/3 &t
2Œ/3

Vcn Vcn
ic ic
0 0
&t 2Œ/3 &t
2Œ/3

HA, LB HA, LC HB, LC HB, LA HC, LA HC, LB HB, LA HC, LA HC, LB HA, LB HA, LC HB, LC

2Π&t 2Π&t

Figure 8-6. BLDC Motor Commutation with DIR = 0 Figure 8-7. BLDC Motor Commutation with DIR = 1

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8.3.3 Device Interface Modes

MCT8315Z supports two different interface modes (SPI and hardware) to provide either flexibility or simplicity
to users. The two interface modes share the same pins (except pins 26-29) allowing the different versions to
be largely pin-to-pin compatible. This compatibility allows application designers to evaluate with one interface
variant and switch to another with minimal modifications to their design.
8.3.3.1 Serial Peripheral Interface (SPI)
The SPI variant supports a serial communication bus that allows an external microcontroller to send and receive
data with MCT8315Z. This allows the external microcontroller to configure device settings and read detailed fault
information. The SPI interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are
described as follows:
• The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on
the SDI and SDO pins.
• The SDI pin is the data input.
• The SDO pin is the data output. The SDO pin can be configured to either open-drain or push-pull through
SDO_MODE.
• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
MCT8315Z.
For more information on the SPI, see the Section 8.5 section.
8.3.3.2 Hardware Interface
Hardware variant uses three resistor-configurable inputs (in the place of SPI pins) which are ADVANCE, MODE
and SLEW.
This variant allows the application designer to configure the critical device settings by tying each pin to logic
high or logic low or leave it floating or pull-up to logic high or pull-down to logic low with a suitable resistor. This
eliminates the requirement for an SPI bus from the external microcontroller to configure MCT8315Z. General
fault information can still be obtained through the nFAULT pin. The voltage levels on the configurable pins
(ADVANCE, SLEW and MODE) are detected only once during power-up and used for device configuration - any
subsequent change in the voltage of these pins does not affect the device configuration till a subsequent power
reset.
• The MODE pin configures the PWM control mode.
• The SLEW pin configures the slew rate of the output voltage.
• The ADVANCE pin configures the lead angle of the output with respect to hall signals.
For more information on the hardware interface, see the Section 8.3.10 section.

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AVDD AVDD
SCLK
RSLEW
SLEW
SPI AVDD
SDI Interface AVDD
VCC MODE
Hardware
RPU AVDD Interface
SDO

AVDD ADVANCE

nSCS

Figure 8-9. MCT8315ZT/H Hardware Interface

Figure 8-8. MCT8315ZR SPI Interface

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8.3.4 Step-Down Mixed-Mode Buck Regulator

The MCT8315Z has an integrated mixed-mode buck regulator to supply regulated 3.3-V or 5.0-V power for an
external controller or system voltage rail. Additionally, the buck output can also be configured to 4.0-V or 5.7-V
for supporting the extra headroom for external LDO for generating a 3.3-V or 5.0-V supplies. The output voltage
of the buck converter is set by BUCK_SEL bits in the MCT8315ZR device (SPI variant). The output voltage of
the buck converter in MCT8315ZH (hardware variant) is always set to 5.0-V.
The buck regulator has a low quiescent current of ~1-2 mA during light loads to prolong battery life. The device
improves performance during line and load transients by implementing a pulse-frequency current-mode control
scheme which requires less output capacitance and simplifies frequency compensation design.
To disable the buck regulator, set the BUCK_DIS bit to 1b in MCT8315ZR (SPI variant). The buck regulator
cannot be disabled in MCT8315ZH (hardware variant). MCT8315ZT has no buck regulator.

Note
If the buck regulator is unused in MCT8315ZH, the buck pins SW_BK, GND_BK, and FB_BK cannot
be left floating or connected to ground. The buck regulator components LBK/RBK and CBK must be
connected in hardware.

Table 8-5. Recommended settings for Buck Regulator

Buck Mode Buck output voltage Max output current Max output current Buck current limit AVDD power
from AVDD (IAVDD) from Buck (IBK) sequencing
Inductor - 47 μH 3.3-V or 4.0-V or 5.0- 30 mA 200 mA 600 mA (BUCK_CL = Not supported
V or 5.7-V 0b) (BUCK_PS_DIS = 1)
Inductor - 47 μH 5.0-V or 5.7-V 30 mA 200 mA - IAVDD 600 mA (BUCK_CL = Supported
0b) (BUCK_PS_DIS = 0)
Inductor - 22 μH 3.3-V or 4.0-V or 5.0- 30 mA 50 mA 150 mA (BUCK_CL = Not supported
V or 5.7-V 1b) (BUCK_PS_DIS = 1)
Inductor - 22 μH 5.0-V or 5.7-V 30 mA 50 mA - IAVDD 150 mA (BUCK_CL = Supported
1b) (BUCK_PS_DIS = 0)
Resistor - 22 Ω 3.3-V or 4.0-V or 5.0- 30 mA 40 mA 150 mA (BUCK_CL = Not supported
V or 5.7-V 1b) (BUCK_PS_DIS = 1)
Resistor - 22 Ω 5.0-V or 5.7-V 30 mA 40 mA - IAVDD 150 mA (BUCK_CL = Supported
1b) (BUCK_PS_DIS = 0)

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8.3.4.1 Buck in Inductor Mode

The buck regulator in MCT8315Z device is primarily designed to support low inductance of 47 µH and 22 µH
inductors. The 47 µH inductor allows the buck regulator to operate up to 200 mA load current support, whereas
the 22 µH inductor limits the load current to 50 mA.
Figure 8-10 shows the connection of buck regulator in inductor mode.

VM

SW_BK
Ext. Load

Control LBK VBK

CBK

GND_BK

FB_BK

Figure 8-10. Buck (Inductor Mode)

8.3.4.2 Buck in Resistor mode

If the external load requirements is less than 40 mA, the inductor can be replaced with a resistor. In resistor
mode the power is dissipated across the external resistor and the efficiency is lower than buck in inductor mode.
Figure 8-11 shows the connection of buck regulator in resistor mode.

VM

SW_BK
Ext. Load

Control RBK VBK

CBK

GND_BK

FB_BK

Figure 8-11. Buck (Resistor Mode)

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8.3.4.3 Buck Regulator with External LDO

The buck regulator also supports the voltage requirement to fed to external LDO to generate standard 3.3 V or
5.0 V output rail with higher accuracies. The buck output voltage should be configured to 4 V or 5.5 V to provide
for a extra headroom to support the external LDO for generating 3.3 V or 5 V rail as shown in Figure 8-12.
This allows for a lower-voltage LDO design to save cost and better thermal management due to low drop-out
voltage.

VM

VBK VLDO
SW_BK (3.3V / 5V)
(4V / 5.7V)
VIN VLDO
Control LBK Ext. Load

CBK 3.3V / 5V CLDO

LDO
GND_BK

GND GND
FB_BK
External LDO

Figure 8-12. Buck Regulator with External LDO

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8.3.4.4 AVDD Power Sequencing on Buck Regulator

The AVDD LDO has an option of using the power supply from mixed mode buck regulator to reduce power
dissipation internally. The power sequencing mode allows on-the-fly changeover of LDO power supply from DC
mains (VM) to buck output (VBK) as shown in Figure 8-13. This sequencing can be configured through the
BUCK_PS_DIS bit. Power sequencing is supported only when buck output voltage is set to 5.0 V or 5.7 V.
VM

SW_BK
Ext. Load

Control LBK VBK

CBK

GND_BK

FB_BK

BUCK_PS_DIS
VBK

VM

REF +
– AVDD External Load

CAVDD
AGND

Figure 8-13. AVDD Power Sequencing on mixed mode Buck Regulator

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8.3.4.5 Mixed mode Buck Operation and Control

The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control.
The output voltage of the buck regulator is compared with the internal reference voltage (VBK_REF) which is
internally generated depending on the buck-output voltage setting (BUCK_SEL) which constitutes an outer
voltage control loop. Depending on the comparator output going high (VBK < VBK_REF) or low (VBK > VBK_REF),
the high-side power FET of the buck turns on and turna off respectively. An independent current control loop
monitors the current in high-side power FET (IBK) and turns off the high-side FET when the current becomes
higher than the buck current limit (IBK_CL). This implements a current limit control for the buck regulator. Figure
8-14 shows the architecture of the buck and various control/protection loops.

SW_BK
IBK Ext. Load
VM
LBK VBK

PWM Control
and Driver CBK

GND_BK
+ IBK
Current Limit
_ IBK_CL

+ IBK
OC Protection
_ IBK_OCP

+ VBK FB_BK
UV Protection
_ VBK_UVLO

VM VBK
+
Voltage Control
_ VBK_REF

Buck
BUCK_SEL
Reference
Buck Control Voltage
Generator

Figure 8-14. Buck Operation and Control Loops

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8.3.5 AVDD Linear Voltage Regulator

A 3.3-V linear regulator is integrated into the MCT8315Z family of devices and is available for use by external
circuitry. The AVDD regulator is used for powering up the internal digital circuitry of the device and additionally,
this regulator can also provide the supply voltage for a low-power MCU or other circuitry supporting low current
(up to 30 mA). The output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R,
1-µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.
The AVDD nominal, no-load output voltage is 3.3 V.

FB_BK

BUCK_PS_DIS
VBK

VM

REF +
– AVDD External Load

CAVDD
AGND

Figure 8-15. AVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator with VM as supply
(BUCK_PS_DIS = 1b)

2 = (88/ F 8#8&& ) × +#8&& (1)

For example, at a VVM of 24 V, drawing 20 mA out of AVDD results in a LDO power dissipation as shown in
Equation 2.

PLDO = (VVM - VAVDD) x IAVDD = (24 - 3.3)V x 20mA = 414mW (2)

Use Equation 3 to calculate the power dissipated in the device by the AVDD linear regulator with buck output as
supply (BUCK_PS_DIS = 0b)

P = VFB_BK − VAVDD × IAVDD (3)

For example, at a VFB_BK of 5 V, drawing 20 mA out of AVDD results in a LDO power dissipation as shown in
Equation 4.

PLDO = (VFB_BK - VAVDD) x IAVDD = (5 - 3.3)V x 20mA = 34mW (4)

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8.3.6 Charge Pump

Because the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the
VM power supply to enhance the high-side FETs fully. The MCT8315Z integrates a charge-pump circuit that
generates a voltage above the VM supply for this purpose.
The charge pump requires two external capacitors for operation. See Figure 8-1, Figure 8-2, Figure 8-3, Section
6 and Section 8.3 for details on these capacitors (value, connection, and so forth).
The charge pump shuts down when nSLEEP is low.

VM

VM

CCP
CP

CPH

VM

CFLY Charge
Pump
Control
CPL

Figure 8-16. MCT8315Z Charge Pump

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8.3.7 Slew Rate Control

An adjustable gate-drive current control to the MOSFETs of half-bridges is implemented to achieve the slew
rate control. The MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and
duration of diode recovery spikes, and switching voltage transients related to parasitics. These slew rates are
predominantly determined by the rate of gate charge to internal MOSFETs as shown in Figure 8-17.

VCP (Internal) VM

Slew Rate
Control

VCP (Internal) OUTx

Slew Rate
Control

GND

Figure 8-17. Slew Rate Circuit Implementation

The slew rate can be adjusted by the SLEW pin in hardware variant or by using the SLEW bits in SPI variant.
Four slew rate settings are available : 25-V/µs, 50-V/µs, 125-V/µs or 200-V/µs. The slew rate is calculated by the
rise time and fall time of the voltage on OUTx pin as shown in Figure 8-18.
VOUTx

VM
VM
80% 80%

20% 20%
0

Time
trise tfall

Figure 8-18. Slew Rate Timings

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8.3.8 Cross Conduction (Dead Time)

The device is fully protected against any cross conduction of MOSFETs - during the switching of high-side
and low-side MOSFETs, MCT8315Z avoids shoot-through events by inserting a dead time (tdead). This is
implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs and ensuring
that VGS of high-side MOSFET has reached below turn-off levels before switching on the low-side MOSFET of
same half-bridge (or vice-versa) as shown in Figure 8-19 and Figure 8-20.

VM

HS Gate
Control

+
VGS_HS
OUTx
–

LS Gate
Control

+ GND
VGS_LS
–

Figure 8-19. Cross Conduction Protection

VGS_HS

10%

tDEAD

VGS_LS
10%

Time

Figure 8-20. Dead Time

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8.3.9 Propagation Delay

The propagation delay time (tpd) is measured as the time between an input logic edge to change in gate driver
voltage. This time has three parts consisting of the digital input deglitcher delay, analog driver, and comparator
delay.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes, a small digital delay is added as the input command propagates
through the device.

PWM

OUTx High
tPD

1V
OUTx Low
OUTx
Time

Figure 8-21. Propagation Delay Timing

8.3.9.1 Driver Delay Compensation

MCT8315Z monitors the propagation delay internally and adds a variable delay on top of it to provide fixed delay
as shown in Figure 8-22 and Figure 8-23. Delay compensation feature reduces uncertainty caused in timing of
current measurement and also reduces duty cycle distortion caused due to propagation delay.
The fixed delay is summation of propagation delay (tPD) caused to internal driver delay and variable delay (tVAR)
added to compensate for uncertainty. The fixed delay can be configured through DLY_TARGET register. Refer
Table 8-6 for recommendation on configuration for DLY_TARGET for different slew rate settings.
Delay compensation is only available in SPI variant MCT8315Z and can be enabled by configuring DLYCMP_EN
and DLY_TARGET. It is disabled in hardware variant MCT8315Z.

PWM PWM

1V 1V 1V 1V
OUTx OUTx

Time Time

tPD tVAR tPD tVAR tPD tVAR tPD tVAR

DLY_TARGET DLY_TARGET DLY_TARGET DLY_TARGET

Figure 8-22. Delay Compensation with current Figure 8-23. Delay Compensation with current
flowing out of phase flowing into the phase

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Table 8-6. Delay Target Recommendation

SLEW RATE DLY_TARGET
200 V/μs DLY_TARGET = 0x5 (1.2 μs)
125 V/μs DLY_TARGET = 0x8 (1.8 μs)
50 V/μs DLY_TARGET = 0xB (2.4 μs)
25 V/μs DLY_TARGET = 0xF (3.2 μs)

8.3.10 Pin Diagrams

This section presents the I/O structure of all digital input and output pins.
8.3.10.1 Logic Level Input Pin (Internal Pulldown)
Figure 8-24 shows the input structure for the logic level pins, BRAKE, DIR, DRVOFF, nSLEEP, PWM, SCLK and
SDI. The input can be with a voltage or external resistor. It is recommended to put these pins low in device sleep
mode to reduce leakage current through internal pull-down resistors.

AVDD

STATE CONNECTION INPUT

VIH Tied to AVDD Logic High

VIL Tied to GND Logic Low

ESD RPD

Figure 8-24. Logic-Level Input Pin Structure

8.3.10.2 Logic Level Input Pin (Internal Pullup)

Figure 8-25 shows the input structure for the logic level pin, nSCS. The input can be driven with a voltage or
external resistor.

AVDD
AVDD
STATE CONNECTION INPUT
RPU
VIH Tied to AVDD Logic High

VIL Tied to GND Logic Low

ESD

Figure 8-25. Logic nSCC

8.3.10.3 Open Drain Pin

Figure 8-26 shows the structure of the open-drain output pins, nFAULT, FGOUT and SDO in open drain mode.
The open-drain output requires an external pullup resistor to function properly.Figure 8-26 also shows the status
table of nFAULT pin during different device state.

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AVDD

STATE STATUS
RPU
No Fault Pulled-Up
OUTPUT
Fault Pulled-Down
ESD Inactive

Active

Figure 8-26. Open Drain

8.3.10.4 Push Pull Pin

Figure 8-27 shows the structure of SDO in push-pull mode.
AVDD

STATE STATUS

VOH Pulled-Up
OUTPUT
VOL Pulled-Down
ESD Logic High

Logic Low

Figure 8-27. Push Pull

8.3.10.5 Four Level Input Pin

Figure 8-28 shows the structure of the four level input pin, SLEW on hardware interface devices. The input can
be set with an external resistor.

CONTROL

AVDD AVDD
STATE RESISTANCE Setting-1
+
VL1 Tied to AGND
RPU ±
Hi-Z (>2000 kŸ WR Setting-2
VL2
AGND)
+
47 NŸ “5% RPD
VL3
to AVDD ±
Setting-3
VL4 Tied to AVDD
+

±
Setting-4

Figure 8-28. Four Level Input Pin Structure

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8.3.10.6 Seven Level Input Pin

Figure 8-29 shows the structure of the seven level input pins, ADVANCE and MODE, on hardware interface
devices. The input can be set with an external resistor.

CONTROL

Setting-1
+

±
STATE RESISTANCE
Setting-2
VL1 Tied to AGND AVDD +
AVDD
±
22 k ± 5%
VL2
to AGND Setting-3

100 k ± 5% RPU +
VL3
to AGND
±
Hi-Z (>2000 kŸ
VL4 Setting-4
to AGND) RPD
+
100 k ± 5%
VL5
to AVDD ±
Latch
22 NŸ “5% Setting-5
VL6
to AVDD
+

VL7 Tied to AVDD ±

Setting-6
+

±
Setting-7

Figure 8-29. Seven Level Input Pin Structure

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8.3.11 Active Demagnetization

MCT8315Z family of devices has smart rectification features (active demagnetization) which decreases power
losses in the device by reducing diode conduction losses. When this feature is enabled, the device automatically
turns ON the corresponding MOSFET whenever it detects diode conduction. This feature can be configured
with the MODE pins in hardware variants. In SPI device variants this can be configured through EN_ASR and
EN_AAR bits. The smart rectification is classified into two categories of automatic synchronous rectification
(ASR) mode and automatic asynchronous rectification (AAR) mode which are described in sections below.

Note
In SPI device variants both bits, EN_ASR and EN_AAR needs to set to 1 to enable active
demagnetization.

The MCT8315Z device includes a high-side (AD_HS) and low-side (AD_LS) comparator which detects the
negative flow of current in the device on each half-bridge. The AD_HS comparator compares the sense-FET
output with the supply voltage (VM) threshold, whereas the AD_LS comparator compares with the ground (0-V)
threshold. Depending upon the flow of current from OUTx to VM or PGND to OUTx, the AD_HS or the AD_LS
comparator trips. This comparator provides a reference point for the operation of active demagnetization feature.

VM
AD_HS
Comparator

(To Digital) + Sense

- FET

VM OUTX

+ Sense
(To Digital)
- FET
AD_LS
Comparator
0V (GND)

PGND
VREF I/V Converter
SOX

GAIN

Figure 8-30. Active Demagnetization Operation

Table 8-7 shows the configuration of ASR and AAR mode in theMCT8315Z device.
Table 8-7. PWM_MODE Configuration
MODE Pin ASR and AAR
MODE Type Hall Configuration Modulation ASR and AAR Mode
(Hardware Variant) configuration
EN_ASR = 0, ASR and AAR
Mode 1 Connected to AGND Analog Hall Input Asynchronous
EN_AAR = 0 Disabled
Connected to AGND EN_ASR = 0, ASR and AAR
Mode 2 Digital Hall Input Asynchronous
with RMODE1 EN_AAR = 0 Disabled
Connected to AGND EN_ASR = 0, ASR and AAR
Mode 3 Analog Hall Input Synchronous
with RMODE2 EN_AAR = 0 Disabled
EN_ASR = 0, ASR and AAR
Mode 4 Hi-Z Digital Hall Input Synchronous
EN_AAR = 0 Disabled
Connected to AVDD EN_ASR = 1, ASR and AAR
Mode 5 Analog Hall Input Synchronous
with RMODE2 EN_AAR = 1 Enabled

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Table 8-7. PWM_MODE Configuration (continued)

MODE Pin ASR and AAR
MODE Type Hall Configuration Modulation ASR and AAR Mode
(Hardware Variant) configuration
Connected to AVDD
Mode 6 EN_ASR = 1, ASR and AAR
with RMODE1 Digital Hall Input Synchronous
EN_AAR = 1 Enabled
Mode 7 Connected to AVDD

8.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)

The automatic synchronous rectification (ASR) mode is divided into two categories of ASR during commutation
and ASR during PWM mode.
8.3.11.1.1 Automatic Synchronous Rectification in Commutation
Figure 8-31 shows the operation of active demagnetization during the BLDC motor commutation. As shown
in Figure 8-31 (a), the current is flowing from HA to LC in one commutation state. During the commutation
changeover as shown in Figure 8-31 (b), the HC switch is turned on, whereas the commutation current (due to
motor inductance) in OUTA flows through the body diode of LA. This incorporates a higher diode loss depending
on the commutation current. This commutation loss is reduced by turning on the LA for the commutation time as
shown in Figure 8-31 (c).
Similarly the operation of high-side FET is realized in Figure 8-31 (d), (e) and (f).

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VM VM

HA HB HC HA HB HC

OUTA OUTA
OUTB OUTB
OUTC OUTC

LA LB LC LA LB LC

(a) Current flowing from HA to LC (d) Current flowing from HC to LA

VM VM

Decay Current Decay Current

HA HB HC HA HB HC

OUTA OUTA
OUTB OUTB
OUTC OUTC

LA LB LC LA LB LC

(b) Decay current with AD disabled (e) Decay current with AD disabled

VM VM

Decay Current Decay Current

HA HB HC HA HB HC

OUTA OUTA
OUTB OUTB
OUTC OUTC

LA LB LC LA LB LC

(c) Decay current with AD enabled (f) Decay current with AD enabled

Figure 8-31. ASR in BLDC Motor Commutation

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Figure 8-32 (a) shows the BLDC motor phase current waveforms for automatic synchronous rectification mode
in BLDC motor operating with trapezoidal commutation. This figure shows the operation of various switches in a
single commutation cycle.
Figure 8-32 (b) shows the zoomed waveform of commutation cycle with details on the ASR mode start with
margin time (tmargin) and ASR mode early stop due to active demagnetization comparator threshold and delays.

Current Limit

3KDVH µ$¶
Current

LA HA

HA, LB HA, LC HB, LC HB, LA HC, LA HC, LB

(a) &RPPXWDWLRQ FXUUHQW RI 3KDVH ³$´

tmargin

tdead

HA Conducts
LA Body Diode
Conducts
HA Body Diode
3KDVH µ$¶ Conducts
Current
LA Conducts

tdead

HA, LC HB, LC HC, LA HC, LB

(b) Zoomed waveform of Active Demagnetization

Figure 8-32. Current Waveforms for ASR in BLDC Motor Commutation

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8.3.11.1.2 Automatic Synchronous Rectification in PWM Mode

Figure 8-33 shows the operation of ASR in PWM mode. As shown in this figure, a PWM is applied only on
the high-side FET, whereas the low-side FET is always off. During the PWM off time, current decays from the
low-side FET which results in higher power losses. Therefore, this mode supports turning on the low-side FET
during the low-side diode conduction.

PWM_HS
(Applied) &t

PWM_LS
(Applied) &t

PWM_HS
(Actual) &t

PWM_LS
(Actual)
&t

Ia
&t

ASR Mode Disabled ASR Mode Enabled

Figure 8-33. ASR in PWM Mode

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8.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)

Figure 8-34 shows the operation of AAR in PWM mode. As shown in this figure, a PWM is applied in a
synchronous rectification to the high-side and low-side FETs. During the low-side FET conduction, for lower
inductance motors, the current can decay to zero and becomes negative since low side FET is in on-state. This
creates a negative torque on the BLDC motor operation. When AAR mode is enabled, the current during the
decay is monitored and the low-side FET is turned off as soon as the current reaches near to zero. This saves
the negative current building in the BLDC motor which results in better noise performance and better thermal
management.

PWM_HS
(Applied) &t

PWM_LS
(Applied) &t

PWM_HS
(Actual) &t

PWM_LS
(Actual)
&t

Ia
&t

AAR Mode Disabled AAR Mode Enabled

Figure 8-34. AAR in PWM Mode

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8.3.12 Cycle-by-Cycle Current Limit

The current-limit circuit activates if the current flowing through the low-side MOSFET exceeds the ILIMIT current.
This feature restricts motor current to less than the ILIMIT.
The current-limit circuitry utilizes the current sense amplifier output of the three phases and compares that
voltage with the voltage at ILIM pin. Figure 8-35 shows the implementation of current limit circuitry. As shown
in this figure, the output of current sense amplifiers is combined with star connected resistive network. This
measured voltage VMEAS is compared with the external reference voltage VILIM applied at ILIM pin to realize the
current limit implementation. The relation between current sensed on OUTX pin and VMEAS threshold is given as:

8
8/'#5 = @ #8&& W2A F k:+176# + +176$ + +176% ; × )#+0¤3o
(5)

where
• AVDD is 3.3-V LDO output
• OUTX is current flowing into the low-side MOSFET
• GAIN is 0.24-V/A
The ILIMIT threshold can be adjusted by configuring ILIM pin between AVDD/2 to (AVDD/2 - 0.32) V. AVDD/2 is
minimum value and when it is applied on ILIM pin cycle by cycle current limit is disabled, whereas maximum
threshold of 4-A can be configured by applying (AVDD/2 - 0.32) V on ILIM pin.

VM

AVDD OUTA

GAIN Sense
I/V Converter
FET

PGND

SOB SOA
To PWM
VMEAS Controller
-
VILIM +

ILIM
SOC

Figure 8-35. Current Limit Implementation

When the current limit threshold is hit, the high-side FET is disabled until the beginning of the next PWM
cycle as shown in Figure 8-36. The low-side FETs can operate in brake mode or Hi-Z mode by configuring the
ILIM_RECIR bit in the SPI device variant.

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PWM

OUTx

ILIMIT

Bridge Operating in
Brake Mode

IBRIDGE

Time

Figure 8-36. Cycle-by-Cycle Current-Limit Operation

In the MCT8315Z device, when the current limit activates in synchronous rectification mode, the current
recirculates through the low-side FETs while the high-side FETs are disabled as shown in Figure 8-37
Moreover, when the current limit activates in asynchronous rectification mode, the current recirculates through
the body diodes of the low-side FETs while the high-side FETs are disabled as shown in Figure 8-38

VM
VM

HA
X X X HB

OUTA
HC
HA
X X X
HB HC

OUTB OUTA
OUTC OUTB
OUTC
LA LB LC
LA
X X X
LB LC

Figure 8-37. Brake State Figure 8-38. Coast State

Note
The current-limit circuit is ignored immediately after the PWM signal goes active for a short blanking
time to prevent false trips of the current-limit circuit.

Note
During the brake operation, a high-current can flow through the low-side FETs which can eventually
trigger the over current protection circuit. This allows the body-diode of the high-side FET to conduct
and pump brake energy to the VM supply rail.

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8.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
In case of 100% duty cycle applied on PWM input, there is no edge available to turn high-side FET back on. To
overcome this problem, MCT8315Z has built in internal PWM clock which is used to turn high-side FET back on
once it is disabled after exceeding ILIMIT threshold. In SPI variant MCT8315Z, this internal PWM clock can be
configured to either 20 kHz or 40 kHz through PWM_100_DUTY_SEL. In HW variants, MCT8315Z PWM internal
clock is set to 20 kHz. Figure 8-39 shows operation with 100 % duty cycle.

PWM

Internal
PWM

OUTx

ILIMIT

Bridge Operating in
Brake Mode

Time

Figure 8-39. Cycle-by-Cycle Current-Limit Operation with 100% PWM Duty Cycle

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8.3.13 Hall Comparators (Analog Hall Inputs)

Three comparators are provided to process the raw signals from the Hall-effect sensors to commutate the motor.
The Hall comparators sense the zero crossings of the differential inputs and pass the information to digital logic.
The Hall comparators have hysteresis, and their detect threshold is centered at 0-V. The hysteresis is defined as
shown in Figure 8-40.
In addition to the hysteresis, the Hall inputs are deglitched with a circuit that ignores any extra Hall transitions for
a period of tHDG after sensing a valid transition. Ignoring these transitions for the tHDG time prevents PWM noise
from being coupled into the Hall inputs, which can result in erroneous commutation.
If excessive noise is still coupled into the Hall comparator inputs, adding capacitors between the positive and
negative inputs of the Hall comparators may be required. The ESD protection circuitry on the Hall inputs
implements a diode to the AVDD pin. Because of this diode, the voltage on the Hall inputs should not exceed the
AVDD voltage.
Because the AVDD pin is disabled in sleep mode (nSLEEP inactive), the Hall inputs should not be driven by
external voltages in sleep mode. If the Hall sensors are powered externally, the supply to the Hall sensors should
be disabled if the MCT8315Z device is put into sleep mode. In addition, the Hall sensors' power supply should
be powered up after enabling the motor otherwise an invalid Hall state may cause a delay in motor operation.

Hall Differential
VHYS/2 Voltage (VID/2)

Hall Comparator
Common Mode
Voltage (VCM)

Hall Comparator
Output tHDEG (Hall
Deglitch Time)
Time

Figure 8-40. Hall Comparators Operation

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8.3.14 Advance Angle

The MCT8315Z includes an advance angle feature to advance the commutation by a specified electrical angle
based on the voltage on the ADVANCE pin (in HW device variant) or the ADVANCE_LVL bits (in SPI variant).
Figure 8-41 shows the operation of advance angle feature.

Hall A
&t

Hall B
&t

Hall C
&t

Van Before Advance

ia After Advance

0
&t
Advance
Angle

Vbn
ib

0
&t
2Œ/3

Vcn
ic
0
&t
2Œ/3

HA, LB HA, LC HB, LC HB, LA HC, LA HC, LB

2Π&t

Figure 8-41. Advance Angle

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8.3.15 FGOUT Signal

The MCT8315Z device also has an open-drain FGOUT signal that can be used for closed-loop speed control
of a BLDC motor. This signal includes the information of all three Hall-elements inputs as shown in Figure 8-42.
In the MCT8315ZR (SPI variant), FGOUT can be configured to be a different division factor of Hall signals as
shown in Figure 8-42. In the MCT8315ZH/T (hardware variant), the default mode is FGOUT_SEL = 00b.

Hall Input
(HPA, HNA)

Hall Input
(HPB, HNB)

Hall Input
(HPC, HNC)

Hall Comparator
Output (HA) /
Digital Hall Input

Hall Comparator
Output (HB) /
Digital Hall Input

Hall Comparator
Output (HC) /
Digital Hall Input

FGOUT
(FGOUT_SEL =
00b)

FGOUT
(FGOUT_SEL =
01b)

FGOUT
(FGOUT_SEL =
10b)

FGOUT
(FGOUT_SEL =
11b) Time

Figure 8-42. FGOUT Signal

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8.3.16 Protections
The MCT8315Z devices are protected against VM, AVDD, charge pump and buck undervoltage, VM
overvoltage, buck and FET overcurrent, motor lock, SPI and OTP error and over temperature events. Table
8-8 summarizes various faults details.
Table 8-8. Fault Action and Response (SPI Devices)
FAULT CONDITION CONFIGURATION REPORT FETs LOGIC RECOVERY
Automatic:
VM undervoltage VVM > VUVLO (rising)
VVM < VUVLO (falling) — — Hi-Z Disabled
(NPOR) CLR_FLT, nSLEEP Reset Pulse (NPOR
bit)
Automatic:
AVDD undervoltage VAVDD > VAVDD_UV (rising)
VAVDD < VAVDD_UV (falling) — — Hi-Z Disabled
(NPOR) CLR_FLT, nSLEEP Reset Pulse (NPOR
bit)
Automatic:
Buck undervoltage VFB_BK > VBUCK_UV (rising)
VFB_BK < VBK_UV (falling) — nFAULT Active Active
(BUCK_UV) CLR_FLT, nSLEEP Reset Pulse
(BUCK_UV bit)
Automatic:
Charge pump
VVCP > VCPUV (rising)
undervoltage VCP < VCPUV (falling) — nFAULT Hi-Z Active
CLR_FLT, nSLEEP Reset Pulse
(VCP_UV)
(VCP_UV bit)
OVP_EN = 0b None Active Active No action (OVP Disabled)
Overvoltage
Protection VVM > VOVP (rising) Automatic:
(OVP) OVP_EN = 1b nFAULT Hi-Z Active VVM < VOVP (falling)
CLR_FLT, nSLEEP Reset Pulse (OVP bit)
Latched:
Overcurrent OCP_MODE = 00b nFAULT Hi-Z Active CLR_FLT, nSLEEP Reset Pulse (OCP
Protection IPHASE > IOCP bits)
(OCP) Retry:
OCP_MODE = 01b nFAULT Hi-Z Active
tRETRY
Buck Overcurrent
Retry:
Protection IBK > IBK_OCP — nFAULT Active Active
tBK_RETRY
(BUCK_OCP)
Automatic:
SPI Error SCLK fault and ADDR SPI_FLT_REP = 0b nFAULT Active Active CLR_FLT, nSLEEP Reset Pulse
(SPI_FLT) fault (SPI_FLT bit)
SPI_FLT_REP = 1b None Active Active No action
OTP Error Latched:
OTP reading is erroneous — nFAULT Hi-Z Active
(OTP_ERR) Power Cycle, nSLEEP Reset Pulse
Latched:
MTR_LOCK_MODE = 00b nFAULT Hi-Z Active CLR_FLT, nSLEEP Pulse (MTR_LOCK
bit)
Retry:
Motor Lock No hall signals > MTR_LOCK_MODE = 01b nFAULT Hi-Z Active
tMTR_LOCK_RETRY
(MTR_LOCK) tMTR_LOCK_TDET
Automatic:
MTR_LOCK_MODE = 10b nFAULT Active Active CLR_FLT, nSLEEP Reset Pulse (OCP
bits)
MTR_LOCK_MODE = 11b None Active Active No action
OTW_REP = 0b None Active Active No action
Thermal warning Automatic:
TJ > TOTW
(OTW) OTW_REP = 1b nFAULT Active Active TJ < TOTW – TOTW_HYS
CLR_FLT, nSLEEP Pulse (OTW bit)
Thermal shutdown Automatic:
TJ > TTSD — nFAULT Hi-Z Active
(TSD) TJ < TTSD – TTSD_HYS
Automatic:
Thermal shutdown
TJ > TTSD_FET — nFAULT Hi-Z Active TJ < TTSD_FET – TTSD_FET_HYS
(TSD_FET)
CLR_FLT, nSLEEP Pulse (OTS bit)

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8.3.16.1 VM Supply Undervoltage Lockout (NPOR)

If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold (VM UVLO falling
threshold), all of the integrated FETs, driver charge-pump and digital logic controller are disabled as shown in
Figure 8-43. Normal operation resumes (driver operation) when the VM undervoltage condition is removed. The
NPOR bit is reset and latched low in the IC status (IC_STAT) register once the device presumes VM. The NPOR
bit remains in reset condition until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST).

VUVLO (max) rising

VUVLO (min) rising

VUVLO (max) falling

VUVLO (min) falling VVM

DEVICE ON DEVICE OFF DEVICE ON

Time

Figure 8-43. VM Supply Undervoltage Lockout

8.3.16.2 AVDD Undervoltage Lockout (AVDD_UV)

If at any time the voltage on AVDD pin falls lower than the VAVDD_UV threshold, all of the integrated FETs, driver
charge-pump and digital logic controller are disabled. Normal operation resumes (driver operation) when the
AVDD undervoltage condition is removed. The NPOR bit is reset and latched low in the IC status (IC_STAT)
register once the device presumes VM. The NPOR bit remains in reset condition until cleared through the
CLR_FLT bit or an nSLEEP pin reset pulse (tRST).
8.3.16.3 Buck Undervoltage Lockout (BUCK_UV)
If at any time the voltage on VFB_BK pin falls lower than the VBK_UV threshold, the nFAULT pin is driven low and
the BK_FLT bit in IC_STAT register is set while the driver FETs, charge pump, and digital logic control continue
to operate normally. The FAULT and BUCK_UV bits are also latched high in the status registers. Normal
operation starts again (buck regulator operation and the nFAULT pin is released) when the buck undervoltage
condition clears. The BK_FLT and BUCK_UV bits stay set until cleared through the CLR_FLT bit or an nSLEEP
pin reset pulse (tRST).
8.3.16.4 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls lower than the VCPUV threshold voltage of the
charge pump, all of the integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and VCP_UV
bits are also latched high in the registers on SPI devices. Normal operation starts again (driver operation and
the nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set until cleared
through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST). The CPUV protection is always enabled in both
hardware and SPI device varaints.
8.3.16.5 Overvoltage Protection (OVP)
If at any time input supply voltage on the VM pins rises higher lower than the VOVP threshold voltage, all of the
integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and OVP bits are also latched high
in the registers on SPI devices. Normal operation starts again (driver operation and the nFAULT pin is released)
when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin

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reset pulse (tRST). Setting the OVP_EN bit high on the SPI devices enables this protection feature. The OVP
threshold is programmable on the SPI variant and can be set to 22-V or 34-V based on the OVP_SEL bit. In
hardware variant, the OVP protection is always enabled and set to a 34-V threshold.

VVM

VOVP (max) rising

VOVP (min) rising

VOVP (max) falling

VOVP (min) falling

DEVICE ON DEVICE OFF DEVICE ON

nFAULT
Time

Figure 8-44. Over Voltage Protection

8.3.16.6 Overcurrent Protection (OCP)

A MOSFET overcurrent event is sensed by monitoring the current flowing through FETs. If the current across
a FET exceeds the IOCP threshold for longer than the tOCP deglitch time, an OCP event is recognized and
action is done according to the OCP_MODE bit. On hardware interface devices, the IOCP threshold is fixed at
9-A threshold, the tOCP_DEG is fixed at 0.6-µs, and the OCP_MODE bit is configured for latched shutdown. On
SPI devices, the IOCP threshold is set through OCP_LVL, the tOCP_DEG is set through the OCP_DEG, and the
OCP_MODE bit can operate in four different modes: OCP latched shutdown, OCP automatic retry, OCP report
only, and OCP disabled.
8.3.16.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
After a OCP event in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,
and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again (driver
operation and the nFAULT pin is released) when the OCP condition clears and a clear faults command is issued
either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).

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Peak Current due

to deglitch time

IOCP

IOUTx

tOCP

nFAULT Pulled High Fault Condition nFAULT Released

nFAULT
Time Clear Fault

Figure 8-45. Overcurrent Protection - Latched Shutdown Mode

8.3.16.6.2 OCP Automatic Retry (OCP_MODE = 01b)

After a OCP event in this mode, all the FETs are disabled and the nFAULT pin is driven low. The FAULT,
OCP, and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again
automatically (driver operation and the nFAULT pin is released) after the tRETRY time elapses. After the tRETRY
time elapses, the FAULT, OCP, and corresponding FET's OCP bits stay latched until a clear faults command is
issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).

Peak Current due

to deglitch time

IOCP

IOUTx

tOCP tRETRY

nFAULT Pulled High Fault Condition nFAULT Released

nFAULT
Time

Figure 8-46. Overcurrent Protection - Automatic Retry Mode

8.3.16.7 Buck Overcurrent Protection

A buck overcurrent event is sensed by monitoring the current flowing through buck regulator’s FETs. If the
current across the buck regulator FET exceeds the IBK_OCP threshold for longer than the tBK_OCP deglitch time,
an OCP event is recognized. The buck OCP mode is configured in automatic retry setting. In this setting, after

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a buck OCP event is detected, all the buck regulator’s FETs are disabled and the nFAULT pin is driven low.
The FAULT, BK_FLT, and BUCK_OCP bits are latched high in the SPI registers. Normal operation starts again
automatically (driver operation and the nFAULT pin is released) after the tBK_RETRY time elapses. The FAULT,
BK_FLT, and BUCK_OCP bits stay latched until the tBK_RETRY period expires.
8.3.16.8 Motor Lock (MTR_LOCK)
During motor is in lock condition the hall signals will be not available, so a Motor Lock event is sensed by
monitoring the hall signals. If the hall signals are not present for for longer than the tMTR_LOCK, a MTR_LCK event
is recognized and action is done according to the MTR_LOCK_MODE bits. On hardware interface devices, the
tMTR_LOCK threshold is set to 1000-ms, and the MTR_LOCK_MODE bit is configured for latched shutdown. On
SPI devices, the tMTR_LOCK threshold is set through the MTR_LOCK_TDET register and the MTR_LOCK_MODE
bit can operate in four different modes: MTR_LOCK latched shutdown, MTR_LOCK automatic retry, MTR_LOCK
report only, and MTR_LOCK disabled.
8.3.16.8.1 MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)
After a motor lock event in this mode, all FETs are disabled and the nFAULT pin is driven low. The FAULT and
MTR_LOCK bits are latched high in the SPI registers. Normal operation starts again (driver operation and the
nFAULT pin is released) when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP
reset pulse (tRST).
8.3.16.8.2 MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b)
After a motor lock event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven
low. The FAULT and MTR_LOCK bits are latched high in the SPI registers. Normal operation starts again
automatically (driver operation and the nFAULT pin is released) after the tMTR_LOCK_RETRY time elapses. The
FAULT and MTR_LOCK bits stay latched until the tMTR_LOCK_RETRY period expires.
8.3.16.8.3 MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)
No protective action occurs after a MTR_LOCK event in this mode. The motor lock event is reported by driving
the nFAULT pin low and latching the FAULT and MTR_LOCK bits high in the SPI registers. The MCT8315Z
continues to operate as usual. The external controller manages the motor lock condition by acting appropriately.
The reporting clears (nFAULT pin is released) when a clear faults command is issued either through the
CLR_FLT bit or an nSLEEP reset pulse (tRST).
8.3.16.8.4 MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)
No action occurs after a MTR_LOCK event in this mode.
8.3.16.8.5

Note
The motor lock detection scheme requires the PWM off-time (tPWM_OFF) to be lower than the motor
lock detection time (tMTR_LOCK)

8.3.16.9 Thermal Warning (OTW)

If the die temperature exceeds the trip point of the thermal warning (TOTW), the OT bit in the IC status (IC_STAT)
register and OTW bit in the status register is set. The reporting of OTW on the nFAULT pin can be enabled by
setting the over-temperature warning reporting (OTW_REP) bit in the configuration control register. The device
performs no additional action and continues to function. In this case, the nFAULT pin releases when the die
temperature decreases below the hysteresis point of the thermal warning (TOTW - TOTW_HYS). The OTW bit
remains set until cleared through the CLR_FLT bit or an nSLEEP reset pulse (tRST) and the die temperature is
lower than thermal warning trip (TOTW).
8.3.16.10 Thermal Shutdown (OTSD)
MCT8315Z has 2 die temperature sensor for thermal shutdown, one of them near FETs and other one in other
part of die.

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8.3.16.10.1 OTSD FET

If the die temperature near FET exceeds the trip point of the thermal shutdown limit (TTSD_FET), all the FETs
are disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and OT
bit in the IC status (IC_STAT) register and OTS bit in the status register is set. Normal operation starts again
(driver operation and the nFAULT pin is released) when the overtemperature condition clears. The OTS bit stays
latched high indicating that a thermal event occurred until a clear fault command is issued either through the
CLR_FLT bit or an nSLEEP reset pulse (tRST). This protection feature cannot be disabled.
8.3.16.10.2 OTSD (Non-FET)
If the die temperature in the device exceeds the trip point of the thermal shutdown limit (TTSD), all the FETs
are disabled, the buck regulator disabled, the charge pump is shut down, and the nFAULT pin is driven low.
In addition, the FAULT and OT bit in the IC status (IC_STAT) register and OTS bit in the status register is
set. Normal operation starts again (driver operation and the nFAULT pin is released) when the overtemperature
condition clears. The OTS bit stays latched high indicating that a thermal event occurred until a clear fault
command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST). This protection feature
cannot be disabled.

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8.4 Device Functional Modes

8.4.1 Functional Modes
8.4.1.1 Sleep Mode
The nSLEEP pin manages the state of the MCT8315Z family of devices. When the nSLEEP pin is low, the
device goes to a low-power sleep mode. In sleep mode, all FETs are disabled, current sense amplifiers are
disabled, buck regulator (if present) is disabled, the charge pump is disabled, the AVDD regulator is disabled,
and the SPI bus is disabled. The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the
device goes to sleep mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high.
The tWAKE time must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all MOSFETs are disabled.

Note
During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low
as the internal regulators are enabled or disabled. After the regulators have enabled or disabled, the
nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the
tSLEEP or tWAKE time.

Note
TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into
internal test mode. If external supply is used to pull up nFAULT, make sure that it is pulled to >2.2 V on
power up or the device will enter internal test mode.

8.4.1.2 Operating Mode

When the nSLEEP pin is high and the VVM voltage is greater than the VUVLO voltage, the device goes to
operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the charge
pump, AVDD regulator, buck regulator, and SPI bus are active.
8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
In the case of device latched faults, the MCT8315Z family of devices goes to a partial shutdown state to help
protect the power MOSFETs and system.
When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT bit
to 1b in the SPI variant or issuing a reset pulse to the nSLEEP pin on either variant. The nSLEEP reset pulse
(tRST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence should
fall within the tRST time window or else the device will start the complete shutdown sequence (low power sleep
mode). The reset pulse has no effect on any of the regulators, device settings, or other functional blocks.
8.4.2 DRVOFF
MCT8315Z has capability to disable pre-driver and MOSFETs bypassing the digital through DRVOFF pin. When
DRVOFF pin is pulled high, all six MOSFETs are disabled (Hi-Z). If nSLEEP is high when the DRVOFF pin is
high, the charge pump, AVDD regulator, buck regulator, and SPI bus are active and any driver-related faults
such as OCP will be inactive. DRVOFF pin independently disables MOSFETs which will stop motor commutation
irrespective of status of PWM, HPx and HNx pins.

Note
Since DRVOFF pin independently disables the MOSFETs bypassing digital logic, it can trigger fault
detection resulting in nFAULT getting pulled low.

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8.5 SPI Communication

8.5.1 Programming
On MCT8315Z SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in secondary mode and connects to a controller. The SPI input data
(SDI) word consists of a 16-bit word, with a 6-bit address and 8 bits of data. The SPI output consists of 16 bit
word, with a 8 bits of status information (STAT register) and 8-bit register data.
A valid frame must meet the following conditions:
• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin should be pulled high for at least 400 ns between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
placed in the Hi-Z state.
• Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK
pin.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 8-bit status data.
The SPI registers are reset to the default settings on power up and when the device is enters sleep mode
8.5.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit B15)
• 6 address bits, A (bits B14 through B9)
• Parity bit, P (bit B8). Parity bit is set such that the SDI input data word has even number of 1s and 0s
• 8 data bits, D (bits B7 through B0)
The SDO output data word is 16 bits long and the first 8 bits are status bits. The data word is the content of the
register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.

nSCS

A1 D1
SDI

SDO
S1 R1

Figure 8-47.

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Master Controller
Device

MCLK SCLK

MO SDI
SPI
SPI SDO Communication
MI
Communication
nSCS
CS

Figure 8-48.

Table 8-9. SDI Input Data Word Format

R/W ADDRESS Parity DATA
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
W0 A5 A4 A3 A2 A1 A0 P D7 D6 D5 D4 D3 D2 D1 D0

Table 8-10. SDO Output Data Word Format

STATUS DATA
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0

nSCS

SCLK

SDI X MSB LSB X

SDO Z MSB LSB Z

Capture
Point

Propagate
Point

Figure 8-49. SPI Secondary Timing Diagram

SPI Error Handling

SPI Frame Error (SPI_SCLK_FLT: If the nSCS gets deasserted before the end of 16-bit frame, SPI frame error
is detected and SPI_SCLK_FLT bit is set in STAT2. The SPI_SCLK_FLT status bit is latched and can be cleared
when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse

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SPI Address Error (SPI_ADDR_FLT): If an invalid address is provided in the ADDR field of the input SPI
data on SDI, SPI address error is detected and SPI_ADDR_FLT bit in STAT2 is set. Invalid address is any
address that is not defined in Register Map i.e. address not falling in the range of address 0x0 to 0xC. The
SPI_ADDR_FLT status bit is latched and can be cleared when a clear faults command is issued either through
the CLR_FLT bit or an nSLEEP reset pulse

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8.6 Register Map

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8.6.1 STATUS Registers

Table 8-11 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in
Table 8-11 should be considered as reserved locations and the register contents should not be modified.
Table 8-11. STATUS Registers
Offset Acronym Register Name Section
0h IC Status Register IC Status Register Section 8.6.1.1
1h Status Register 1 Status Register 1 Section 8.6.1.2
2h Status Register 2 Status Register 2 Section 8.6.1.3

Complex bit access types are encoded to fit into small table cells. Table 8-12 shows the codes that are used for
access types in this section.
Table 8-12. STATUS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Reset or Default Value
-n Value after reset or the default
value

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8.6.1.1 IC Status Register (Offset = 0h) [Reset = 00h]

IC Status Register is shown in Table 8-13.
Return to the Summary Table.
Table 8-13. IC Status Register Field Descriptions
Bit Field Type Reset Description
7 MTR_LOCK R 0h Motor Lock Status Bit
0h = No motor lock is detected
1h = Motor lock is detected
6 BK_FLT R 0h Buck Fault Bit
0h = No buck regulator fault condition is detected
1h = Buck regulator fault condition is detected
5 SPI_FLT R 0h SPI Fault Bit
0h = No SPI fault condition is detected
1h = SPI Fault condition is detected
4 OCP R 0h Over Current Protection Status Bit
0h = No overcurrent condition is detected
1h = Overcurrent condition is detected
3 NPOR R 0h Supply Power On Reset Bit
0h = Power on reset condition is detected on VM
1h = No power-on-reset condition is detected on VM
2 OVP R 0h Supply Overvoltage Protection Status Bit
0h = No overvoltage condition is detected on VM
1h = Overvoltage condition is detected on VM
1 OT R 0h Overtemperature Fault Status Bit
0h = No overtemperature warning / shutdown is detected
1h = Overtemperature warning / shutdown is detected
0 FAULT R 0h Device Fault Bit
0h = No fault condition is detected
1h = Fault condition is detected

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8.6.1.2 Status Register 1 (Offset = 1h) [Reset = 00h]

Status Register 1 is shown in Table 8-14.
Return to the Summary Table.
Table 8-14. Status Register 1 Field Descriptions
Bit Field Type Reset Description
7 OTW R 0h Overtemperature Warning Status Bit
0h = No overtemperature warning is detected
1h = Overtemperature warning is detected
6 OTS R 0h Overtemperature Shutdown Status Bit
0h = No overtemperature shutdown is detected
1h = Overtemperature shutdown is detected
5 OCP_HC R 0h Overcurrent Status on High-side switch of OUTC
0h = No overcurrent detected on high-side switch of OUTC
1h = Overcurrent detected on high-side switch of OUTC
4 OCL_LC R 0h Overcurrent Status on Low-side switch of OUTC
0h = No overcurrent detected on low-side switch of OUTC
1h = Overcurrent detected on low-side switch of OUTC
3 OCP_HB R 0h Overcurrent Status on High-side switch of OUTB
0h = No overcurrent detected on high-side switch of OUTB
1h = Overcurrent detected on high-side switch of OUTB
2 OCP_LB R 0h Overcurrent Status on Low-side switch of OUTB
0h = No overcurrent detected on low-side switch of OUTB
1h = Overcurrent detected on low-side switch of OUTB
1 OCP_HA R 0h Overcurrent Status on High-side switch of OUTA
0h = No overcurrent detected on high-side switch of OUTA
1h = Overcurrent detected on high-side switch of OUTA
0 OCP_LA R 0h Overcurrent Status on Low-side switch of OUTA
0h = No overcurrent detected on low-side switch of OUTA
1h = Overcurrent detected on low-side switch of OUTA

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8.6.1.3 Status Register 2 (Offset = 2h) [Reset = 00h]

Status Register 2 is shown in Table 8-15.
Return to the Summary Table.
Table 8-15. Status Register 2 Field Descriptions
Bit Field Type Reset Description
7 RESERVED R-0 0h Reserved
6 OTP_ERR R 0h One Time Programmability Error
0h = No OTP error is detected
1h = OTP Error is detected
5 BUCK_OCP R 0h Buck Regulator Overcurrent Status Bit
0h = No buck regulator overcurrent is detected
1h = Buck regulator overcurrent is detected
4 BUCK_UV R 0h Buck Regulator Undervoltage Status Bit
0h = No buck regulator undervoltage is detected
1h = Buck regulator undervoltage is detected
3 VCP_UV R 0h Charge Pump Undervoltage Status Bit
0h = No charge pump undervoltage is detected
1h = Charge pump undervoltage is detected
2 SPI_PARITY R-0 0h SPI Parity Error Bit
0h = No SPI parity error is detected
1h = SPI parity error is detected
1 SPI_SCLK_FLT R 0h SPI Clock Framing Error Bit
0h = No SPI clock framing error is detected
1h = SPI clock framing error is detected
0 SPI_ADDR_FLT R 0h SPI Address Error Bit
0h = No SPI address fault is detected (due to accessing non-user
register)
1h = SPI address fault is detected

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8.6.2 CONTROL Registers

Table 8-16 lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed
in Table 8-16 should be considered as reserved locations and the register contents should not be modified.
Table 8-16. CONTROL Registers
Offset Acronym Register Name Section
3h Control Register 1 Control Register 1 Section 8.6.2.1
4h Control Register 2 Control Register 2 Section 8.6.2.2
5h Control Register 3 Control Register 3 Section 8.6.2.3
6h Control Register 4 Control Register 4 Section 8.6.2.4
7h Control Register 5 Control Register 5 Section 8.6.2.5
8h Control Register 6 Control Register 6 Section 8.6.2.6
9h Control Register 7 Control Register 7 Section 8.6.2.7
Ah Control Register 8 Control Register 8 Section 8.6.2.8
Bh Control Register 9 Control Register 9 Section 8.6.2.9
Ch Control Register 10 Control Register 10 Section 8.6.2.10

Complex bit access types are encoded to fit into small table cells. Table 8-17 shows the codes that are used for
access types in this section.
Table 8-17. CONTROL Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
WAPU W Write
APU Atomic write with password
unlock
Reset or Default Value
-n Value after reset or the default
value

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8.6.2.1 Control Register 1 (Offset = 3h) [Reset = 00h]

Control Register 1 is shown in Table 8-18.
Return to the Summary Table.
Table 8-18. Control Register 1 Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R-0 0h Reserved
2-0 REG_LOCK R/WAPU 0h Register Lock Bits
0h = No effect unless locked or unlocked
1h = No effect unless locked or unlocked
2h = No effect unless locked or unlocked
3h = Write 011b to this register to unlock all registers
4h = No effect unless locked or unlocked
5h = No effect unless locked or unlocked
6h = Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x03h bits 2-0.
7h = No effect unless locked or unlocked

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8.6.2.2 Control Register 2 (Offset = 4h) [Reset = 80h]

Control Register 2 is shown in Table 8-19.
Return to the Summary Table.
Table 8-19. Control Register 2 Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R/W 0h Reserved
5 SDO_MODE R/W 0h SDO Mode Setting
0h = SDO IO in Open Drain Mode
1h = SDO IO in Push Pull Mode
4-3 SLEW R/W 0h Slew Rate Settings
0h = Slew rate is 25 V/µs
1h = Slew rate is 50 V/µs
2h = Slew rate is 125 V/µs
3h = Slew rate is 200 V/µs
2-1 PWM_MODE R/W 0h Device Mode Selection
0h = Asynchronous rectification with analog Hall
1h = Asynchronous rectification with digital Hall
2h = Synchronous rectification with analog Hall
3h = Synchronous rectification with digital Hall
0 CLR_FLT W1C 0h Clear Fault
0h = No clear fault command is issued
1h = To clear the latched fault bits. This bit automatically resets after
being written.

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8.6.2.3 Control Register 3 (Offset = 5h) [Reset = 46h]

Control Register 3 is shown in Table 8-20.
Return to the Summary Table.
Table 8-20. Control Register 3 Field Descriptions
Bit Field Type Reset Description
7 RESERVED R-0 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 PWM_100_DUTY_SEL R/W 0h Frequency of PWM at 100% Duty Cycle
0h = 20KHz
1h = 40KHz
3 OVP_SEL R/W 0h Overvoltage Level Setting
0h = VM overvoltage level is 34-V
1h = VM overvoltage level is 22-V
2 OVP_EN R/W 1h Overvoltage Enable Bit
0h = Overvoltage protection is disabled
1h = Overvoltage protection is enabled
1 SPI_FLT_REP R/W 1h SPI Fault Reporting Disable Bit
0h = SPI fault reporting on nFAULT pin is enabled
1h = SPI fault reporting on nFAULT pin is disabled
0 OTW_REP R/W 0h Overtemperature Warning Reporting Bit
0h = Over temperature reporting on nFAULT is disabled
1h = Over temperature reporting on nFAULT is enabled

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8.6.2.4 Control Register 4 (Offset = 6h) [Reset = 10h]

Control Register 4 is shown in Table 8-21.
Return to the Summary Table.
Table 8-21. Control Register 4 Field Descriptions
Bit Field Type Reset Description
7 DRV_OFF R/W 0h Driver OFF Bit
0h = No Action
1h = Hi-Z FETs
6 OCP_CBC R/W 0h OCP PWM Cycle Operation Bit
0h = OCP clearing in PWM input cycle change is disabled
1h = OCP clearing in PWM input cycle change is enabled
5-4 OCP_DEG R/W 1h OCP Deglitch Time Settings
0h = OCP deglitch time is 0.2 µs
1h = OCP deglitch time is 0.6 µs
2h = OCP deglitch time is 1.2 µs
3h = OCP deglitch time is 1.6 µs
3 OCP_RETRY R/W 0h OCP Retry Time Settings
0h = OCP retry time is 5 ms
1h = OCP retry time is 500 ms
2 OCP_LVL R/W 0h Overcurrent Level Setting
0h = OCP level is 9 A
1h = OCP level is 13 A
1-0 OCP_MODE R/W 0h OCP Fault Mode
0h = Overcurrent causes a latched fault
1h = Overcurrent causes an automatic retrying fault
2h = Reserved
3h = Reserved

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8.6.2.5 Control Register 5 (Offset = 7h) [Reset = 00h]

Control Register 5 is shown in Table 8-22.
Return to the Summary Table.
Table 8-22. Control Register 5 Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 0h Reserved
6 ILIM_RECIR R/W 0h Current Limit Recirculation Settings
0h = Current recirculation through FETs (Brake Mode)
1h = Current recirculation through diodes (Coast Mode)
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 EN_AAR R/W 0h Active Asynchronous Rectification Enable Bit
0h = AAR mode is disabled
1h = AAR mode is enabled
2 EN_ASR R/W 0h Active Synchronous Rectification Enable Bit
0h = ASR mode is disabled
1h = ASR mode is enabled
1-0 RESERVED R/W 0h Reserved

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8.6.2.6 Control Register 6 (Offset = 8h) [Reset = 00h]

Control Register 6 is shown in Table 8-23.
Return to the Summary Table.
Table 8-23. Control Register 6 Field Descriptions
Bit Field Type Reset Description
7-6 RESERVED R-0 0h Reserved
5 RESERVED R/W 0h Reserved
4 BUCK_PS_DIS R/W 0h Buck Power Sequencing Disable Bit
0h = Buck power sequencing is enabled
1h = Buck power sequencing is disabled
3 BUCK_CL R/W 0h Buck Current Limit Setting
0h = Buck regulator current limit is set to 600 mA
1h = Buck regulator current limit is set to 150 mA
2-1 BUCK_SEL R/W 0h Buck Voltage Selection
0h = Buck voltage is 3.3 V
1h = Buck voltage is 5.0 V
2h = Buck voltage is 4.0 V
3h = Buck voltage is 5.7 V
0 BUCK_DIS R/W 0h Buck Disable Bit
0h = Buck regulator is enabled
1h = Buck regulator is disabled

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8.6.2.7 Control Register 7 (Offset = 9h) [Reset = 00h]

Control Register 7 is shown in Table 8-24.
Return to the Summary Table.
Table 8-24. Control Register 7 Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R-0 0h Reserved
4 HALL_HYS R/W 0h Hall Comparator Hysteresis Settings
0h = 5 mV
1h = 50 mV
3 BRAKE_MODE R/W 0h Brake Mode Setting
0h = Device operation is braking in brake mode
1h = Device operation is coasting in brake mode
2 COAST R/W 0h Coast Bit
0h = Device coast mode is disabled
1h = Device coast mode is enabled
1 RESERVED R/W 0h Reserved
0 DIR R/W 0h Direction Bit
0h = Motor direction is set to clockwise direction
1h = Motor direction is set to anti-clockwise direction

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8.6.2.8 Control Register 8 (Offset = Ah) [Reset = 00h]

Control Register 8 is shown in Table 8-25.
Return to the Summary Table.
Table 8-25. Control Register 8 Field Descriptions
Bit Field Type Reset Description
7-6 FGOUT_SEL R/W 0h Electrical Frequency Generation Output Mode Bits
0h = FGOUT frequency is 3x commutation frequency
1h = FGOUT frequency is 1x of commutation frequency
2h = FGOUT frequency is 0.5x of commutation frequency
3h = FGOUT frequency is 0.25x of commutation frequency
5 RESERVED R-0 0h Reserved
4 MTR_LOCK_RETRY R/W 0h Motor Lock Retry Time Settings
0h = 500 ms
1h = 5000 ms
3-2 MTR_LOCK_TDET R/W 0h Motor Lock Detection Time Settings
0h = 300 ms
1h = 500 ms
2h = 1000 ms
3h = 5000 ms
1-0 MTR_LOCK_MODE R/W 0h Motor Lock Fault Options
0h = Motor lock causes a latched fault
1h = Motor lock causes an automatic retrying fault
2h = Motor lock is report only but no action is taken
3h = Motor lock is not reported and no action is taken

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8.6.2.9 Control Register 9 (Offset = Bh) [Reset = 00h]

Control Register 9 is shown in Table 8-26.
Return to the Summary Table.
Table 8-26. Control Register 9 Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R-0 0h Reserved
2-0 ADVANCE_LVL R/W 0h Phase Advance Setting
0h = 0°
1h = 4°
2h = 7°
3h = 11°
4h = 15°
5h = 20°
6h = 25°
7h = 30°

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8.6.2.10 Control Register 10 (Offset = Ch) [Reset = 00h]

Control Register 10 is shown in Table 8-27.
Return to the Summary Table.
Table 8-27. Control Register 10 Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R-0 0h Reserved
4 DLYCMP_EN R/W 0h Driver Delay Compensation enable
0h = Disable
1h = Enable
3-0 DLY_TARGET R/W 0h Delay Target for Driver Delay Compensation
0h = 0 µs
1h = 0.4 µs
2h = 0.6 µs
3h = 0.8 µs
4h = 1 µs
5h = 1.2 µs
6h = 1.4 µs
7h = 1.6 µs
8h = 1.8 µs
9h = 2 µs
Ah = 2.2 µs
Bh = 2.4 µs
Ch = 2.6 µs
Dh = 2.8 µs
Eh = 3 µs
Fh = 3.2 µs

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The MCT8315Z can be used to drive Brushless-DC motors. The following design procedure can be used to
configure the MCT8315Z.

VVM

+
0.1 µF 10 nF 1 µF 0.1 µF 10 µF

VCC CPH CPL CP VM

RCL1

ILIM
AVDD
Microcontroller RCL2
CAVDD
AGND

Replace Resistor (RBK) with Inductor

(LBK) for larger external load or to
RPU1 reduce power dissipa on
LBK
GP-I FGOUT External
Load
SW_BK
RPU2 RBK
CBK
GP-I nFAULT MCT8315ZH GND_BK

Sleep Control nSLEEP

FB_BK
GP-O DRVOFF

GP-O PWM
PWM PWM
Control GP-O DIR Control
Module Input OUTA Hall
GP-O BRAKE Sensors
AVDD
Hall A

OUTB Hall B
ADVANCE
Hall C
SLEW Hardware
MODE interface

OUTC

PGND

HPA HNA HPB HNB HPC HNC

(Optional)

Figure 9-1. Primary Application Schematics for MCT8315ZH (hardware variant with buck)

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Note
For MCT8315ZT (hardware variant without buck), pins 2 and 4 should be left open (floating) while pin
3 should be tied to PGND.

VVM

+
0.1 µF 47 nF 1 µF 0.1 µF 10 µF

VCC CPH CPL CP VM

RCL1

ILIM
AVDD
Microcontroller RCL2
CAVDD
AGND

Replace Resistor (RBK) with Inductor

(LBK) for larger external load or to
RPU1
LBK reduce power dissipa on
GP-I FGOUT External
Load
SW_BK
RPU2 RBK
CBK
GP-I nFAULT MCT8315ZR GND_BK

Sleep Control nSLEEP

FB_BK
GP-O DRVOFF

GP-O PWM
PWM PWM
Control Control
Module Input OUTA Hall
GP-O BRAKE Sensors

Hall A

OUTB Hall B
GP-I SDO
Hall C
GP-O nSCS
SPI SPI
GP-O SCLK

GP-O SDI OUTC

PGND

HPA HNA HPB HNB HPC HNC

(Optional)

Figure 9-2. Primary Application Schematics for MCT8315ZR (SPI variant)

9.2 Hall Sensor Configuration and Connection

The combinations of Hall sensor connections in this section are common connections.
9.2.1 Typical Configuration
The Hall sensor inputs on the MCT8315Z device can interface with a variety of Hall sensors. Typically, a Hall
element is used, which outputs a differential signal. To use this type of sensor, the AVDD regulator can be used
to power the Hall sensor. Figure 9-3 shows the connections.

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AVDD

INP

OUTN OUTP HPx Hall

Hall Sensor
Comparator
+
INN -
(Optional)
HNx

Figure 9-3. Typical Hall Sensor Configuration

Because the amplitude of the Hall-sensor output signal is very low, capacitors are often placed across the Hall
inputs to help reject noise coupled from the motor. Capacitors with a value of 1 nF to 100 nF are typically used.
9.2.2 Open Drain Configuration
Some motors use digital Hall sensors with open-drain outputs. These sensors can also be used with the
MCT8315Z device, with the addition of a few resistors as shown in Figure 9-4.

AVDD

1 to 1 to
VCC 4.7 NŸ 4.7 NŸ

HPx Hall
Hall Sensor
OUT Comparator
+
GND -

HNx

To Other
HNx Inputs

Figure 9-4. Open-Drain Hall Sensor Configuration

The negative (HNx) inputs are biased to AVDD / 2 by a pair of resistors between the AVDD pin and ground. For
open-collector Hall sensors, an additional pullup resistor to the AVDD pin is required on the positive (HPx) input.
Again, the AVDD output can usually be used to supply power to the Hall sensors.

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9.2.3 Series Configuration

Hall elements are also connected in series or parallel depending upon the Hall sensor current/voltage
requirement. Figure 9-5 shows the series connection of Hall sensors powered via the MCT8315Z internal LDO
(AVDD). This configuration is used if the current requirement per Hall sensor is high (>10 mA)

RSE
AVDD

INP

HPA Hall
Hall Sensor
OUTN OUTP Comparator
+
INN -

HNA

INP

HPB Hall
Hall Sensor
OUTN OUTP Comparator
+
INN -

HNB

INP

HPC Hall
Hall Sensor
OUTN OUTP Comparator
+
INN -
GND
HNC

Figure 9-5. Hall Sensor Connected in Series Configuration

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9.2.4 Parallel Configuration

Figure 9-6 shows the parallel connection of Hall sensors which is powered by the AVDD. This configuration can
be used if the current requirement per Hall sensor is low (<10 mA).

AVDD

RPL

INP

HPA Hall
Hall Sensor
OUTN OUTP Comparator
+
INN -
GND
HNA

INP

HPB Hall
Hall Sensor
OUTN OUTP Comparator
+
INN -
GND
HNB

INP

HPC Hall
Hall Sensor
OUTN OUTP Comparator
+
INN -
GND
HNC

Figure 9-6. Hall Sensors Connected in Parallel Configuration

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9.3 Typical Applications

9.3.1 Three-Phase Brushless-DC Motor Control With Current Limit
In this application, the MCT8315Z is used to drive a brushless-DC motor with current limit up to 100% duty cycle.
The following design procedure can be used to configure the MCT8315Z in current limit mode.
9.3.1.1 Detailed Design Procedure
Table 9-1 lists the example input parameters for the system design.
Table 9-1. Design Parameters
DESIGN PARAMETERS REFERENCE EXAMPLE VALUE
Supply voltage VVM 24 V
Motor peak current IPEAK 2A
PWM Frequency fPWM 50 kHz
Slew Rate Setting SR 200 V/µs
Buck regulator output voltage VBK 3.3 V

9.3.1.1.1 Motor Voltage

Brushless-DC motors are typically rated for a certain voltage (for example 12 V or 24 V). Operating a motor at a
higher voltage corresponds to a lower drive current to obtain the same motor power. Operating at lower voltages
generally allows for more accurate control of phase currents. The MCT8315Z functions down to a supply of 4.5V.
A higher operating voltage also corresponds to a higher obtainable rpm. The MCT8315Z allows for a range of
possible operating voltages because of a maximum VM rating of 40 V.
9.3.1.1.2 Using Active Demagnetization
Active demagnetization reduces power losses in the device by turning on the MOSFETs automatically when the
body diode starts conducting to reduce diode conduction losses. It is used in trapezoidal commutation when
switching commutation states (turning a high-side MOSFET off and another high-side MOSFET on while keeping
a low-side MOSFET on). Active demagnetization is enabled when EN_ASR and EN_AAR bits are set in the SPI
variant or MODE pin is set to Mode 5, Mode 6, or Mode 7 in the H/W variant.
When switching commutation states with active demagnetization disabled, dead time is inserted and the low-side
MOSFET’s body diode conducts while turning another high-side MOSFET on to continue sourcing current
through the motor. This conduction period causes higher power losses due to the forward-bias voltage of
the diode and slower dissipation of current. Figure 9-7 shows the body diode conducting when switching
commutation states.

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Figure 9-7. Active demagnetization disabled in MCT8315Z

When active demagnetization is enabled, the AD_HS and AD_LS comparators detect when the sense FET
voltage is higher or lower than the programmed threshold. After the dead time period, if the threshold is
exceeded for a fixed amount of time, the body diode is conducting and the logic core turns the low-side FET
on to provide a conduction path with smaller power losses. Once the VDS voltage is below the comparator
threshold, the MOSFET turns off and current briefly conducts through the body diode until the current completely
decays to zero. This is shown in Figure 9-8.

Figure 9-8. Active demagnetization enabled in MCT8315Z

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9.3.1.1.3 Using Delay Compensation

Differences in delays of dead time and propagation delay can cause mismatch in the output timings of PWMs,
which can lead to duty cycle distortion. To accommodate differences in propagation delay between various input
conditions, the MCT8315Z integrates a Delay Compensation feature.
Delay Compensation is used to match delay times for currents going into and out of phase by adding a variable
delay time (tvar) to match a preset target delay time. This delay time is configurable in SPI devices, and it is
recommended in the datasheets to choose a target delay time that is equal to the propagation delay time plus
the driver dead time (tpd + tdead).
For an example of Delay Compensation implementation, please visit the Delay and Dead Time in Integrated
MOSFET Drivers application note.
9.3.1.1.4 Using the Buck Regulator
In MCT8315Z, the buck regulator components must be populated whether the buck is used or unused.
If unused, Resistor Mode should be configured by placing a small value resistor of 22-Ω for RBK and a 10-V
rated, 22-µF capacitor for CBK to minimize board space and reduce component cost. To disable the buck
regulator, set the BUCK_DIS in the SPI variant. The buck cannot be disabled in the Hardware variant.
If the buck regulator is used, either the Inductor or Resistor Mode can be selected. Inductor Mode allows a
22-µH or 47-µH inductor be used for LBK. CBK is recommended to be 22-µF. Make sure an appropriate inductor
is chosen to allow for maximum peak saturation current at a 20% inductance drop since the buck can supply up
to 600-mA external current.
Resistor Mode allows for power to be dissipated in an external resistor if the load requirement is less than
40-mA. Make sure the resistor is rated for the power dissipation required at worst case VM voltage dropout. See
Equation 6, Equation 7, and Equation 8 to calculate the resistor power rating required for a 24-V rated system,
3.3V buck output voltage, and 20-mA load current.

PRBK > VM − VBK × IBK (6)

PRBK > 24V − 3.3V × 20mA (7)

PR_BK > 0.434W (8)

9.3.1.1.5 Power Dissipation and Junction Temperature Losses

To calculate the junction temperature of the MCT8315Z from power losses, use Equation 9. Note that the
thermal resistance θJA depends on PCB configurations such as the ambient temperature, numbers of PCB
layers, copper thickness on top and bottom layers, and the PCB area.

℃
T J ℃ = Ploss W × θ JA W + TA ℃ (9)

The table below shows summary of equations for calculating each loss in the MCT8315Z.
Table 9-2. MCT8315Z Power Losses
Loss type Equation

Standby power Pstandby = VPVDD x IPVDDS

GVDD CP mode (PVDD < 18V) PLDO = 2 x VPVDD x IGVDD - VGVDD x IGVDD

GVDD LDO mode (PVDD > 18V) PLDO = (VPVDD - VGVDD) x IGVDD

AVDD LDO PLDO = (VPVDD - VAVDD) x IAVDD

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9.3.1.2 Application Curves

Figure 9-9. Device Powerup with VM Figure 9-10. Device Powerup with nSLEEP

Figure 9-11. Driver PWM Operation Figure 9-12. Driver PWM Operation with FGOUT

Figure 9-13. Power Management

Figure 9-14. Driver PWM with Active
Demagnetization (ASR and AAR)

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Figure 9-15. Driver PWM Operation with Current Figure 9-16. Driver 100% Operation with Current
Limit Chopping

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10 Power Supply Recommendations

10.1 Bulk Capacitance
Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The capacitance and current capability of the power supply
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed dc, brushless DC, stepper)
• The motor braking method
The inductance between the power supply and the motor drive system limits the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ +
Motor Driver
±

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 10-1. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.

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11 Layout
11.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors such as the charge pump, AVDD, and VREF capacitors should be ceramic and placed
closely to device pins.
The high-current device outputs should use wide metal traces.
To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,
grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage
circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the
device. Optionally, GND_BK can be split. Make sure grounds are connected through net-ties or wide resistors to
reduce voltage offsets and maintain gate driver performance.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
power loss that is generated in the device.
To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across
all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and
improve thermal dissipation from the die surface.
Separate the SW_BK and FB_BK traces with ground separation to reduce buck switching from coupling as noise
into the buck outer feedback loop. Widen the FB_BK trace as much as possible to allow for faster load switching.
Figure 11-1 shows a layout example for the MCT8315Z.

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11.2 Layout Example

Figure 11-1. Recommended Layout Example for MCT8315Z

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11.3 Thermal Considerations

The MCT8315Z has thermal shutdown (TSD) as previously described. A die temperature in excess of 165°C
(min.) disables the device until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
11.3.1 Power Dissipation
The power loss in MCT8315Z include standby power losses, LDO and Buck power losses, FET conduction
and switching losses, and diode losses. The FET conduction loss dominates the total power dissipation in
MCT8315Z. At start-up and fault conditions, the output current is much higher than normal current; remember
to take these peak currents and their duration into consideration. The total device dissipation is the power
dissipated in each of the three half bridges added together. The maximum amount of power that the device can
dissipate depends on ambient temperature and heatsinking. Note that RDS,ON increases with temperature, so
as the device heats, the power dissipation increases. Take this into consideration when designing the PCB and
heatsinking.
A summary of equations for calculating each loss is shown below for trapezoidal control.
Table 11-1. MCT8315Z Power Losses for Trapezoidal Control
Loss type Trapezoidal

Standby power Pstandby = VM x IVM_TA

LDO (from VM) PLDO = (VM-VAVDD) x IAVDD

FET conduction PCON = 2 x IRMS(trap) x Rds,on(TA)

FET switching PSW = IPK(trap) x VPK(trap) x trise/fall x fPWM

Diode Pdiode = IRMS(trap) x Vdiode

X tdiode x fPWM

Buck PBK = 0.97 x VBK x IBK

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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Visit the MCT8315ZH-EVM Tool Page
• Download the BLDC Integrated MOSFET Thermal Calculator tool
• Calculating Motor Driver Power Dissipation, SLVA504
• PowerPAD™ Thermally Enhanced Package, SLMA002
• PowerPAD™ Made Easy, SLMA004
• Sensored 3-Phase BLDC Motor Control Using MSP430, SLAA503
• Understanding Motor Driver Current Ratings, SLVA505
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

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www.ti.com 15-Dec-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MCT8315Z0HRRYR ACTIVE WQFN RRY 32 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MCT8315 Samples
Z0HRRY

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 GENERIC PACKAGE VIEW
RRY 32 WQFN - 0.8 mm max height
4 x 6, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229624/A

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 PACKAGE OUTLINE
RRY0032B SCALE 2.500
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4.1 A
B
3.9

PIN 1 INDEX AREA

6.1
5.9

0.8
0.7
C

SEATING PLANE
0.05 0.08 C
0.00
2.7 0.1

2X 2.5
SYMM
EXPOSED (0.1) TYP
11 16
THERMAL PAD
10 17

SYMM 33
2X 4.5 4.7 0.1

28X 0.5
1
26 0.3
32X
0.2
PIN 1 ID 32 27
0.1 C A B
(45 X 0.3) 0.5
32X 0.05 C
0.3
4229604/A 04/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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 EXAMPLE BOARD LAYOUT
RRY0032B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(2.7)

SYMM SEE SOLDER MASK

32 27 DETAIL
32X (0.6)

32X (0.25)

1 26

(0.92)
28X (0.5)
(4.7)

(1.18)

33 SYMM
(5.8)

(R0.05) TYP

( 0.2) TYP
VIA 17
10

11 16
(1.1)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

0.07 MIN
0.07 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE
SOLDER MASK

EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK

OPENING METAL OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4229604/A 04/2023
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
RRY0032B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(0.695)

32 27
32X (0.6)

32X (0.25)

1 26

28X (0.5)
(1.18)

33 (0.59)
SYMM (5.8)

(R0.05) TYP

8X (0.98)

10
17

11 16
8X (1.19)

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 15X

EXPOSED PAD 33
74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4229604/A 04/2023

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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