Module – III

(Stack and Interrupts)

• Syllabus
• Stack structure of 8086,Programming using
stack.Interrupts - Types of Interrupts and Interrupt Service
Routine. Handling Interrupts in 8086, Interrupt
programming. - Programmable Interrupt Controller - 8259
– Architecture(Just mention the control word,no need to
memorize the control word)-Interfacingmemory with 8086.

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 Stack structure of 8086
• During interrupt and subroutine operations, the
contents of specific internal registers(CS and IP) of the
8086.
• If these registers contain data that are needed after
the return, they should be PUSHed to a section of
memory known as the Stack.
• Here they may be maintained temporarily. At the
completion of the service routine or subroutine,
these values are POPped off the stack in the reverse
order of the PUSH, and the register contents are
restored with their original data

CE kottarakkara,Dept. of CSE 2
• When an interrupt occurs, the 80x86
automatically PUSHes the current flags, the value
in CS, and the value in IP onto the stack. • As part
of the service routine for the interrupt, the
contents of other registers may be pushed onto
the stack by executing PUSH instructions.

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• stack is implemented in the memory of the 8086.
• It is a maximum of 64K bytes long .The lowest
addressed byte in the current stack is pointed to
by the contents of the stack segment (SS) register.
• Another register, the stack pointer (SP) contains an
offset of the current top of the stack from the
value in SS.
• The address obtained from the contents of SS and
SP is the physical address of the last storage
location in the stack to which data were PUSHed.
This is known as the top of the stack.
CE kottarakkara,Dept. of CSE 4
• The value in the stack pointer starts at 0FFFFh upon
initialization of the 8086.
• Combining this value with the current value in SS
gives the highest addressed location in the stack: that
is, the bottom of the stack.
• Since data transfers to and from stack are always 16-
bit words, it is important to configure the system such
that all stack locations are at even word boundaries.
• This minimizes the number of memory cycles required
to PUSH or POP data for the stack and minimizes the
amount of time required to perform a switch in
program context.
CE kottarakkara,Dept. of CSE 5
• The 8086 PUSHes data and addresses to the
stack one word at a time.
 Each time a register value is to be PUSHed onto
the top of the stack, the value in the stack pointer
is first decremented by 2 and then the contents of
the register are written into memory.
the stack grows down in memory from the bottom
of the stack, which corresponds to the physical
address derived from SS and 0FFFFh toward the
end of the stack, which corresponds to the
physical address obtained from SS and offset
000016.

CE kottarakkara,Dept. of CSE 6
• When a value is popped from the top of the stack,
the reverse of this sequence occurs. The physical
address defined by SS and SP always points to the
location of the last value pushed onto the stack.
• Its contents are first popped off the stack and put
into the specified register within the 8086; then SP
is incremented by 2. The top of the stack now
corresponds to the previous value pushed onto
the stack

CE kottarakkara,Dept. of CSE 7
 PUSH operation
• For instance, if the instruction is PUSH AX its
execution results in the following:
• SP <- SP - 1 ; SP is decrementedSS:SP <= AH ; AH
is PUSHed on the Stack
• SP <- SP - 1 ; SP is decrementedSS:SP <= AL ; AL is
PUSHed on the Stack

CE kottarakkara,Dept. of CSE 8
 Pop operation
• if the instruction is POP AX, its execution results in
the following:AL <- SS:SP ; AL is POPped from the
StackSP <- SP + 1 ; SP is incrementedAH <= SS:SP ;
AH is POPped from the StackSP <- SP + 1 ; SP is
incremented

CE kottarakkara,Dept. of CSE 9
Programming using stack

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CS305 MP-MC, Dept of CSE,College of
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 Interrupts
• Interrupt Types
– Hardware Interrupts: External event
– Software Interrupts: Internal event (Software generated)
– Maskable and non-maskable interrupts

• Interrupt Vectors and Interrupt Handlers

• Interrupt Controllers

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 The Purpose of Interrupts
• Interrupts are useful when interfacing I/O devices with low data-
transfer rates, like a keyboard or a mouse, in which case polling the
device wastes valuable processing time
• The peripheral interrupts the normal application execution,
requesting to send or receive data.
• The processor jumps to a special program called Interrupt Service
Routine to service the peripheral
• After the processor services the peripheral, the execution of the
interrupted program continues.

Main Program Main Program Main Program Main Program

Printer Interrupt Modem Interrupt Modem Interrupt

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 BASIC INTERRUPT TERMINOLOGY
 Interrupt pins: Set of pins used in hardware interrupts
 Interrupt Service Routine (ISR) or Interrupt handler: code
used for handling a specific interrupt
 Interrupt priority: In systems with more than one interrupt
inputs, some interrupts have a higher priority than other
◦ They are serviced first if multiple interrupts are triggered simultaneously
 Interrupt vector: Code loaded on the bus by the interrupting
device that contains the Address (segment and offset) of
specific interrupt service routine
 Interrupt Masking: Ignoring (disabling) an interrupt
 Non-Maskable Interrupt: Interrupt that cannot be ignored
(power-down)
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Interrupt processing flow
Main program

Interrupt N
Req

Accept N
Interrupt

Get interrupt
vector

Jump to ISR
Save PC

Load PC

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 Hardware Interrupts – Interrupt pins and timing
• x86 Interrupt Pins
– INTR: Interrupt Request. Activated by a peripheral device to interrupt the processor.
• Level triggered. Activated with a logic 1.
– /INTA: Interrupt Acknowledge. Activated by the processor to inform the interrupting device the the
interrupt request (INTR) is accepted.
• Level triggered. Activated with a logic 0.
– NMI: Non-Maskable Interrupt. Used for major system faults such as parity errors and power failures.
• Edge triggered. Activated with a positive edge (0 to 1) transition.
• Must remain at logic 1, until it is accepted by the processor.
• Before the 0 to 1 transition, NMI must be at logic 0 for at least 2 clock cycles.
• No need for interrupt acknowledgement.

INTR

INTA΄

D7-D0 Vector

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 Interrupt Vectors
 The processor uses the interrupt vector to determine the address of the
ISR of the interrupting device.
 In the 8088/8086 processor as well as in the 80386/80486/Pentium
processors operating in Real Mode (16-bit operation), the interrupt
vector is a pointer to the Interrupt Vector Table.
◦ The Interrupt Vector Table occupies the address range from 00000H to
003FFH (the first 1024 bytes in the memory map).
◦ Each entry in the Interrupt Vector Table is 4 bytes long:
 The first two represent the offset address and the last two the
segment address of the ISR.
◦ The first 5 vectors are reserved by Intel to be used by the processor.
 The vectors 5 to 255 are free to be used by the user.

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 Interrupt Vector - Example
Draw a circuit diagram to show how a device with interrupt
vector 4CH can be connected on an 8088 microprocessor system.
Answer:
◦ The peripheral device activates the INTR line
◦ The processor responds by activating the INTA signal
◦ The NAND gate enables the 74LS244 octal buffer
 the number 4CH appears on the data bus
◦ The processor reads the data bus to get the interrupt vector

D7

Peripheral
Device
8088 System

D0

A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
E2 INTR
LS244
E1
I7 I6 I5 I4 I3 I2 I1 I0
A19 +5V
INTA
4C = 0 1 0 0 1 1 0 0
INTR

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 Interrupt Vector Table –Example
•Using the Interrupt Vector Table shown below, determine the address of the ISR of a device
with interrupt vector 42H.
•Answer: Address in table = 4 X 42H = 108H
• (Multiply by 4 since each entry is 4 bytes)
• Offset Low = [108] = 2A, Offset High = [109] = 33
• Segment Low = [10A] = 3C, Segment High = [10B] = 4A
• Address = 4A3C:332A = 4A3C0 + 332A = 4D6EAH

0 1 2 3 4 5 6 7 8 9 A B C D E F
00000 3C 22 10 38 6F 13 2C 2A 33 22 21 67 EE F1 32 25
00010 11 3C 32 88 90 16 44 32 14 30 42 58 30 36 34 66
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00100 4A 33 3C 4A AA 1A 1B A2 2A 33 3C 4A AA 1A 3E 77
00110 C1 58 4E C1 4F 11 66 F4 C5 58 4E 20 4F 11 F0 F4
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00250 00 10 10 20 3F 26 33 3C 20 26 20 C1 3F 10 28 32
00260 20 4E 00 10 50 88 22 38 10 5A 38 10 4C 55 14 54
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
003E0 3A 10 45 2F 4E 33 6F 90 3A 44 37 43 3A 54 54 7F
003F0 22 3C 80 01 3C 4F 4E 88 22 3C 50 21 49 3F F4 65
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 Interrupt Vector Table –Example
Write a sequence of instructions that initialize vector 40H to point to the ISR
“isr40”.
Answer: Address in table = 4 X 40H = 100H
 Set ds to 0 since the Interrupt Vector Table begins at 00000H
 Get the offset address of the ISR using the Offset directive
 and store it in the addresses 100H and 101H
 Get the segment address of the ISR using the Segment directive
 and store it in the addresses 102H and 103H
push ax Save registers in the stack
push ds
mov ax,0
Set ds to 0 to point to the interrupt vector table
mov ds,ax
mov ax,offset isr40 Get the offset address of the ISR and store
mov [0100h],ax it in the address 0100h (4X40h = 100h)
mov ax,segment isr40 Get the segment address of the ISR
mov [0102h],ax and store it in the address 0102h
pop ds
Restore registers from the stack
pop ax
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 Interrupt Masking
• The processor can inhibit certain types of
interrupts by use of a special interrupt mask bit.
• This mask bit is part of the flags/condition code
register, or a special interrupt register.
• If this bit is clear, and an interrupt request occurs
on the Interrupt Request input, it is ignored.
• NMI cannot be masked

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 Software Interrupts
• Traps: (self-interrupt!)
– Single step mode
– Calls to Operating System (INT 21H - x86)

• Exceptions:
– Divide by zero
– Memory protection fault

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 Interrupt Processing
• Save state
– Disable interrupts for the duration of the ISR
– Save instruction pointer
– Save flags
– Save register values

• Jump to interrupt service routine

– Location obtained by interrupt vector

• Process interrupt
• Restore state
– Load PC, flags, registers etc.

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 Interrupt Processing on the 8086 Microprocessor
 1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin,
(or an internal interrupt occurs.)
 2. The CPU finishes the present instruction (for a hardware interrupt) and checks the
INTR pin. If IF=0 the processor ignores the interrupt, else sends Interrupt
Acknowledge (INTA) to hardware interface.
 3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus
from the hardware interface.
 4. The contents of the flag registers are pushed onto the stack.
 5. Both the interrupt (IF – FR bit 9) and (TF – FR bit 8) flags are cleared. This
disables the INTR pin and the trap or single-step feature.
 6. The contents of the code segment register (CS) are pushed onto the Stack.
 7. The contents of the instruction pointer (IP) are pushed onto the Stack.
 8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP
and from (4 x N +2) into the CS so that the next instruction executes at the interrupt
service procedure addressed by the interrupt vector.
 9. While returning from the interrupt-service routine by the Interrupt Return (IRET)
instruction, the IP, CS and Flag registers are popped from the Stack and return to
their state prior to the interrupt.

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 The Intel x86 Interrupt Software Instructions
• All x86 processors provide the following instructions related to
interrupts:
– INT nn: Interrupt. Run the ISR pointed by vector nn.
• INT 0 is reserved for the Divide Error
• INT 1 is reserved for Single Step operation
• INT 2 is reserved for the NMI pin
• INT 3 is reserved for setting a Breakpoint
• INT 4 is reserved for Overflow (Same as the INTO (Interrupt on overflow)
instruction.
– CLI: Clear Interrupt Flag. IF is set to 0, thus interrupts are disabled.
– STI: Set Interrupt Flag. IF is set to 1, thus interrupts are enabled.
– IRET: Return from interrupt. This is the last instruction in the ISR (Real Mode only).
It pops from the stack the Flag register, the IP and the CS.
• After returning from an ISR the interrupts are enabled, since the initial value of the
flag register is poped from the stack.

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 Interrupt Vectors
 The Interrupt Vector contains the address of the interrupt service routine
 The Interrupt Vector Table is located in the first 1024 bytes of memory at
address 000000H-0003FFH.
 It contains 256 different 4-byte interrupt vectors, grouped in 18 types
◦ 000H: Type 0 (Divide error)
◦ 004H: Type 1 (Single-step)
◦ 008H: Type 2 (NMI) •030H: Type 12 (Stack segment
◦ 00CH: Type 3 (1-byte breakpoint) overrun)
◦ 010H: Type 4 (Overflow)
◦ 014H: Type 5 (BOUND)
•034H: Type 13 (General
◦ 018H: Type 6 (Undefined opcode) protection)
◦ 01CH: Type 7 (Coprocessor not available) •038H: Type 14 (Page fault)
◦ 020H: Type 8 (Double fault)
◦ 024H: Type 9 (Coprocessor segment overrun) •03CH: Type 15 (Unassigned)
◦ 028H: Type 10 (Invlid task state segment) •040H: Type 16 (Coprocessor
◦ 02CH: Type 11 (Segment not present)
error)
•044H-07CH: Type 14-31
(Reserved)
•080H: Type 32-255 (User)
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 Interrupt Types
 Type 0: Divide error – Division overflow or division by zero
 Type 1: Single step or Trap – After the execution of each instruction when trap flag set
 Type 2: NMI Hardware Interrupt – ‘1’ in the NMI pin
 Type 3: One-byte Interrupt – INT3 instruction (used for breakpoints)
 Type 4: Overflow – INTO instruction with an overflow flag
 Type 5: BOUND – Register contents out-of-bounds
 Type 6: Invalid Opcode – Undefined opcode occurred in program
 Type 7: Coprocessor not available – MSW indicates a coprocessor
 Type 8: Double Fault – Two separate interrupts occur during the same instruction
 Type 9: Coprocessor Segment Overrun – Coprocessor call operand exceeds FFFFH
 Type 10: Invalid Task State Segment – TSS invalid (probably not initialized)
 Type 11: Segment not present – Descriptor P bit indicates segment not present or invalid
 Type 12: Stack Segment Overrun – Stack segment not present or exceeded
 Type 13: General Protection – Protection violation in 286 (general protection fault)
 Type 14: Page Fault – 80386 and above
 Type 16: Coprocessor Error – ERROR΄ = ‘0’ (80386 and above)
 Type 17: Alignment Check – Word/Doubleword data addressed at odd location (486 and above)
 Type 18: Machine Check – MemoryCS305 Management interrupt (Pentium and above)
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 The 8259A Programmable Interrupt Controller
 Adds 8 vectored priority encoded interrupts to the microprocessor
 Can be expanded without additional hardware to accept up to 64
IRQ (one 8259A master, and one slave)
 Requires 4 wait states to be connected to a 8086
 D0-D7: Bidirectional data connections 11
D0 IR0
18
10 IR1 19
 IR0-IR7: Interrupt request inputs 9
D1
D2 IR2 20
8 IR3 21
 WR΄: Write input strobe 7
6
D3
D4 IR4 22
23
D5 IR5
 RD΄: Read input connects to the IORC΄signal4 D6
5
IR6
24
25
D7 8259A IR7
 INT: Output, connects to μP INTR pin 27
A0
1 CS΄
 INTA΄: Input, connects to μP INTA΄ pin 3
2
RD΄
WR΄
 A0: Command word select 16
17
SP/EN΄
CAS0
CAS1
12
13
INT
 CS΄: Chip select input 26
INTA΄
CAS2 15

 SP/EN΄: Slave program/enable buffer pin

 CAS0-CAS2: Outputs from master to slave for cascading multiple
8259A chips
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 Three internal registers

input-signals
8259A

IRR output-signal

IMR
ISR

IRR = Interrupt Request Register

IMR = Interrupt Mask Register
ISR = In-Service Register
 PC System Design

8259A
8259A INTR CPU
PIC
PIC (master)
(slave)

Programming is via
Programming is via I/O-ports 0x20-0x21
I/O-ports 0xA0-0xA1
Block Diagram(Architecture) of 8259

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 Programming the 8259A
• Initialization Control Words (ICWs)
– Prgrammed before 8259A begins to function
– A0 must be high
– There are four ICWs: ICW1, ICW2, ICW3, ICW4
– When there is only one 8259A in the system, ICW3 is not necessary

• Operation Control Words (OCWs)

– Programmed during normal operation
– There are three OCWs: OCW1, OCW2, OCW3
– A0 must be low, except in OCW1

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 ICW1 and ICW2
01 xx xx xx 11 LTIM ADI SNGL IC4 ICW1

LTIM (1 = Level-Triggered Interrupt Mode, 0 = Edge-Triggered Interupt Mode)

ADI is length of Address-Interval for call-instruction (1 = 4-bytes, 0 = 8-bytes)
SNGL (1 = single controller system, 0 = multiple controllers in cascade mode)
IC4 means Initialization Command-Word 4 is needed (1 = yes, 0 = no)

A15 A14 A13 A12 A11 ICW2

1 / T7 / T6 / T5 / T4 / T3 A10 A9 A8
ICW2 specifies the vector number used with the interrupt
request inputs
Example: for vectors 08H-0FH, write 08H in ICW2
Example: for vectors 70H-77H, write 70H in ICW2
 ICW3

1 S7 S6 S5 S4 S3 S2 S1 S0 (master)

S Interrupt-Request Input is from a slave controller (1=yes, 0=no)

1 0 0 0 0 0 ID2 ID1 ID0 (slave)

ID number of slave controller’s input-pin to master controller (0-7)

 ICW4

1 0 0 0 SFNMBUFM / SAEOIµPM

Special Fully-Nested Mode microprocessor

(1 = yes, 0 = no) mode
1=8086/8088
0=8080
NON-BUFFERED mode (00 or 01)
Automatic EOI mode
BUFFERED-MODE (10 = slave, 11 = master)
1 = yes, 0 = no
 OCW1/OCW2

 Operation Control Word 1 (OCW1) bits: Sets the

mask register
◦ 7 Mask IRQ7 (when ‘1’)
◦ 6 Mask IRQ6 (when ‘1’)
◦ 5 Mask IRQ5 (when ‘1’)
◦ 4 Mask IRQ4 (when ‘1’)
◦ 3 Mask IRQ3 (when ‘1’)
◦ 2 Mask IRQ2 (when ‘1’)
◦ 1 Mask IRQ1 (when ‘1’)
◦ 0 Mask IRQ0 (when ‘1’)

 OCW2 is used when automatic/normal end of

interrupt is not selected
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 OCW3
• OCW3 is used to read internal 8259A registers,
specify the operation of the special mask register,
and the poll command
• Status registers:
– Interrupt Request Register (IRR): indicates which IR inputs are active
– In-Service Register (ISR): contains the level of the interrupt being serviced
– Interrupt Mask Register (IMR): Holds the interrupt mask bits

• IRR and ISR are read by programming OCW3, IMR

is read through OCW1

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Interfacing Memory and I/O

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Memory device- RAM

Input Buffer
Output buffer

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 Basic Concepts
Memory Address Memory
 A memory device can be viewed Binary Hex Contents
as a single column table. 00-0000-0000 000 10011001
◦ Table index (row number) refers to the address of
the memory. 00-0000-0001 001 00111000
◦ Table entries refer to the memory contents or
data. 00-0000-0010 002 11001001
◦ Each table entry is referred as a memory location 00-0000-0011 003 00111011
or as a word.
 Both the memory address and
the memory contents are binary
numbers, expressed in most 11-1111-1100 3FC 01101000
cases in Hex format. 11-1111-1101 3FD 10111001
 The size of a memory device is 11-1111-1110 3FE 00110100
specified as the number of 11-1111-1111 3FF 00011000
memory locations X width or
1024 X 8 (or 1KX8) Memory
word size (in bits).
◦ For example a 1K X 8 memory device has 1024
memory locations, with a width of 8 bits.
College of Engg,Kottarakkara,Dept. of CSE 40
 Address Lines

 A memory device or memory chip

must have three types of lines or
connections: Address, Data, and
Control. Y00 Location 000
Y01 Location 001
 Address Lines: The input lines that Y02 Location 002
select a memory location within the A00 Y03 Location 003
A01
memory device.
◦ Decoders are used, inside the memory chip, to select a
specific location An-2
◦ The number of address pins on a memory chip specifies An-1 YFC Location 0FC
the number of memory locations.
YFD Location 0FD
 If a memory chip has 13 address pins (A0..A12), then
YFE Location 0FE
it has:
YFF Location 0FF
213 = 23 X 210 = 8K locations.
 If a memory chip has 4K locations, then it should
have N pins:
2N = 4K = 22 X 210 = 212  N=12 address pins
(A0..A11)
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 Data Lines

 Data Connections: All memory devices have a set of data output

pins (for ROM devices), or input/output pins (for RAM devices).
◦ Most RAM chips have common bi-directional I/O connections.
◦ Most memory devices have 1, 8 or 16 data lines.

Data Input Lines

(DI0..DIn-1)
k- address lines k- address lines
(A0..Am-1) 2m words (A0..Am-1) 2m words
k- address lines
(A0..Am-1) 2m words
Read/Write (R/W) n-bits per Output Enable (OE) n-bits per
Read (RD) n-bits per word word
Chip Select (CS) Chip Select (CS)
Write (WR) word
Chip Select (CS)
Data Output Lines
Data Input/Output (D0..Dn-1)
Data Output Lines Lines (D0..Dn-1)
(DO0..DOn-1) (2m X n) ROM with only O/P Data
(2m X n) RAM with common I/P
(2m X n) RAM with separate I/P lines
and O/P Data lines
and O/P Data lines

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 Control Lines

• Enable Connections:
– All memory devices have at least one Chip Select (CS) or Chip Enable (CE)
input, used to select or enable the memory device.
• If a device is not selected or enabled then no data can be read from, or
written into it.
• The CS or CE input is usually controlled by the microprocessor through the
higher address lines via an address decoding circuit.

• Control Connections:
– RAM chips have two control input signals that specify the type of memory
operation: the Read (RD) and the Write (WR) signals.
• Some RAM chips have a common Read/ Write (R/W) signal.
– ROM chips can perform only memory read operations, thus there is no need
for a Write (WR) signal.
• In most real ROM devices the Read signal is called the Output Enable
(OE) signal. College of Engg,Kottarakkara,Dept. of CSE 43
 Memory Read Operations

•A memory read operation is carried out in the following

steps:
– The processor loads on the Address bus the address of the memory location to be read (Step 1).
• Some of the address lines select the memory devices that owns the memory
location to be read (Step 1a), while the rest point to the required memory location
within the memory device.
– The processor activates the Read (RD) signal (Step 2).
• The selected memory device loads on the data bus the content of the memory
location specified by the address bus (Step 3).
– The processor reads the data from the data bus, and resets the RD signal (Step 4).
C lock T1 T2 T3

A ddress B us V alid A ddress

C hip E nable

R ead (R D )

D ata B us Invalid D ata V alid D ata

S tep 1a
S tep 2 S tep 3 S tep 4
S tep 1 44
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 Memory Write Operations

•A memory write operation is carried out in the

following steps:
– The processor loads on the Address bus the address of the memory location (Step 1).
• Some of the address lines select the memory devices that owns the memory
location to be written (Step 1a), while the rest point to the required memory
location within the memory device.
– The processor loads on the data bus the data to be written (Step 2).
– The processor activates the Write (WR) signal (Step 3).
• The data at the data bus is stored in the memory location specified by the address
bus (Step 4).

C lo c k T1 T2 T3

A d d re s s B u s V a lid A d d r e s s

D a ta B u s V a lid D a t a

C h ip E n a b le

W r it e ( W R )
S te p 2
S te p 1 45
College of S te p 1 a S te p 3
S te p 4
Engg,Kottarakkara,Dept. of CSE
 Example: (32X4 RAM module using 8X4 RAM chips - Assume an 8-address line processor)

D3 D3 D0 D3 D0 D3 D0 D3 D0
8x4 RAM 1 8x4 RAM 2 8x4 RAM 3 8x4 RAM 4
A0 A0 A0 A0

D0
A2 A2 A2 A2

RD WR CS RD WR CS RD WR CS RD WR CS

RD
WR

A0

2X4 DEC.
A2
A3 A Y0
A4 B Y1
A5 Y2
A6 CS Y3
A7

College of 46
Engg,Kottarakkara,Dept. of CSE
 Memory Map for previous example.

 There are three address lines connected on the address selection circuit. Thus
there can be eight different memory map configurations.
 Three possible memory map configurations are shown below.

Address Selection A5 Address Selection A5 Address Selection A5

Circuit
A6 Circuit
A6 Circuit
A6
A7 A7 A7

A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map

0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 Not 0 0 0 0 0 0 0 0 00 Not
RAM1 Used Used
0 0 0 0 0 1 1 1 07 1 0 0 1 1 1 1 1 9F 1 1 0 1 1 1 1 1 DF
0 0 0 0 1 0 0 0 08 1 0 1 0 0 0 0 0 A0 1 1 1 0 0 0 0 0 E0
RAM2 RAM1 RAM1
0 0 0 0 1 1 1 1 0F 1 0 1 0 0 1 1 1 A7 1 1 1 0 0 1 1 1 E7
0 0 0 1 0 0 0 0 10 1 0 1 0 1 0 0 0 A8 1 1 1 0 1 0 0 0 E8
RAM3 RAM2 RAM2
0 0 0 1 0 1 1 1 17 1 0 1 0 1 1 1 1 AF 1 1 1 0 1 1 1 1 EF
0 0 0 1 1 0 0 0 18 1 0 1 1 0 0 0 0 B0 1 1 1 1 0 0 0 0 F0
RAM4 RAM3 RAM3
0 0 0 1 1 1 1 1 1F 1 0 1 1 0 1 1 1 B7 1 1 1 1 0 1 1 1 F7
0 0 1 0 0 0 0 0 20 Not 1 0 1 1 1 0 0 0 B8 1 1 1 1 1 0 0 0 F8
Used RAM4 RAM4
1 1 1 1 1 1 1 1 FF 1 0 1 1 1 1 1 1 BF 1 1 1 1 1 1 1 1 FF
1 1 0 0 0 0 0 0 C0 Not
1 1 1 1 1 1 1 1 FF Used

College of Engg,Kottarakkara,Dept. of CSE 47

 Design Example:
Design an 8KX8 RAM module using 2KX8 RAM chips. The module should be connected on an 8-bit
processor with a 16-bit address bus, and occupy the address range starting from the address A000.
Show the circuit and the memory map.

• Number of memory devices needed = 8K/2K

=4
• Decoder needed = 2X4
• Number of address lines on each 2KX8
memory chip = 11
2m = 2K = 21 x 210 = 211  (A0..A10)
• Decoder needed = 2X4
 2 address lines are needed for the decoder.
 (A11..A12)
• Number of address lines needed for the
address selection circuit
= 16 - 11 - 2 = 3  (A13, A14 A15)

College of Engg,Kottarakkara,Dept. of CSE 48

 Circuit Diagram

D7
D0 D7 D0 D7 D0 D7 D0 D7

2Kx8 RAM 2Kx8 RAM 2Kx8 RAM 2Kx8 RAM

D0 A0 A0 A0 A0

A10 A10 A10 A10

RD WR CS RD WR CS RD WR CS RD WR CS

RD
WR

A0
2X4 DEC.
A11
A Y0
A12
B Y1
A13
Y2
A14
CS Y3
A15 A15

College of Engg,Kottarakkara,Dept. of CSE 49

 Address Decoding
• The physical address space, or memory map, of a microprocessor refers
to the range of addresses of memory location that can accessed by the
microprocessor.
• The size of the address space depends on the number of address lines of
the microprocessor.
• At least two memory devices are required in a microprocessor system:
one for the ROM and one for the RAM.
• In an 8088/8086 the high addresses in the memory map should always
be occupied by a ROM, while the low addresses in the memory map
should always be occupied by a RAM.

ACOE255 Microprocessors I - Frederick University 50

 Address decoding is required in order to enable the
connection of more than one memory devices on the
microprocessor. Each device will occupy a unique area in
the memory map.
 A memory system is not fully decoded if some of the
address lines are not used by the address decoding circuit
or memory. In this case a memory device will occupy more
than one sections in the memory map. This is referred as
memory mirroring or memory imaging.

College of Engg,Kottarakkara,Dept. of CSE 51