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Analysis and Design Considerations of

Integrated 3-Level Buck Converters
Xun Liu, Student Member, IEEE, Philip K. T. Mok, Fellow, IEEE,
Junmin Jiang, Student Member, IEEE, and Wing-Hung Ki, Member, IEEE

Abstract—This paper presents a systematic analysis of inte-

grated 3-level buck converters under both ideal and real conditions
as a guidance for designing robust and fast 3-level buck converters.
Under ideal conditions, the voltage conversion ratio, the output
voltage ripple and, in particular, the system’s loop-gain function
are derived. Design considerations for real circuitry implementa-
tions of an integrated 3-level converter, such as the implementation
of the flying capacitor, the impacts of the parasitic capacitors of the
flying capacitor and the 4 power switches, and the time mismatch
between the 2 duty-cycle signals are thoroughly discussed. Under
these conditions, the voltage conversion ratio, the voltage across
the flying capacitor and the power efficiency are analyzed and
verified with Cadence simulation results. The loop-gain function of Fig. 1. Topology of (a) a standard 2-level buck converter with high-voltage
an integrated 3-level buck converter with parasitic capacitors and devices; (b) a cascode 2-level buck converter with low-voltage devices; and
time mismatch is derived with the state-space averaging method. (c) a 3-level buck converter with low-voltage devices.
The derived loop-gain functions are verified with time-domain
small signal injection simulation and measurement, with a good A 3-level DC-DC converter, as shown in Fig. 1(c), has
match between the analytical and experimental results. many advantages over the cascode 2-level topology through
Index Terms—Loop gain, MOS parasitic capacitors, power con- the addition of an extra flying capacitor CF . Due to CF and
verter modeling, power integrated circuits, small signal injection the interleaving switching behavior [14], the voltage at the VX
simulation, state-space averaging, transfer function, 3-level buck node can swing between 3 values: Vg , Vg /2, and zero, thus
converters. the origin of the name “3-level.” The finer step of VX voltage
reduces the inductor current ripple to 1/4 and output voltage
I. I NTRODUCTION ripple to 1/8 that of a standard 2-level buck converter [7],

T HREE-LEVEL converters, since first proposed in [1],

have become more and more attractive recently in both the
academia and the industry [2]–[12] due to their many advan-
hence allowing the use of smaller LC components for lower
cost, smaller form factor, fast large signal transient response
and a potentially higher bandwidth. Thus, it has been widely
tages under high-voltage operations. Although voltage ratings adopted in supply modulators for power amplifiers with faster
in advanced CMOS technologies have reduced to between reference tracking capability and lower noises [2]–[4], and
0.9 V and 1.2 V for standard devices, or 1.8 V, 2.5 V, 3.3 V, fully-integrated converters for smaller area and lower cost of
and 5 V for I/O devices, the supply voltages in many appli- integrated LC components [5], [6].
cations, such as lithium batteries directly powered devices or Up to now, only a handful of works have been reported imple-
wireless power transmission, are still high, around 2 V–5 V. As menting on-chip 3-level DC-DC converters [4]–[6]. Amo et al.
shown in Fig. 1(a), adopting high-voltage devices (I/O devices) [4] use a 3-level buck converter as part of the supply modulator,
with a standard 2-level buck operation solves this over-voltage but do not mention the implementation of the flying capac-
problem, but degrades the efficiency due to large switching loss. itor or the compensator design. In [6], a monolithic 3-level
High-voltage devices bring a higher cost and may not be avail- buck converter in discontinuous conduction mode (DCM) is
able for some process options. As shown in Fig. 1(b), a cascode introduced, but it lacks a detailed description of the pulse fre-
2-level buck converter with stacking low-voltage devices is able quency modulation (PFM) controller design. A fully-integrated
to tackle the voltage stress issue with better efficiency [13]. 3-level buck converter is presented in [5] with on-chip spiral
inductors and on-chip capacitors. The implementation of CF
and the efficiency reduction due to CF ’s parasitic capacitor are
briefly discussed. However, most of the measurement results are
Manuscript received October 5, 2015; revised February 24, 2016; accepted conducted in open-loop, and the important impact on the volt-
March 30, 2016. This work was supported in part by the Research Grant Council age across CF due to the parasitic capacitor is not mentioned.
of Hong Kong SAR Government, China, under Project 16207014. This paper
was recommended by Associate Editor M. di Bernardo. Moreover, none of these works [4]–[6] discusses the influences
The authors are with the Department of Electronic and Computer Engineer- of the time mismatch and the power switches’ parasitic capaci-
ing, the Hong Kong University of Science and Technology, Clear Water Bay, tors on the converter’s performance. As the switching frequency
Hong Kong (e-mail: xliuam@connect.ust.hk; eemok@ust.hk). increases, parasitics of CF and the power switches, and the
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. time mismatch between the control signals, are playing a more
Digital Object Identifier 10.1109/TCSI.2016.2556098 significant role in affecting the system’s performance.
1549-8328 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

There have been quite a few 3-level converters designed for

high power high voltage applications using discrete compo-
nents [7]–[12], but most of such works focus on the topology
implementations and open-loop responses. Except for these,
[1] further explores the topology and extends it to stacked
multi-cell converters for different applications. The dynamic
modelling and the voltage distributions of the flying capacitors
are discussed in [15]. However, they are generalized analyses
for multi-level converters and are not very straightforward
for 3-level buck converters. Moreover, they cannot cover the Fig. 2. Driver signals for 3-level buck converters.
problems brought by integrated circuits. In [16], the control
laws for multi-cell chopper to achieve close loop regulation
are proposed. These laws could be studied and adapted to be
applied for 3-level buck converters.
In summary, the loop-gain functions of 3-level buck convert-
ers, still remain open for study. Furthermore, practical design
considerations of integrated 3-level buck converters such as the
time mismatch and parasitic capacitors are seldom discussed,
but they are crucial issues in circuit design. In this research, we
study the loop-gain function as well as practical IC design con-
siderations as a fundamental guideline for the design of robust
and fast 3-level converters. In particular, the operation principle
will be presented, and the voltage conversion ratio, output
voltage ripple, and loop-gain function will be derived. Practical
design issues for the implementation of an integrated 3-level
converter, such as the time mismatch, the implementation of
the flying capacitor, and the effects of parasitic capacitors are
considered.
The paper is organized as follows. Section II explains the
operation principle of a generic 3-level buck converters. In
Section III, the dynamic performance is elaborated, and the
loop-gain function under ideal conditions is derived using Fig. 3. Timing diagram of D, DS , VX , inductor current IL and flying
state-space averaging (SSA) method with perturbation analysis. capacitor’s voltage VCF in one cycle when (a) D ≤ 0.5, (b) D ≥ 0.5.
Design considerations and practical design issues of integrated
3-level buck converters, such as the influences of parasitic
capacitors and the time mismatch, are discussed in Section IV.
Simulation results in Cadence Virtuoso Analog Design Envi-
ronment are presented to verify all the analyses. Section V
introduces a time-domain small signal injection simulation
method with Bode plot results to verify the derived loop-gain
functions. Experimental results are also presented in Section VI
to justify the models. Finally, Section VII concludes the paper.

II. O PERATION P RINCIPLE OF 3-L EVEL

B UCK C ONVERTERS
As shown in Fig. 2, the power stage of a 3-level buck
converter has two pairs of complementary switches, P1 , N1
and P2 , N2 , with switching signals of D and DS , respectively.
D and DS have the same duty cycle, but with a 180◦ phase
shift. The timing diagram of D and DS is shown in Fig. 3. Fig. 4. Four operation states of a 3-level buck converter S1 , S2 , S3 , and S4 .
Each period is separated into 4 parts, with D1 , D2 , D3 , and D4
defined as the duty cycle for each part. Ideally, D1 = D3 and N2 turned on and VX equaling Vg − VCF . The inductor current
D2 = D4 . In Case 1, when D is smaller than 0.5, D = D1 ; and goes up, at the same time, charging CF , as shown in Fig. 3(a).
in Case 2, when D is larger than 0.5, D = D1 + 0.5. Under the If, ideally, VCF is half of Vg , the voltages across the 4 terminals
ideal conditions, the average voltage across the flying capacitor of the 4 switches are kept within half of Vg , which is the safe
CF is expected to be half of Vg [15]. When D is smaller than operation region of the transistors.
0.5, the 3-level buck converter has 3 kinds of configurations as For the duration of D2 , the converter works in State 2 (S2 ),
shown in Fig. 4 [17]. with N1 and N2 turned on and VX equaling 0. The inductor
Considering Case 1, when D = 0.5 with VO = Vg /2, for the current goes down and VCF stays the same. For the duration
duration of D1 , the converter works in State 1 (S1 ) with P1 and of D3 , the converter works in State 3 (S3 ) with P2 and N1
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LIU et al.: ANALYSIS AND DESIGN CONSIDERATIONS OF INTEGRATED 3-LEVEL BUCK CONVERTERS 3

turned on and VX equaling VCF . The inductor current goes

up and discharges CF . For the duration of D4 , the converter
works in S2 , the same as D2 ’s duration. For all these states, the
voltage difference between the 4 terminals of the 4 switches is
still within half of Vg .
For Case 2 when D ≥ 0.5 with VO = Vg /2, there is a new
state for the duration of D1 : State 4 (S4 ), when P1 and P2
are turned on as shown in Fig. 4. In this state, the inductor
current goes up while VCF stays the same. The converter will go
through the sequence of S4 → S1 → S4 → S3 for the duration
D1 to D4 [17]. The timing diagram, the voltage at node VX ,
the inductor current and the flying capacitor’s voltage are also
sketched in Fig. 3(b).
Fig. 5. Comparison of the normalized output voltage ripple between 3-level
It can be observed that, in each cycle, the inductor current and buck converters and 2-level buck converters.
the flying capacitor’s voltage achieve natural balance. The ac-
tual frequency of the inductor current is twice that of the switch-
ing frequency. The ripple voltage of VCF depends on the size of
the flying capacitor and the loading current.

III. P ERFORMANCE A NALYSIS U NDER I DEAL C ONDITIONS

Assume that the 3-level buck converter is ideal, which
means there is no time mismatch, no parasitic capacitor or
no equivalent series resistor (ESR) in any of the components,
the conduction resistance of the switches is negligible and the
voltage across the flying capacitor is constantly half of Vg .
The inductor current in one cycle is sketched in Fig. 3. If VCF
is half of Vg , it has the same slope in D1 , D3 , and in D2 , D4 ,
respectively. The rising and falling slopes are annotated as m1
and m2 , respectively.
Fig. 6. Block diagram of a voltage-mode controlled 3-level buck converter.
A. Conversion Ratio
For 2-level buck converters, the output ripple is
According to the volt-second balance law
1 (1 − D)DVg TS2
m1 D 1 + m2 D 2 + m1 D 3 + m2 D 4 = 0 (1) ΔVo = . (8)
8 LC
In Case 1 (D ≤ 0.5) A comparison of the normalized output voltage ripple be-
tween 2-level and 3-level converters under the same conditions
(Vg − VCF − VO )D1 + (VCF − VO )D1 = 2VO D2 (2) is plotted in Fig. 5. Note that, a 3-level converter uses an
VO = DVg . (3) additional flying capacitor and it is assumed that CF is equal to
the output capacitor. For fair comparison, the value of the total
In Case 2 (D ≥ 0.5) capacitance is kept the same. The ripple of a 2-level converter
with equivalent capacitance is also plotted in Fig. 5. The peak
2(Vg −VO )D1 = −(Vg −VCF −VO )D2 −(VCF −VO )D2 (4) voltage ripple of the 3-level converter is only 1/8 that of the
VO = DVg . (5) 2-level converter and is 1/4 that of the 2-level converter with
equivalent capacitance.
As can be seen from (3) and (5), 3-level converters have the
same conversion ratio as 2-level converters. The same result can C. Derivation of Loop-Gain Function With the Perturbed
also be obtained by inspecting the VX voltage. SSA Method
Fig. 6 shows the block diagram of a voltage-mode controlled
B. Output Voltage Ripple 3-level buck converter. Two ramp signals and clocks with a 180◦
The output voltage ripple is introduced by the inductor phase shift are used to generate 2 switching signals D and DS .
current charging and discharging the output capacitor, as shown The loop-gain function can be divided into 2 parts: the first is
in Fig. 3. In Case 1 defined as the transfer function from the output of the error
  amplifier (EA) to the output voltage VO ; and the second is from
1 m1 D1 TS TS 1 12 −D Vo TS2 1 ( 12 −D)DVg TS2 VO to the output of the EA. The second part, which is known
ΔVo = = = .
2 2C 4 16 LC 16 LC as the compensator K(s), is to be designed to achieve a stable
(6) system. Therefore the first part of the loop-gain function will be
And in Case 2 focused on.
1 m1 D 1 T S T S 1 (−D2 +1.5D−0.5)Vg TS2 There are 3 energy-storing elements: the flying capacitor, the
ΔVo = = . (7)
2 2C 4 16 LC inductor, and the output capacitor. In each state, 3 equations can
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

TABLE I
M ATRICES

be written according to the current and voltage relationships of where E = (A1 + A3 − 2A2 )x0 + (B 1 + B 3 − 2B 2 )u0 .
the energy storing elements. For example, in S1 dˆ is determined by the control equation
dVO (t) 1 1 1 dˆ = G .
=− VO (t) + IL (t) + i2 (9) x + Hu (16)
dt RC C C
dVCF (t) 1 And it is the output result of comparing VEA with Vramp :
= IL (t) (10) K(s)VO
dt CF dˆ = . (17)
dIL (t) 1 1 1 Vm
= − VO (t) − VCF (t) + Vg . (11)
dt L L L From this G can be found.
To facilitate the discussion, 2 vectors are identified: (Here, According to [18], the open loop-gain function is
vectors are represented by boldfaced lower case letters, e.g.,  
T (s) = trace (sI − A)−1 EG . (18)
x, u; matrices are boldface upper case, e.g., A, B, C, D; per-
, u
turbed quantities are hatted letters, e.g., x  ; and derivative Substituting the obtained matrices into (18), the expression is
values are above-dotted letters, e.g., ẋ.) Vg 1
⎡ ⎤ T (s) = K(s) L
. (19)
VO (t) Vm 1 + s R + s2 LC
V
state vector : x = ⎣VCF (t)⎦ and input vector : u = g . In Case 2, the operation sequence is S4 → S1 → S4 → S3
i2
IL (t)
ẋ = (D1 A4 + D2 A1 + D3 A4 + D4 A3 )x
The above 3 equations can be written as
+ (D1 B 4 + D2 B 1 + D3 B 4 + D4 B 3 )u
ẋ = A1 x + B 1 u (12) = ((1 − D)(A1 + A3 ) + (2D − 1)A4 ) x
⎡ ⎤ ⎡ ⎤
−(1/RC) 0 (1/C) 0 (1/C) + ((1 − D)(B 1 + B 3 ) + (2D − 1)B 4 ) u
where A1=⎣ 0 0 (1/CF )⎦, B 1=⎣ 0 0 ⎦. = Ax + Bu (20)
−(1/L) −(1/L) 0 (1/L) 0
The same methodology can be applied to derive the loop-gain
According to the above analysis, each of the 4 states of the function for this case. It turns out that it has the same loop-gain
3-level converter has its corresponding state equations, as listed function as that in Case 1. Note that CF does not appear in the
above (all the matrices are listed in Table I): loop-gain function.
S1 : ẋ = A1 x + B 1 u; S2 : ẋ = A2 x + B 2 u In summary, the loop-gain function for an ideal 3-level buck
S3 : ẋ = A3 x + B 3 u; S4 : ẋ = A4 x + B 4 u. (13) converter is
Vg 1
In Case 1, the operation sequence is S1 → S2 → S3 → S2 , T (s) = K(s) L
. (21)
Vm 1 + s R + s2 LC
so the average of the vectors over one period is the time
weighted sum of the equations representing S1 , S2 , S3 , and S2 , It is the same as that of a 2-level buck converter.
as in (14):
IV. D ESIGN C ONSIDERATIONS OF I NTEGRATED 3-L EVEL
ẋ = (D1 A1 + D2 A2 + D3 A3 + D4 A2 )x
B UCK C ONVERTERS U NDER R EAL C ONDITIONS
+ (D1 B 1 + D2 B 2 + D3 B 3 + D4 B 2 )u
= (D(A1 + A3 ) + (1 − 2D)A2 ) x The analysis in Section III is based on the assumption that
D1 equals D3 and D2 equals D4 and it does not consider any
+ (D(B 1 + B 3 ) + (1 − 2D)B 2 ) u
parasitics of the power stage [19]. However, process voltage
= Ax + Bu (14) and temperature (PVT) variations are always a challenge in
integrated circuit design and it is impossible to achieve the ideal
where A = D(A1 + A3 ) + (1 − 2D)A2 and B = D(B 1 + conditions of a 3-level converter for integrated circuits.
B 3 ) + (1 − 2D)B 2 . Integrated 3-level buck converters usually have P1 , P2 , N1 ,
To apply the perturbation analysis [18] N2 , and CF fabricated on-chip, which raises a lot of practical
˙ = A
x x + Bu  + E dˆ (15) issues. For example, the chip area limits the size of CF and
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LIU et al.: ANALYSIS AND DESIGN CONSIDERATIONS OF INTEGRATED 3-LEVEL BUCK CONVERTERS 5

Fig. 7. Timing diagram of mismatches between D1 , D3 and D2 , D4 when

(a) D ≤ 0.5, (b) D ≥ 0.5.

a small CF results in large ripple of VCF . If part of CF is Fig. 8. Four types of MOS capacitors used as CF . (a) NMOS capacitor.
implemented as a MOS capacitor, it has non-negligible parasitic (b) PMOS capacitor. (c) N -cap. (d) P -cap.
capacitance. Due to the mismatch between comparators and on-
chip propagation delays, D1 , D3 and D2 , D4 will not be exactly As mentioned above, VCF should be half of Vg during
the same. All these practical issues pose a stringent challenge normal operation to maintain the switches operating within the
to the design of a robust integrated 3-level converter. safe regions and reduce the ripples. For this reason, the time
For all Cadence simulations presented in this paper, the mismatch should be kept as small as possible so as to minimize
switches: P1 , P2 , N2 , and N1 are realized by nearly ideal its periodic change.
switches that have very low on resistance (1 mΩ) and very large
off resistance (1 GΩ) and take nearly no time (1 ys) to transit B. Minimum Flying Capacitance
between the on-state and off-state. The gate signals ensure that A large flying capacitor is desired since the larger the capac-
there is no shoot-through current flow through the switches. itance of CF , the smaller the ripple of VCF . However, a larger
To verify the analysis, a 3-level buck converter is designed CF increases the chip area and its parasitic capacitance. In this
with the following specifications: Vg = 5 V, fS = 50 MHz, way, it is necessary to find the minimum CF with which the
L = 100 nH, C = 10 nF, and R = 8 Ω. For the analyses from converter can still operate normally.
Section IV-A to Section IV-D, only one kind of non-ideality is The inductor current along with the voltage across CF is
considered at a time to find its impacts. shown in Fig. 3. For Case 1, CF is charged in S1 , and dis-
charged in S3 . Assume that the nominal voltage stress of the
A. Time Mismatch Between D1 , D3 and D2 , D4 power transistors should be within half of Vg and 10% excessive
voltage is acceptable [20], then in Case 1
D and DS are generated from the comparators and SR
ΔVCF ILOAD D1 TS
latches. The comparators’ different offset voltages, gains and = ≤ 0.1VMOS (27)
other characteristics due to process variation will bring a time 2 2CF
mismatch between D and DS . The mismatch between the Assume the loading is resistive
actual gate signals will also be influenced by the propagation
ILOAD ∗ D1 TS D2 Vg TS 2.5
delay and the drivers. Especially at high-frequency operations, CF ≥ = = TS .
such as the 200 MHz in [5] with only a 5 ns switching 0.2VMOS max 0.2 ∗ 0.5Vg R max R
period, the time mismatch in the nano-second range may have (28)
a significant impact on the system performance. In Case 2
As shown in Fig. 7(a), assume that
ILOAD ∗ D2 TS
D = D1 , D3 = D1 + d1 (22) CF ≥
0.2VMOS max
D4 = D2 + d2 (23) (1 − D)DVg TS 2.5
= = TS . (29)
D1 + D2 + D3 + D4 = 1. (24) 0.2 ∗ 0.5Vg R max R
In Case 1, the change of VCF over one period is:
The ripple voltage of CF increases with the loading current and
dVCF (t) 1 1 1 decreases with the switching frequency and it is at its maximum
= IL (t)D1 + − IL (t) D3 = − IL (t)d1 .
dt CF CF CF when D = 0.5. For R = 8 Ω and TS = 20 ns, CF should be
(25) larger than 6.25 nF.
In Case 2, the change is
dVCF (t) 1 1 1 C. Parasitic Capacitor of Flying Capacitor
= IL (t)D2 + − IL (t) D4 = − IL (t)d2 .
dt CF CF CF Generally, 3 kinds of capacitors are available in bulk CMOS
(26) technologies: metal-insulator-metal (MIM) capacitors, metal-
The average of IL is the loading current. If d1 and d2 are zero, oxide-metal (MOM) capacitors, and MOS capacitors. To in-
VCF should remain constant over one period. Otherwise, VCF crease the density of the on-chip capacitors, stacking all kinds
will keep increasing or decreasing until the converter totally of capacitors in a vertical hierarchy is usually used [21], [22].
deviate from its normal operation. Note that the change of VCF The MOS capacitor has the highest density and occupies around
over one period increases linearly with the time mismatch. The 60%–70% of the total capacitance.
VCF drifting phenomena due to the unbalanced duty cycles is To implement a MOS capacitor, there are 4 methods as
also shown in [15]. shown in Fig. 8. Method 1 in Fig. 8(a) uses an NMOS to
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

implement the capacitor with the gate as the top plate and
the source and drain as the bottom. However, it is seldom
used as the body terminal is fixed to the substrate. Method 2
in Fig. 8(b) adopts a PMOS with the source and drain as the
top plate and the gate as the bottom plate. The N -well is
connected to the top plate so as to keep the voltage between
the 4 terminals of the PMOS within half of Vg . There is also
a parasitic capacitor from the N -well to the P -substrate, Cw .
Method 3 in Fig. 8(c) is called an N -cap, provided by the
technologies, with the gate as the top plate and the N channel as
the bottom plate. The N -well has a similar voltage to that of the
N channel, which is the bottom plate, and it forms a parasitic
capacitor Cw with the substrate. Method 4 in Fig. 8(d) is called
a P -cap, also provided by the technologies, with the P channel
working as the top plate and the gate works as the bottom plate.
The P -well is surrounded by a deep N -well to isolate itself
from the substrate. Similarly, the deep N -well is well biased to Fig. 9. Power loss and efficiency versus CF .
Vg and there is a parasitic capacitor Cw from the P -well to the
deep N -well.
However, different MOS capacitors have different percent-
From the above analysis, it can be summarized that the
ages of parasitic capacitance, so the power loss is not the same
flying capacitor will have a parasitic capacitor CF P , either
for these MOS capacitors. Simulated in a UMC 65 nm process,
to ground or to Vg , which affects the converter’s power loss
if the PMOS capacitor stacked with MIM capacitor and MOM
and DC operating points as will be discussed in the following
capacitor is used to implement the flying capacitor, the overall
subsections.
capacitance density is 6.6 fF/μm2 , and the parasitic capacitance
1) Power Loss: For the PMOS capacitor, in S1 and S4 ,
is 1.4% of the total flying capacitance. If the N -cap is adopted,
VCFP , the voltage across CFP , is Vg and in S2 and S3 , it is
the overall capacitance density is 6.8 fF/μm2 , and CFP is
VCF . So in every cycle, VCFP will be charged to Vg , then half
1.36% of total CF while if the P -cap is selected, the overall
of the charge will be dumped to CF , causing power loss. In S2
capacitance density is only 5.6 fF/μm2 , and CFP is as large
or S3 , CFP and CF exchange charges
as 6.33% of total CF . If CF is 6.25 nF, then CFP is around

Vg CFP + VCF CF = (CFP + CF )VCF (30) 90 pF or even 400 pF, in accordance with the type of MOS
capacitor used. Under this circumstance, CFP is comparable or
 CFP (Vg − VCF )
ΔVCF = VCF − VCF = even larger than the power switches’ gate capacitance, so the
CFP + CF ) switching loss due to CFP might dominate the total switching
CFP (Vg − VCF ) loss. This is another reason why a very large on-chip flying
≈ . (31) capacitor is not desired.
CF
Based on the Cadence simulation parameters and setups
The additional energy CF obtains from this process is
stated at the beginning of this section, and adding CFP as the
1 1
Eadd = CF (VCF + ΔVCF )2 − CF VCF 2 only parasitic while keeping all the other components ideal,
2 2 simulations are conducted to verify the power loss analysis.
≈ CF VCF ΔVCF (32) Fig. 9 shows the calculated and simulated power loss and
Eadd ≈ CFP (Vg − VCF )VCF . (33) efficiency with the above-mentioned 3 MOS capacitor con-
The total energy loss is the energy charging CFP minus the figurations when VO = 2.14 V. Some small time mismatch
additional energy CFP transfer to CF is deliberately added to maintain VCF at half of Vg during
simulation. It can be observed that the power loss increases
Eloss = Vg Qloss − Eadd linearly with CF because larger CF introduces more CFP and
≈ Vg CFP (Vg − VCF ) − CFP (Vg − VCF )VCF large CFP significantly degrades the efficiency. Among these
3 types of MOS capacitors, the converter achieves the highest
= CFP (Vg − VCF )2 . (34) efficiency with the N -cap under the same flying capacitance.
Moreover, the N -cap occupies the smallest area since it has
For the N -cap, the charges on CFP in S1 or S4 will be dumped
the highest capacitance density. Although the PMOS capacitor
to ground in S2 or S3 . Thus
has a similar capacitance density and parasitic capacitance
Eloss = (Vg − VCF )Qloss = CFP (Vg − VCF )2 . (35) percentage to that of the N -cap, N -cap is still preferred because
it has better linearity due to the process control.
For the P -cap, in S1 and S4 , VCFP is 0 and in S2 and S3 , it is 2) Additional Charge State of the Flying Capacitor: The
Vg − VCF ; thus parasitic capacitor will not only cause power loss, but will
Eloss = (Vg − VCF )Qloss = CFP (Vg − VCF )2 . (36) also bring extra charges to the flying capacitor. In the follow-
ing analysis, only the flying capacitor’s parasitic capacitor is
If VCF = Vg /2 considered. For the PMOS capacitor, when the 3-level buck
Eloss CFP 2 1 converter goes from S4 to S3 or from S1 to S2 , some charges
Ploss = = V = CFP Vg2 f. (37)
T 4T g 4 of CFP will be dumped to CF , as in (31).
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LIU et al.: ANALYSIS AND DESIGN CONSIDERATIONS OF INTEGRATED 3-LEVEL BUCK CONVERTERS 7

In Case 1
ẋ0 = (D1 A1 + D2 A2 + D3 A3 + D4 A2 + At )x0
+ (D1 B 1 + D2 B 2 + D3 B 3 + D4 B 2 + B t )u0
= ACF P x0 + B CF P u0 . (42)
With A1 to A4 and B1 to B4 staying the same as those in
Table I, the matrices can be calculated from the above
⎡ 1 1⎤ ⎡ 1⎤
− RC 0 C
0 C
ACFP = ⎣ 0 − TCCFPF 0 ⎦, B CFP = ⎣ T CFPF
C
0 ⎦.
−L 1
0 0 D
L 0
(43)
In the steady state, the derivation of x0 over one period is zero,
so the DC operating points can be calculated as follows:
⎡ ⎤ ⎡ ⎤
VO DVg
x0 = −A−1 ⎣
CFP B CFP u0 = VCF =
⎦ ⎣ Vg ⎦ . (44)
DVg
Fig. 10. Simulated VO , IL , VX , and VCF with CFP in the steady state. IL R
Since CFP charges CF in every cycle, the converter will
For the N -cap, when the 3-level buck converter goes from achieve balance when ΔVCF in (31), (39), and (40) equals zero,
S2 to S1 or from S3 to S4 , the bottom plate of CF will switch which means VCF equals Vg . The same results can be obtained
from zero to half of Vg , which means CFP will be immediately in Case 2. For CF = 6.25 nF, CFP = 85 pF and D = 40%, the
charged. The current flowing to CFP will also flow through CF , simulation waveforms are shown in Fig. 10. VO is around 2
charging VCF with V, the same as the calculation, and VCF is very close to 5 V.
The error is due to the approximation of the SSA method. In
ΔVCF CF = (Vg − VCF )CFP (38) calculation, the SSA method adopts the average value over
(Vg − VCF )CFP one period to represent the time changing signal, bringing in
ΔVCF = . (39) errors. So it is required that the inductor current ripple and
CF
the voltage ripple should be small. But under this condition,
Similarly for the P -cap, when the 3-level buck converter goes the inductor current ripple and the output voltage ripple are
from S1 to S2 or from S4 to S3 , the top plate of CF will switch becoming larger as VCF is large. Moreover, with VCF equal
from Vg to Vg − VCF , which means CFP will be immediately to Vg , VX will be either 0 or Vg , losing the property of being
charged. The current flowing to CFP will also flow through CF , half of Vg , so the converter will behave like a standard 2-level
charging VCF with converter, losing all the advantages of the 3-level operation. As
(Vg − VCF )CFP shown in Fig. 10, the frequency of the inductor current is fS , the
ΔVCF = . (40) same as a 2-level converter, rather than twice fS as it is under
CF
3-level conditions. To avoid this kind of fault behavior, the
Just like the power loss, the equation for the additional type of capacitor with smaller parasitic capacitance is preferred
charges to CF due to CFP are the same with all parasitic to implement the flying capacitor. Some operation mechanism
capacitor configurations. But the actual values vary with respect should also be deliberately added to compensate the additional
to the ratios between CFP and CF . As discussed above, with charges brought by CFP .
the N -cap, the converter achieves the best performance in
terms of efficiency and area. For this reason, in the following D. Parasitic Capacitors of Power Switches
analysis, only the N -cap, whose results are applicable to all the
conditions by changing CFP /CF , is considered. Parasitic capacitor of the flying capacitor brings power loss
In the SSA analysis under ideal conditions, only 4 states and extra charges to CF . Power switches, implemented with
are considered. Any change of the inductor current and the MOS transistors, have more parasitic capacitors, like Cgs , Cgd ,
output capacitor voltage is completely included in the 4 states. and Cds . The power losses due to these parasitic capacitors,
However, due to the parasitic capacitors, CF can be charged in which are similar to those of a 2-level buck converter, will not
an additional state, which must be included in the SSA analysis, be covered. However, the parasitic capacitors’ effect on VCF
so the voltage balance of VCF should be reconsidered. In the will be discussed in detail.
following analysis, the steady state value of x is defined as x0 Since Cgs and Cgd of the power transistors do not engage
V in charge transfer during state transitions, only Cds will be
and u0 is defined as g . considered here. For a 3-level converter, the sizes of N1 and
0
N2 are usually the same. So are P1 and P2 . To simplify
If the changes to the state vector due to the parasitic capac-
the analysis, it is assumed that CdsN1 = CdsN2 = CdsN and
itors in every cycle are fit it into the equation: ẋ0 = At x0 +
CdsP1 = CdsP2 = CdsP . For Case 1, when the converter, with
B t u0 , it can be obtained that
Cds the only parasitic capacitors, transits from S1 to S2 , as
⎡ ⎤ ⎡ ⎤ illustrated in Fig. 11.
0 0 0 0 0
At = ⎣0 − TCCFPF 0⎦ , B t = ⎣ TCCFPF 0⎦ . (41) 
CF VCF + CdsP VCF = CF VCF 
+ CdsP VCF 
−CdsP (Vg −VCF ).
0 0 0 0 0 (45)
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8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

⎡ ⎤
0 0 0
which makes Ax = ⎣0 −(2Cds /T CF ) 0⎦, B x =
0 0 0
⎡ ⎤
0 0
⎣(Cds /T CF ) 0⎦. The DC operating points in both cases
0 0
can be calculated as follows:
⎡ ⎤ ⎡ ⎤
VO DVg
⎢ Vg ⎥
x0 = ⎣VCF ⎦ = ⎣ 2 ⎦ . (56)
IL DVg
R

This shows that the parasitic capacitor Cds of the switches

helps maintain VCF at equal to half of Vg , thus guaranteeing the
correct operation of the 3-level converter. The power switches,
Fig. 11. State transition diagram with the power switches’ Cds capacitors in
Case 1.
which are implemented by 2.5-V I/O devices in a UMC 65 nm
technology, after size optimization according to the specifi-
After charge re-distribution cations stated at the beginning of this Section, have parasitic
CdsP Vg + (CF + CdsP )VCF capacitors CdsP around 10 pF and CdsN around 5 pF. The Cds

VCF = (46) capacitors can help correct VCF against the impacts of the time
CF + 2CdsP mismatch and CFP . However, the intrinsic Cds capacitance may
 CdsP (Vg − VCF )
ΔVCF = VCF − VCF = . (47) not be large enough to compete with other non-idealities as will
CF + 2CdsP be discussed in the next part. Larger capacitors at node VX
When the converter transits from S2 to S3 (from VX to ground or to Vg ) could be intentionally added to

maintain VCF at half of Vg , but it is at the cost of the extra
CF VCF − CdsP (Vg − VCF ) = CF VCF power loss the capacitors will bring.
 
− CdsP (Vg − VCF ) + CdsN VCF . (48)
E. Derivation of DC Operating Points With Time Mismatch
And after charge re-distribution and Parasitic Capacitors
 −CdsN VCF
ΔVCF = VCF − VCF = . (49) Since both the time mismatch and the parasitic capacitors
CF + CdsN + CdsP affect the state vectors’ balance over one period, we will
When the converter transits from S3 to S2 consider all of the effects in the following analysis.
Suppose that D1 , D2 , D3 and D4 have the same relationship,

CF VCF − CdsP (Vg − VCF ) = CF VCF as defined in (22)–(24), in Case 1
 
− CdsP (Vg − VCF ) + CdsP VCF . (50)
ẋ0 = (D1 A1 + D2 A2 + D3 A3 + D4 A2 + At + Ax )x0
And after charge re-distribution + (D1 B 1 + D2 B 2 + D3 B 3 + D4 B 2 + B t + B x )u0
= Atot x0 + B tot u0 . (57)
 −CdsP VCF
ΔVCF = VCF − VCF = . (51)
CF + 2CdsP From the above, the DC operating points can be calculated as
follows:
When the converter transits from S2 to S1 ⎡ ⎤
⎡ ⎤ Vg DR(CFP +2Cds )+d1 R(CFP +Cds )
 
− CF VCF − CdsP VCF = −CF VCF − CdsP VCF VO ⎢ d21 T +R(CFP +2Cds )
⎥

+ CdsN (Vg − VCF ). (52) x0 = ⎣VCF ⎦ = ⎢⎣ Vg R(C FP +Cds )−Dd1 T
d21 T +R(CFP +2Cds
⎥. (58)
⎦
IL Vg D(CFP 2
+2Cds )+d1 (CFP +Cds )
d T +R(CFP +2Cds ) 1
And after charge re-distribution
Similar results, by replacing d1 with d2 can be obtained in
 CdsN (Vg − VCF ) Case 2. If d21 T R(CFP + 2Cds ), using the aforementioned
ΔVCF = VCF − VCF = . (53)
CF + CdsN + CdsP typical value for CFP and Cds , it means d1 0.24; then the
VO term can be approximated as DV g .
After one cycle, the total voltage difference on the flying Simulations are conducted under 2 conditions, when D =
capacitor is 0.4 and when D = 0.6, to verify the above calculation. In
CdsP CdsN Fig. 12(a), the top graph plots the calculated and simulated
ΔVCF = + (Vg − 2VCF ). VO versus the time mismatch from −0.15 to 0.15, with CFP =
CF +2CdsP CF +CdsN +CdsP 85 pF and Cds = 30 pF. As can be observed from this figure,
(54)
in order to maintain the VO = DV g relationship, it is essential
Define CdsP + CdsN as Cds to keep d1 , the time mismatch smaller than 0.1 and it is best
for it to be smaller than 0.05, which is not difficult to achieve
Cds with careful circuit and layout design. The bottom graph plots
ΔVCF ≈ (Vg − 2VCF ) (55)
CF VCF versus Cds with d1 = 0.05 and CFP = 85 pF. When Cds
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LIU et al.: ANALYSIS AND DESIGN CONSIDERATIONS OF INTEGRATED 3-LEVEL BUCK CONVERTERS 9

Fig. 13. Bode plots of the approximated and accurate loop-gain function when
(a) C = 10 nF and d1 = 0.1, (b) C = 110 nF and d1 = 0.1.

Fig. 12. Calculated and simulated VO versus the time mismatch and VCF After removing the second order components
versus Cds when (a) D = 0.4, (b) D = 0.6.
˙ = (D(A1 +A3 )+d1 A3 +(1−2D−d1)A2 +At +Ax ) x
x 
+ (D(B 1 +B 3 )+d1 B 3 +(1−2D−d1)B 2 +B t +B x ) u 
is large, VCF is closer to half of Vg . However, this effect is ˆ
+ [(A1 + A3 − 2A2 )x0 + (B 1 + B 3 − 2B 2 )u0 ] d
not significant when it is below 300 pF, while its reasonable
value is around 30 pF for the transistors. The results shown  + B tot u
= Atot x ˆ
 + E d. (60)
in Fig. 12(b) are simulated under the same condition as (a) E = (A1 + A3 −2A2 )x0 + (B 1 + B 3 −2B 2 )u0 , the same
except that D = 0.6. Similarly, when d2 is smaller than 0.1, as the ideal condition.
VO ≈ DV g even though VCF might deviate from 2.5 V. But dˆ is determined by the same control equation (16). Since the
VCF is quite sensitive to all the parasitics as shown in (58). controller is the same as before, both G and H are same as the
If VCF is not half of Vg , the power transistors will not work ideal condition.
in the safe operation regions and the ripple reduction effect As discussed above, the open loop-gain function is [18]
will be degraded, implying that there should be a calibration or  
balancing mechanism for the voltage across the flying capacitor. T (s) = trace (sI − Atot )−1 EG . (61)
Some recent state-of-the-art methods have been developed to Substituting the obtained matrices into (61), the solution is
successfully calibrate VCF [23], [24]. given in (62), shown at the bottom of the page, with CFT
As can be observed, the calculated results are quite close to defined as CFP + 2Cds .
the simulation results. The error is due to the approximation of It has 1 zero of CFT /T CF and 3 poles (1 real pole
the SSA method. and 2 complex poles), as in the form of (1 + (s/ω1 ))(1 +
(1/Q)(s/ω0 ) + (s2 /ω02 ). Comparing the expanded terms with
the denominator as in (63) and (64)
F. Derivation of Loop-Gain Function With Time Mismatch 1 s s 1 1 1
and Parasitic Capacitors 1+ + + s2 + 2 s2 + 2 s3 (63)
Q ω0 ω1 Qω0 ω1 ω0 ω0 ω1
As analyzed above, with the time mismatch and the parasitic T d21 L T (CF + d21 C) T LCF 2
capacitors, the DC operating points of a 3-level buck converter +1+ s+ s+ s
RCFT R CFT RCFT
differ from the ideal one. The dynamic performance, especially T LCCF 3
the loop-gain function could also be different. Since the loop- + LCs2 + s (64)
CFT
gain function is essential in determining the compensation, it is
vital to find the loop-gain function with all the non-idealities. it can observed that if
In Case 1, we apply the perturbation analysis to (57) T d21
1 and d21 C CF (65)
 RCFT
ẋ0 + x˙ = (D + d)(Aˆ 1 + A3 ) + d1 A3
then the 3 poles and Q are
   

+ 1 − 2(D+ d̂)−d1 A2 +At + Ax (x0 + x ) CFT CFT T CF 1
ω1 = , ω0 = ∗ =
+ ((D + d)Bˆ 1 + B 3 ) + d1 B 3 T CF T LCCF CFT LC 
+ (1 − 2(D + d) ˆ − d1 )B 2 + B t + B x )(u0 + u  ). C
and Q = R . (66)
(59) L

Vg R(CFT + T CF s)
T (s) = K(s) (62)
Vm T d21 + RCFT + LCFT s + T R(CF + d21 C)s + T LCF s2 + LRCCFT s2 + T LRCCF s3
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10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 14. Bode plots of approximated and accurate models and time-domain Fig. 15. Bode plot of approximated and accurate models and time-domain
simulation results with different time mismatch when C = 10 nF. simulation results with different time mismatch when C = 110 nF.

ω1 equals the zero and the complex poles are contributed by

the power stage, the same as in the ideal condition. Finally, the
approximated loop-gain function is obtained as below
Vg 1
T (s) = K(s) L
. (67)
Vm 1 + s R + s2 LC
The same loop-gain function can also be derivedin Case 2.
To guarantee
 (65), d1 should be much smaller than RCFT /T
and CF /C. Before designing the compensator, we regard
K(s) as 1 when analyzing the Bode plot of T (s). For the
previous power stage specifications with d1 = 0.1, the Bode
plots of the accurate loop-gain function and the approximated Fig. 16. Experimental setup to test the 3-level buck converter system’s loop-
model, with no obvious difference, are shown in Fig. 13(a). gain function.
For C = 110 nF instead of the 10 nF for some cases, (65)
B. Simulation Results
requires d1 much smaller than 0.24. If d1 is still 0.1, as given in
Fig. 13(b), the Bode plots of the two loop-gain functions have For the following Cadence simulations, the control loop is
different locations of the complex poles. built with ideal comparators and logic circuits, which have an
It can be concluded that if the time mismatch is controlled infinite slew rate and negligible delay, rise time and fall time.
according to (65), the loop-gain function is very close to that Two power stage configurations are selected for simulation.
under the ideal condition. However, if the time mismatch is For the first one, the power stage is the same as that stated
out of the controlling range, the 3-level converter cannot be at the beginning of Section IV. CF is 6.25 nF, and for Cds ,
approximated as a 2-level converter for compensation. CdsN = 5 pF, and CdsP = 10 pF. The simulation is conducted
at VO = 3.4 V. With this power stage, the time mismatch is
V. V ERIFICATION BY S IMULATION easy to meet the requirement of using the approximated model.
Two conditions are simulated: 1) CFP = 85 pF, d2 = 0.03; and
To validate the derived loop-gain function, a time-domain
2) CFP = 400 pF, d2 = 0.12. The simulation results together
small signal injection simulation is conducted [25].
with the approximated loop-gain function and the accurate
loop-gain function under the second condition are shown in
A. Time-Domain Small Signal Injection Simulation Fig. 14. With this power stage, the accurate model is close to
The loop is broken at the output of the EA. A small signal, the approximated model even with a large time mismatch. As a
which is a sinusoidal signal with small magnitude at a given result, the 2 simulated Bode plots almost coincide with each
frequency, is injected where the loop is broken. The small signal other, indicating the correctness and accuracy of the derived
passes through the controller and the power stage and finally model. After 20 MHz, the small signal gain is smaller than 1
appears at VO with a gain in magnitude and a shift in phase, and the switching noise becomes so significant that accurate
which represents the control-to-output small signal behavior results cannot be obtained through this method. Fortunately,
without the compensator. The magnitude of the small signal the aggressive bandwidth of a switching converter is limited to
should be small enough that it does not affect the DC operating around 1/5 of its switching frequency, which is 10 MHz, so the
points of the converter. loop-gain function after 20 MHz is not of interest.
Fourier analysis is then carried out on VO . The magnitude For the second power stage, everything is the same except
and phase of the signal in the same frequency as the input small that C is 110 nF instead of 10 nF for better comparison. As
signal can be extracted, which represents the response at this aforementioned, 2 conditions are simulated: 1) CFP = 85 pF,
frequency. By sweeping the frequencies of the injected signal, d2 = 0.03; and 2) CFP = 400 pF, d2 = 0.12. Bode plots of the
the frequency response of the whole picture is obtained. approximated model and the accurate model under the second
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LIU et al.: ANALYSIS AND DESIGN CONSIDERATIONS OF INTEGRATED 3-LEVEL BUCK CONVERTERS 11

Fig. 17. Measured Bode plots of a 3-level buck system. (a) CO = 10 nF with small mismatch. (b) CO = 10 nF with large mismatch. (c) CO = 110 nF with
small mismatch. (d) CO = 110 nF with large mismatch.

condition, and the 2 simulation results are shown in Fig. 15. As its peak output voltage ripple is much smaller than that of a
can be observed, for the first condition, when d2 is small, the 2-level buck converter.
approximated loop-gain function can be applied, while for the For an integrated 3-level converter under practical condi-
second condition, when d2 is large, even though the converter tions, the implementation of a flying capacitor and the effects
is with the same L, R, and C values, the simulated loop-gain of time mismatch and the power stage’s parasitic capacitors
function has a significant difference from the approximated are thoroughly discussed. The time mismatch and the flying
model, but matches the derived accurate loop-gain function. capacitor’s parasitic capacitor can cause the voltage across the
flying capacitor to deviate from half of Vg while the large
VI. E XPERIMENTAL V ERIFICATION parasitic capacitors at VX can help maintain VCF to half of Vg .
Even including the drain-to-source capacitors, the analysis
A 3-level buck converter system was designed with UMC indicates that a calibration mechanism to keep VCF to half
65 nm CMOS process for experimental verifications. The pa- of Vg , is necessary to guarantee the safe voltage stress of the
rameters of system are as follows: Vg = 5 V, VO = 1 V to power switches and the correct operation of the converter. In
4 V, IO,MAX = 700 mA, L = 100 nH, CO = 10 nF/110 nF, terms of the system’s loop-gain function, the time mismatch
and CF ≈ 6 nF. A voltage-mode controller with a type-III needs to be kept within an acceptable range in (65) so that the
compensator was built for stable operation. The measurement 3-level buck converter can maintain the same loop-gain func-
setup is shown in Fig. 16. The procedures are as follows: 1) the tion as a 2-level buck converter, as verified with time-domain
loop is broken at VO ; 2) a DC operating point is set with a high small signal analysis and measurement results.
precision DC supply; 3) an AC small signal from HP4194A
Gain/Phase analyzer is injected through a bias tee; 4) the gain
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[9] T. Song, N. Huang, and A. Ioinovici, “A zero-voltage and zero-current Philip K. T. Mok (S’86–M’95–SM’02–F’14) re-
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May 2013. Hong Kong University of Science and Technology,
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[13] F. Sluijs, H. Neuteboom, and M. Breedveld, “An on-chip USB-powered from the University of Toronto, and the Teaching Excellence Appreciation
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process,” in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, He is also a co-recipient of the Best Student Paper Award twice in 2002 and
CA, USA, Feb. 2000, pp. 440–441. 2009 IEEE Custom Integrated Circuits Conference. He has been a member
[14] T. A. Meynard, Analysis and Design of Multicell DC/DC Converters of the International Technical Program Committees of the IEEE International
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[15] T. A. Meynard, M. Fadel, and N. Aouda, “Modeling of multilevel to 2016. He has served as a Distinguished Lecturer for the IEEE Solid-State
converters,” IEEE Trans. Ind. Electron., vol. 44, no. 3, pp. 356–364, Circuits Society from 2009 to 2010, as an associate editor for IEEE J OURNAL
Jun. 1997. OF S OLID -S TATE C IRCUITS from 2006 to 2011, IEEE T RANSACTIONS ON
[16] M. Fadel and T. A. Meynard, “Fixed frequency control laws for multicell C IRCUITS AND S YSTEMS —I from 2007 to 2009 and has served again since
chopper,” in Proc. 9th Eur. Conf. Power Electron. Appl., Graz, Austria, 2016, and IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS —II from
2001. 2005 to 2007 and from 2012 to 2015.
[17] G. Villar and E. Alarcon, CMOS Integrated Switching Power Converters.
New York, NY, USA: Springer, 2011.
[18] W.-H. Ki, “Signal flow graph in loop gain analysis of DC-DC PWM CCM Junmin Jiang (S’09) received the B.Eng. degree
switching converters,” IEEE Trans. Circuits Syst. I, Fundam. Theory in electronic and information engineering from
Appl., vol. 45, no. 6, pp. 644–655, Jun. 1998. Zhejiang University, China in 2011. He joined the
[19] X. Liu, C. Huang, and P. K. T. Mok, “Dynamic performance analysis of Department of Electronic and Computer Engineer-
3-level integrated buck converters,” in Proc. IEEE Int. Symp. Circuits ing, The Hong Kong University of Science and Tech-
Syst., Lisbon, Portugal, May 2015, pp. 2093–2096. nology in 2013 and is currently working toward the
[20] “UMC 65 nm LOGIC and MIXED_MODE low leakage 2.5 V IO Ph.D. degree.
MOSFET SPICE model document,” United Microelectronics Co., 2009, His research interest is power IC design, espe-
p. 14. cially in switched capacitor power converter design.
[21] J. Jiang, Y. Lu, C. Huang, W.-H. Ki, and P. K. T. Mok, “A 2-/3-phase He was the recipient of both the Analog Devices
fully integrated switched-capacitor DC-DC converter in bulk CMOS for Inc. (ADI) Outstanding Student Designer Award and
energy-efficient digital circuits with 14% efficiency improvement,” in International Solid-State Circuits Conference (ISSCC) Student Travel Grant
Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, Award in 2015.
Feb. 2015, pp. 366–367.
[22] C. Huang and P. K. T. Mok, “An 84.7% efficiency 100-MHz package
bondwire-based fully integrated buck converter with precise DCM oper- Wing-Hung Ki (S’86–M’91) received the B.Sc. de-
ation and enhanced light-load efficiency,” IEEE J. Solid-State Circuits, gree from the University of California, San Diego,
vol. 48, no. 11, pp. 2595–2607, Nov. 2013. CA, USA, in 1984, the M.Sc. degree from the
[23] J. Xue and H. Lee, “A 2 MHz 12-to-100 V 90%-efficiency self-balancing
California Institute of Technology, Pasadena, CA,
ZVS three-level DC-DC regulator with constant-frequency AOT V2 con- USA, in 1985, and the Ph.D. degree from the Univer-
trol and 5 ns ZVS turn-on delay,” in Proc. IEEE Int. Solid-State Circuits sity of California, Los Angeles, CA, USA, in 1995,
Conf., San Francisco, CA, USA, Feb. 2016, pp. 226–227. all in electrical engineering.
[24] X. Liu, C. Huang, and P. K. T. Mok, “A 50 MHz 5 V 3 W 90% efficiency
He worked for Micro Linear Corporation in
3-level buck converter with real-time calibration and wide output range San Jose, CA, USA, from 1992 to 1995. He then
for fast-DVS in 65 nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, joined the Hong Kong University of Science and
Honolulu, HI, USA, Jun. 2016.
Technology in 1995, where he is now a Professor
[25] D. Ma, V. H. S. Tam, W.-H. Ki, and H. Y. H. Lam, “A CAD simulator with the Department of Electronic and Computer Engineering. His research
based on loop gain measurement for switching converters,” in Proc. IEEE interests include power management integrated circuits, micro-power energy
Int. Symp. Circuits Syst., Vancouver, Canada, BC, May 2004, vol. 5, harvesting circuits, biomedical implantable devices, and fundamental research
pp. 940–943.
in analog integrated circuit analysis and design. Prof. Ki served as an Associate
Editor of the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS II from
2012 to 2013, and the International Technical Program Committee of the IEEE
Xun Liu (S’12) received the B.Eng. degree in elec- International Solid-State Circuits Conference from 2010 to 2014.
tronic and information engineering from Zhejiang
University, China, in 2011. She joined the Depart-
ment of Electronic and Computer Engineering, the
Hong Kong University of Science and Technology,
Hong Kong, China, in 2012 and is currently working
toward the Ph.D. degree.
Her research interest includes power management
IC and analog IC design, especially in high fre-
quency DC-DC converters, 3-level buck converters,
and power amplifier supply modulators design.