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A Design of a High Efficiency DC-DC Buck

Converter with Two-Step Digital PWM and
Low Power Self Tracking Zero Current
Detector for IoT Applications

Sang-Yun Kim, Young-Jun Park, Imran Ali, Truong Thi Kim Nga, Ho-Cheol Ryu, Zaffar
Hayat Nawaz Khan, Seong-Mun Park, Student Member, IEEE,
YoungGun Pu, Minjae Lee, Keum Cheol Hwang, Youngoo Yang, Member, IEEE, and Kang-
Yoon Lee, Senior Member, IEEE1

Abstract: In this paper, a high efficiency DC-DC Buck Converter with two-step Digital Pulse Width

Modulation (DPWM) and low power Self Tracking Zero Current Detector (ST-ZCD) is proposed for

Internet of Things (IoT) and ultra-low power applications. The Hybrid DPWM Core with high linearity

and low power consumption is proposed to implement the high efficiency DPWM DC-DC Converter.

It is composed of a two-step delay control using the Counter and Delay Line. An Adaptive Window

Analog to Digital Converter (ADC) is proposed to reduce the output voltage ripple within 20 mV. A

dead time generator is implemented with the proposed ST-ZCD to minimize the reverse current. The

ST-ZCD can improve efficiency by reducing the control loss that accounts for a large proportion of the

DC-DC Converter. Also, all digital Type-III Compensator is implemented for the low power and small

die area. This chip is fabricated with a 55 nm CMOS process, which uses the standard supply voltage

of 1.5 ~ 3 V to generate the output voltage of 1.2 V. The total active area is 500 µm x 300 µm. The

measured peak efficiency of the DPWM DC-DC Buck Converter is 91.5 % with a quiescent current

consuming only 130 µA.

Keywords: Adaptive Window ADC, DC-DC Buck Converter, Digital Compensator, Digital Pulse
Width Modulation, Hybrid DPWM Core, Self Tracking Zero Current Detector.

This work was supported by Institute for Information & communications Technology Promotion(IITP) grant funded by the Korea
government(MSIP) (No.B0717-16-0057,Development of MST integrated 15W magnetic induction/resonance wireless charging
technology)

S.-Y. Kim, Y.-J. Park, I. Ali, T.T.K Nga, H.-C Ryu, Z.H.N. Khan, S.-M Park, Y.G. Pu, K. C. Hwang, Y.G. Yang, and K.-Y. Lee
are with the College of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746, Korea.
(corresponding author to provide phone: +82-31-299-4954; fax: +82-31-299-4629; e-mail: klee@skku.edu).

M. Lee is with the School of Information and Communications, Gwangju Institute of Science and Technology, Gwangju, 61005,
Korea

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I. INTRODUCTION

Recently, an Internet of Things (IoT) has been developed with a reduced size is minimized to

enhance flexibility in response to customers’ needs. The IoT applications are developed to operate for

years without replacing the battery. However, the lifetime and charging technology of the battery have

not kept up with the demand of IoT. Therefore, the attention paid to developing power management

techniques is gradually increasing in response to the need to solve low power requirements [1].

Digital controllers could be a very attractive solution in low-to-medium power DC-DC Buck

Converters because of their inherently lower sensitivity to process variation and programmability, as

well as their reduction or elimination of passive components for tuning without compromising dynamic

performance, simplicity or cost [2]-[5]. Furthermore, it is relatively easier to design an advanced

control algorithm using a digital approach to achieve optimal transient performance.

On the other hand, despite of these advantages, the output voltage ripple of conventional Digital

Pulse Width Modulation (DPWM) based DC-DC Buck Converter is proportional to the resolution of

DPWM. To improve the ripple characteristics of output voltage, the resolution of the Analog to Digital

Converter (ADC) must be increased. Therefore, as the DPWM has a higher resolution for lower output

voltage ripple characteristics, the current consumption and area of the DPWM are increased. It makes

some of DPWM’s advantages disappear [5]-[6]. In order to design a digital DC-DC converter with the

low power, the resolution needs to be lowered requiring the circuit compensation. In addition, when the

DC-DC Buck Converter is operated in the Discontinuous Conduction Mode (DCM) region, it needs

functions to prevent the reverse current. The conventional DC-DC Buck Converter prevents the reverse

current with the Zero Current Detection (ZCD) [7]. The conventional ZCD structure senses the zero

current through the internal switching (VX) node; it has a voltage drop caused by the resistance

component of the Power metal-oxide-semiconductor field-effect transistor (MOSFET). Also, the power

consumption required by the conventional ZCD to sense the point of the zero inductor current using the

high performance comparator is considerable [8].

In this paper, a high efficiency DC-DC Buck Converter with two-step DPWM and low power Self

Tracking Zero Current Detector (ST-ZCD) is proposed. The Hybrid DPWM Core with high linearity

and low power consumption is proposed to implement the high efficiency DPWM DC-DC Converter.

It is composed of a two-step delay control using the Counter and Delay Line, where the Most

Significant Bit (MSB) of the DPWM duty value is determined by the counter based method which has

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high linearity and he Least Significant Bit (LSB) of the DPWM duty value is determined by the Delay

Line method which has low power consumption. An Adaptive Window ADC is proposed to reduce the

output voltage ripple within 20 mV. A dead time generator is implemented with the proposed ST-ZCD

to minimize the reverse current. The ST-ZCD can improve efficiency by reducing the control loss that

accounts for a large proportion of the DC-DC Converter in the light load current conditions. As a result,

process, voltage and temperature (PVT) characteristic and current consumption of DC-DC Converter

are enhanced with ST-ZCD optimized for DPWM in DCM. Also, all digital Type-III Compensator is

implemented for the low power and small die area.

The remainder of this paper is structured as follows: Section II architecture of DPWM DC-DC Buck

Converter. Section III explains the building blocks. In Section IV, the experimental results are

discussed. Section V presents the conclusion.

II. ARCHITECTURE OF DPWM DC-DC BUCK CONVERTER

The conventional structure of the DPWM DC-DC Buck Converter is composed of a Power

MOSFET, External Components, a Gate Driver, and a Digital Controller as shown in Fig. 1. The

rectangular wave signal is generated by the DPWM to control the on-time and off-time of Power

MOSFET switches in each switching period. The output voltage (VOUT) is adjusted to the desired value.

In order to obtain good performances, the three functional blocks (DPWM, Compensator, and ADC),

should be well-designed [9].

Gate Power
Driver MOSFET

VBAT
VBAT
External
Duty_Out H-SIDE
Component
VX L1 VOUT
VBAT
L-SIDE C1
RL
RESR

ADC_ R1
COM VFB
OUT
DPWM Compensator ADC
R2

VCLK

Fig. 1. Conventional DPWM DC-DC Buck Converter.

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Fig. 2 (a) and 2 (b) shown the conventional DPWM which is composed of Counter or Delay Line

based method for controlling the duty of Power MOSFET gate signals. The Counter based method has

good linearity and high resolution. On the other hand, frequency of clock is increased depending on

number of bit. Therefore, it causes the current consumption to be increased [9]. If the Delay Line based

method is used, there is a problem that the linearity according to PVT. In addition, if the Delay Line

based DPWM need to larger delay, area is increased proportionally [10].

VCLK S
SR Q Duty_Out
Counter Latch
Digital R
COM Comparator

(a)

VCLK •••

COM MUX

S
SR Q Duty_Out
Latch
R

(b)

Fig. 2. Block diagram of the conventional DPWM with Counter (a) and Delay Line based (b) method

Generally, the Counter based method requires high frequency as it demands high linearity. Therefore,

it consumes a large amount of current. The Counter based method is directly dependent on the number

of counter bits (n) of the counter and the switching frequency (f SW) as shown in Eq. (1).

(1)

For example, if a 10-bit counter is used and the fSW is 2 MHz, the frequency of the oscillator (fCLK)

should be at least 2 GHz, which requires enormous power dissipation for the Hybrid DPWM Core.

In contrast, the Delay Line with the Digital Delay-Locked Loop (DLL) occupies a very large area as

the number of bits is increased [3]. In the case of using only Delay Line with Digital DLL, the required

number (DLLNUMBER) of delay lines in the DLL is related to the number of counter bits (n), as shown in

Eq. (2).

(2)

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Generally, the compensator in DPWM DC-DC converters are implemented by external

microcontrollers, field programmable gate arrays (FPGAs) and compact reconfigurable input output

(cRIO) modules [11]-[13]. Therefore, the compensator in conventional architecture has large current

consumption and area.

The resolution of ADC is related with the ripple of VOUT, and higher resolution of ADC makes

enhanced regulation characteristic of VOUT. Ideally, the resolution of DPWM should be greater than or

equal to compensator, which can be greater than or equal to ADC to avoid limit cycling. It is depicted

mathematically by Eq. (3).

(3)

As the resolution of the ADC is increased for enhancing characteristic of V OUT, current consumption

and area of the ADC is increased. There is a problem that total area and complexity of DPWM is also

increased for improving resolution of the compensator and DPWM with the ADC high resolution by

equation (3).

Thus, the conventional DPWM DC-DC Buck Converter is not suitable for light load applications due

to the higher power dissipation and large area in each block and lower switching frequency that result

in poor efficiency.

Fig. 3 shows the overall architecture of the proposed DPWM DC-DC Buck Converter. It is

composed of a Hybrid DPWM Core, Adaptive Window ADC, Digital ST-ZCD, Type-III Digital

Compensator, Power Stage, and Gate Driver. The Adaptive Window ADC takes the feedback voltage

(VFB) from the output (VOUT). The output of the Adaptive Window ADC is applied to the Digital

Compensator, which generates the A0, B0 signals for the duty information. The Type-III Digital

Compensator determines the delay control information (COM<5:0>) of the DPWM.

Proposed Hybrid DPWM Core, by mixing the Counter based method and Delay Line method, is

designed to implement the high linearity and low power consumption. The Most Significant Bit (MSB)

of the DPWM duty value is determined by the Counter based method which has high linearity. The

Least Significant Bit (LSB) of the DPWM duty value is determined by the Delay Line method which

has low power consumption. The Hybrid DPWM Core is proposed to implement the wide delay control

range with the fine resolution. It is composed of a two-step delay control using the Counter and Delay

Line. The coarse and fine delays are implemented with the digital Counter and Delay Line, respectively.

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Gate Power
VBGR Clock Gen. Driver MOSFET
VCLK VBAT
VBAT
62.5ns (16MHz) External
H-SIDE
M0 Component
Duty_Out
Vx H-SIDE L-SIDE L1 VOUT
VX
Digital VBAT
C1
ST_ZCD L-SIDE_IN L-SIDE RL
M1
RESR

VBGR
BGR

Hybrid COM Adaptive

Type-III A0 VFB R1
DPWM Core <5:0> Window ADC
Digital
(Counter + B0
Reset Compensator
Delay Line) R2
Digital
Controller

Fig. 3. Top block diagram of the DPWM DC-DC Buck Converter.

The resolution of the proposed DPWM DC-DC Buck Converter is 6-bit considering the power

dissipation and area. By reducing the resolution of the Hybrid DPWM Core with a Digital

Compensator and adapting a low current consumption circuit, this DC-DC Converter only consumes a

current of up to 130 µA. However, a high output voltage ripple can occur due to the low resolution of

6-bit [14]. To reduce the high output voltage ripple, the Adaptive Window ADC is proposed. A trade-

off is needed between the regulation speed and the accuracy of the Window ADC. Therefore, the input

range of the Adaptive Window ADC is adaptively selected by the feedback voltage (VFB) to reduce the

output voltage ripple to within 20 mV. Also, the Adaptive Window ADC is proposed for enhancing

characteristic of VOUT with smaller current consumption and area by controlling reference voltage of

the ADC adaptively instead of higher resolution.

The proposed compensator is implemented with the Type-III digital compensator considering the

phase margin and crossover frequency in the digital domain by the Tustin’s method, so its current

consumption and area are minimized.

The proposed DPWM DC-DC Buck Converter does not need the dead-time generator to prevent the

leakage current when the p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) are turned on

at the same time. The ST-ZCD is proposed to replace the conventional dead-time generator.

The conventional ZCD has a large power consumption to sense the zero inductor current point using

the high performance comparator. In additional, the comparator in the conventional ZCD has the

voltage offset and is sensitive to the PVT variations [8]. The ST-ZCD senses the pulse of the high side

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duty, low side duty and VX node without using comparators to reduce the current consumption. The

ST-ZCD controls the NMOS duty so that it follows the fine duty. The ST-ZCD prevents the reverse

current and minimizes the operating current.

The low power consumption DPWM DC-DC Buck Converter is proposed which is composed of a

Hybrid DPWM Core, Adaptive Window ADC, Digital ST-ZCD, Type-III Digital Compensator, Power

Stage, and Gate Driver. This proposed scheme can reduce the output voltage ripple and the power

dissipation increasing the Power Conversion Efficiency (PCE).

III. BUILDING BLOCKS

A. Hybrid DPWM Core

Fig. 4 shows the Hybrid DPWM Core circuit. The Hybrid DPWM Core generates the duty of the

DPWM DC-DC Buck Converter following the resolution of DPWM. This block ultimately determines

the resolution of the DPWM DC-DC Buck Converter. The resolution of an analog DC-DC Buck

Converter is very fine, whereas that of the digital DC-DC Converter is limited. Therefore, the accurate

duty is one of the most important characteristics in the digital DC-DC Converter. The proposed Hybrid

DPWM Core is composed of a Counter and a Delay Line using a Digital DLL based method.

DPWM Digital DLL Delay Line

Hybrid Core Fine Delay with Digital
(Counter + Delay Line) Tunning DLL
CNT_COMP
VCLK CNT
Counter Digital
Comparator D1 D2 D7 D8
COM<5:3>

COM<2:0>
Delay Delay CLK3 8 to 1 MUX
Clock Clock
Digital Delay Set MUX_SEL
CLK2
COM<5:0> COM<5:3> Comparator Clock A B Duty_Out
M1 Set
M8 Fall Edge Rising Edge
Reset_T
Reset

Fig. 4. Block diagram of the Hybrid DPWM Core.

The overall structure is similar to that in [14], but the delay cells have an adjustable delay as shown

in Fig. 4. The Counter based method can achieve high accuracy based on linearity, but the operating

frequency is dominated by the number of counter bits. It increases the current dissipation. The Delay

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Line with Digital DLL methods consume less current than the Counter based method, but this method

also has a disadvantage. With the Counter based method, when the number of bits is increased by one

bit, the active area is doubled. Therefore, the Hybrid DPWM Core can overcome this disadvantage by

combining the counter based method with the Delay Line method. The resolution of the proposed

DPWM DC-DC Buck Converter is 6-bit considering the power dissipation and area.

Fig. 5 shows a timing diagram of the Hybrid DPWM Core. Duty_Out is the time interval between

the rising edges of Set and Reset_T signals and it is controlled by the counter based on the MSB 3-bit

(COM<5:3>) and LSB 3-bit (COM<2:0>) from the Delay Line with the Digital DLL. The Counter

measures the cycles of the 16 MHz Clock from 0 to 7. This counter value generates the total duty signal

compared with the MSB 3-bit (COM<5:3>) in the digital comparator. The resolution of the Delay Line

with Digital DLL is decided by LSB 3-bit (COM<2:0>) for selecting the number of unit delays to

generate the fine duty, Duty_Out. The delay control block is fed back to match the period of the delay

cell. The delay signal (M1 ~ M7) is compared with the output signals of the delay cells to match the

fine duty. The output signals are continually changed to reduce any error duty.

VCLK
TCLK

CNT 110 111 000 001 010 011 100 101 110 111

Set
(V)

CNT_COMP
Counter based CNT_COMP falling edge
(V)
method à MUX_SEL is high

D2 D7
Delay Line D1 ... D8 ...

MUX_SEL Set rising edge

(V) à Duty_Out rising edge

Delay Line based

Reset_T method
(V)

Duty_Out
Duty_Out falling
Duty_Out COM<2:0>
edge is selected
(V) COM<5:3> by COM<2:0>

Fig. 5. Timing diagram of the Hybrid DPWM Core.

B. Adaptive Window ADC

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Fig. 6 shows the circuit of the Adaptive Window ADC. To implement a fast operation with low

power dissipation, a flash ADC type is used with two high speed comparators which minimize the

effect of the offset and noise. The Adaptive Window ADC compares the Band Gap Reference (VBGR)

designed according to the concept in [15] with 460 mV, with the output sensed by the feedback voltage

signal (VFB) to separate the error code. The size of the window is a dominant factor for the regulation

speed and accuracy.

VBAT Adaptive
Enabled Adaptive
Generator
D_FF Window
VBGR
ADC
BGR_FEEB
VAD

A2
A1
Reference
Generator VREF_H2
Shifter Register
MUX
VREF_H1 A0
VAD A1 A2 A0
VFB
Adaptive VAD
Window VREF_L2
B0 B0

VREF VREF_L1 MUX VCLK

VREF_H2 VREF_H1

VREF_L2 VREF_L1 Adaptive Window ADC Core

Fig. 6. Block diagram of Adaptive Window ADC.

If a small window size is selected, the accuracy of the output voltage is improved, although the

regulation speed becomes slow and operates abnormally. Therefore, the Adaptive Window ADC is

used to optimize the window size following the output signal.

For the first time, the VFB input signal is compared with VREF_H1 and VREF_L2 and it generates 2-bit

error signals with values of 00, 01, and 11 which are stored in the Shift Register. The Shift Register is

synchronized with the reference clock signal, VCLK.

Fig. 7 shows the timing diagram of the Adaptive Window ADC. If the AD signal is turned off,

VREF_H1 and VREF_L1 are selected and a high output voltage ripple of up to 50 mV is obtained. On the

other hand, if the AD signal is turned on, the compared voltages, VREF_H2 and VREF_L2, are selected to

reduce the window size and limit the output voltage ripple by up to 20 mV after two clocks. The AD

signal controls the 2x1 MUX to select the window size. The 6-bit output of Adaptive Window ADC is

the input of the Digital Compensator for matching.

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VFB (V) VREF_H2

VREF_H1 Adaptive Window ADC

50mV 20mV
VREF_L1
VREF_L2

A0 (V) Time

A1 (V) Time

A2 (V) Time

VCLOCK (V) Time

62.5ns(16MHz)

`
AD (V) Time

50mV Output Ripple 20mV Output Ripple

Period Period
Time

Fig. 7. Timing diagram of Adaptive Window ADC.

C. Digital Self Tracking Zero Current Detector (ST-ZCD)

The conventional ZCD structure senses the zero current through the internal switching (VX) node; it

has a voltage drop caused by the resistance component of the Power MOSFET. Also, the power

consumption required by the conventional ZCD to sense the point of the zero inductor current using the

high performance comparator is considerable [8].

Fig. 8 shows a block diagram of the proposed Digital ST-ZCD. The current consumption of the

Digital ST-ZCD is 10 μA, which is smaller than that of the conventional ZCD. Therefore, the Digital

ST-ZCD can improve efficiency by reducing the control loss that accounts for a large proportion of the

DCM DC-DC Converter in light load current conditions. It is also possible to prevent the efficiency

reduction due to ZCD timing errors caused by the comparator offset. Also, the detection timing error of

the Digital ST-ZCD does not cause instability or malfunction under the PVT variations, even though it

is larger than the resolution of the digitally controllable pulse generator.

In the proposed Digital ST-ZCD, the comparator is not used when it detects the point at which the

inductor current is 0 A. On the other hand, the Digital ST-ZCD detects the inductor current indirectly at

the time of the switch off in the previous period while monitoring the VX node voltage for the NMOS

switching at every cycle. If an NMOS switch is quickly turned off, the energizing current in the

10

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inductor must de-energize through the NMOS diode conduction. In this case, the value (S1, S2) which

is made from a flip-flop with VX and DELAY_1 or DELAY_2 is (0, 0). If (S1, S2) is (0, 0), the input of

the UP/DOWN Counter of the Digital ST-ZCD circuit is the UP signal. The pulse width of the L-

SIDE_IN signal is increased as the output signal of the UP/DOWN Counter, DUTY_CONT<7:0>, is

increased.

Self Tracking Zero Current Detector

VX Sensing L-SIDE Pulse 3ns Resolution
L-SIDE L-SIDE Width Control
VX S1
VX D Q
H-SIDE L-SIDE_IN
Flip
H-SIDE DELAY Flop
STAY Digitally
Controllable Pulse
DELAY_1

VX UP
S2
D Q UP/ DUTY_CONT<7:0>
DELAY Flip DOWN
Flop DN Counter

DELAY_2
H-SIDE

Fig. 8. Block diagram of the Digital ST-ZCD.

In contrast, if the NMOS switch is turned off late, (S1, S2) is (1, 1). In this case, the inductor

energizing current must be de-energized through the PMOS diode conduction when NMOS is turned

off, and the DN signal is made for the input of the UP/DOWN Counter. The pulse width of the L-

SIDE_IN signal is decreased as the output signal of the UP/DOWN Counter, DUTY_CONT<7:0>, is

decreased. Through the operation of the Digital ST-ZCD, when the digitally controllable pulse

generator is thereby generating a suitable pulse width values, the signals (S1, S2) is (0,1) by a Flip-Flop.

In this case, since the STAY signal is made for the input of the UP/DOWN Counter, the pulse width of

the L-SIDE_IN is fixed by the DUTY_CONT<7:0> signals.

The ST-ZCD senses VX node continuously with DELAY_1 and DELAY_2 signals also after lock

state. So, if (S1, S2) value is changed by the load condition or PVT variations, the ST-ZCD detects

when inductor current is 0 A with duty control of L-SIDE and UP/DOWN Counter like the way

mentioned before. As a result, the ST-ZCD keeps STAY state independently of environmental changes

with the zero current sensing through continuous sensing (S1, S2) signals.

Fig. 9 shows the state diagram of the Digital ST-ZCD. When the Digital ST-ZCD starts to operate,

the pulse width of the NMOS switch gate control signal is controlled by the UP/DN/STAY signals.

11

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The NMOS switch turns off and after a certain amount of delay, the inductor current is detected by

monitoring the VX using flip-flop. The Digital ST-ZCD determines whether to increase or decrease the

pulse width of the NMOS switch gate control signal through the detecting inductor current. When the

detected inductor current is 0 A, the NMOS switch does not have diode conduction. Therefore, the

Digital ST-ZCD generates the STAY signal, and the Digital ST-ZCD then operates in the locked state.

Start ST-ZCD

Control the
DUTY_CONT<7:0>
UP DN STAY

VX Node Monitoring UP STAY DN

using Flip-Flop Signal Signal Signal

Detect the Current (0,0) (1,1) (0,1)

(S1,S2)

Fig. 9. State diagram of Digital ST-ZCD.

Fig. 10 shows the timing diagram of the Digital ST-ZCD according to the state. In the case shown in

Figs. 10 (a) and 10 (b), due to the diode conduction, the efficiency of the DC-DC Converter is reduced.

In particular, in Fig. 10 (b), the reverse current decreases the output ripple characteristics as well as the

efficiency. As seen in Fig. 10 (a) and (b), the direction of the inductor current is in accordance with the

direction of the energizing current. Consequently, the diode conduction is positive (+) if it is through

NMOS and negative (-) if it is through PMOS. The VX voltage immediately drops to less than 0 V if

the NMOS switch is turned off when the NMOS diode conduction occurs. Alternatively, when the

PMOS diode conduction occurs, VX voltage increases to a voltage higher than the input voltage VIN.

When the digitally controllable pulse generator is thereby generating a suitable pulse width values in

Fig. 10 (c) waveform, the signals (S1, S2) is (0,1) by a Flip-Flop. If the value of (S1, S2) is (0, 1), the

signal is sent to the UP/DOWN Counter and the pulse width of the NMOS is fixed. When the switch

pulse width of the DC-DC Buck Converter reaches the steady state, the Digital ST-ZCD exports the

NMOS switch pulse with the “On” time pulse width at which the inductor current is constant at 0 A.

The DCM operation of the DC-DC Buck Converter can obtain maximum efficiency when the NMOS

switch is “Off” at the time at which the inductor current is 0 A as shown in Fig. 10 (c).

12

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IL
IL

H-SIDE
H-SIDE

L-SIDE
L-SIDE

DELAY_1
DELAY_1
DELAY_2
DELAY_2
VIN
(S1, S2)=(1, 1)
VX VIN

0V VX

(S1, S2)=(0, 0) 0V

(a) (b)

IL

H-SIDE

L-SIDE

DELAY_1

DELAY_2

VX

(S1, S2)=(0, 1)

(c)

Fig. 10. Timing diagram of the Digital ST-ZCD at (a) UP state (b) DN state (c) STAY.

D. Type-III Digital Compensator

In this paper, the Type-III Digital Compensator is proposed to reduce the current consumption and

area. By designing Type-III Compensator as all digital, low power and low area can be realized. Type-

III compensation is used to improve the transient response, and to boost the crossover frequency and

phase margin. It guarantees the targeted bandwidth and phase margin, as well as an unconditionally

stable control loop [15].

The Digital Compensator improves the accuracy of the output voltage through increase the dc gain of

the DC-DC Converter close-loop transfer function, and it ensures the stability by compensating the pole

location of the DC-DC Converter. It also compensates the pole/zero location by the output filter of the

DC-DC Converter

13

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In this paper, the Digital Compensator has the 2-bit input from the Adaptive Window ADC, and the

6-bit output to the Hybrid DPWM Core. As described in Section II, the characteristic of the output

voltage ripple is improved as the resolution of the Compensator increases. On the other hand, the area

and current of the DC-DC Converter is increased since the resolution of the DPWM and ADC increases.

The Type-III Digital Compensator is implemented using the 6-bit resolution to realize the small area

and low current consumption in this paper, and the DPWM DC-DC Converter with an enhanced

characteristic of the output voltage and high stability is designed using the Adaptive Window ADC.

In the proposed Type-III Digital Compensator approach, the analog compensator is designed with

the required phase margin and crossover frequency in the s-domain. Once the design is verified, it is

ready for its conversion to the digital domain (z-domain) for which Tustin’s method is used. The type-

III analog compensator s-domain transfer function for a gain of 13 dB and a phase margin of 55° is

given as shown in Eq. (4):

6.30707e-10s2 +5.02277e-5s+1
H s  = (4)
3.51537e-16s3 +5.0498e-11s 2 +1.8135e-6s

The generalized form of the digital compensator z-transfer function is given as shown in Eq. (5):

b0 z N +b1z N-1 +Lb N

H(z)= (5)
a 0 z N +a1z N-1 +La N

where N is the order of the system, b0…bN is the coefficients of the numerator, and a0…aN is the

coefficients of the denominator. The obtained 3rd-order discrete-transfer function is given as shown in

Eq. (6):

0.441z-3 -0.441z-2 -0.424z-1 +0.441

H(z)= (6)
-0.930z-3 -2.860z-2 -2.929z-1 +1

Bilinear transformation [16]-[17] and Tustin’s method [18] are used to convert the transfer function

from the s domain to the z domain. Tustin’s method and the pole-zero match are very useful methods.

The controller is initially designed in the s-domain and fulfills the criteria for stability, i.e., all of the

poles are on the left half of the s-plan. The poles on the z-plan are inside the unit circle to ensure

stability, as shown in Figs. 11 (a) and (b). The location of the three poles P1, P2, and P3 are as follows:

P1 [1 + 0i], [0.9647 + 0.0011i] and [0.9647 - 0.0011i]. The phase margin in the z-domain is 92°. The

14

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magnitude and phase are shown in Fig. 11 (a), and the pole-zero location is shown in Fig. 11 (b). Since

the Type-III Digital Compensator is designed considering the inductor of 3 µH, capacitor of 3 µF used

as the output filter under the input voltage range of 1.5 ~ 3 V and load current conditions of 1 ~ 10 mA,

it can be confirmed that the loop phase margin of the DPWM DC-DC Converter is 92° and sufficiency

stability are ensured as shown in Fig. 11 (b). In addition, the pole/zero locations of the z-domain which

must be considered in the Digital Compensator are all within the stability as shown in Fig. 11 (b).

Gm = -76.7 dB (at 0 rad/s)

Pm = 92 deg (at 8.42e+07 rad/s)

(a)

(b)

Fig. 11. (a) Magnitude and phase of the digital controller, and (b) pole-zero locations on z-plan (1 + 0i, 0.9647 + 0.0011i, 0.9647
- 0.0011i).

15

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IV. EXPERIMENTAL RESULTS

Fig. 12 shows the chip microphotograph. The chip is fabricated using a 55 nm CMOS process with a

single poly layer, four layers of metal, metal-insulator-metal (MIM) capacitors, and high sheet

resistance poly resistors. The die area of the DPWM DC-DC Buck Converter is 500 µm x 300 µm.

300 µm

Adaptive Power
Digital
Window MOSFET
ST-ZCD
ADC

500 µm
DLL

Start-Up Type-III
Oscillator + Digital
Clock Hybrid
Compensator
Generator DPWM Core

Fig. 12. Chip microphotograph of the DPWM DC-DC Buck Converter.

Fig. 13 shows the simulation results of the DPWM DC-DC Buck Converter. In the start-up sequence

with open-loop, the initial voltage is generated. The DPWM DC-DC Buck Converter is then switched

to close-loop, and is operated in the DPWM mode. The output voltage (VOUT) of the DPWM DC-DC

Buck Converter operation is in accordance with that of regulation output voltage of 1.2V. The output

ripple voltage is approximately 20 mV. The load current condition is 10 mA. The switching frequency

of the DPWM DC-DC Buck Converter is 2 MHz.

L1 Switching Frequency = 2MHz

Current

VOUT VOUT (1.18V ~ 1.21V) Regulation

Start-Up

VCLOCK

A0

B0

Duty_Out

BGR Output Voltage

VBGR
(460 mV)
dsfsdf

Fig. 13. Top simulation results of the DC-DC Buck Converter.

16

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Fig. 14 shows the simulation results in the DCM region when the load current is 10 mA. The UP,

DN, and STAY signals are generated repeatedly by sensing the instant when VX is zero by Digital ST-

ZCD.

UP/DN/STAY UP STAY
STAY
VX
VX

DCM Mode
L1
Current

L-SIDE

ILOAD 10 mA

1.2 V
VOUT

Fig. 14. Digital ST-ZCD simulation results of DC-DC Buck Converter.

The information reflects the output of the Low Side Driver, the L-SIDE signal, which is one of the

critical signals for the DCM region. As Digital ST-ZCD converges to the steady state, the STAY signal

continues to minimize the high side and low side conduction losses due to the voltage at VX node. The

output voltage of the DPWM DC-DC Buck Converter, VOUT, settles to 1.2 V.

The measurement environment of the DPWM DC-DC Buck Converter is illustrated in Fig. 15. The

test board is composed of a test port for the IC measurement. In the test board, the DPWM operation

and regulation characteristics are measured through the output voltage of the DPWM DC-DC Buck

Converter and the inductor VX voltage by applying an external power supply of 1.5 ~ 3 V.

Power supply
(1.5 V ~ 3.0V)

Fabricated
IC

VX L1 (3 μH) VOUT

Fig. 15. Measurement environment of the DPWM DC-DC Buck Converter.

17

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Fig. 16 (a) shows the measured waveform of the DPWM DC-DC Buck Converter, illustrating the

internal VX node and output voltage (VOUT) at the switching frequency of 2 MHz. Fig. 16 (b) shows the

magnified waveform, illustrating the operation of Digital ST-ZCD in more detail. It shows the Digital

ST-ZCD in the normal DPWM, which detects the point at which the inductor current is zero and turns

off the NMOS. Therefore, it can prevent the reverse current and the NMOS is turned off without the

diode conduction of NMOS and PMOS as shown in Fig. 16 (b).

Figs. 17 (a) – 17 (c) show the operation of Digital ST-ZCD. In Figs. 17 (a) and 17 (b), High side

diode conduction loss and Low side diode conduction loss occur since the Digital ST-ZCD is turned off

earlier and later than the optimum timing, respectively. Fig. 17 (c) shows the normal operation of

Digital ST-ZCD, where no High side and Low side diode conduction losses occur at the Stay state after

repeating the Up and Down states.

0.5us Switching Frequency = 2 MHz

VX

VOUT = 1.2 V

(a)
DCM Operation using
VX Digital ST-ZCD
PMOS On
ALL OFF

NMOS On

VOUT = 1.2 V

(b)
Fig. 16. Measured waveform of the DPWM DC-DC Buck Converter at (a) DPWM operation using Digital ST-ZCD and (b) zoom
measurement result.

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(a)

(b)

(c)
Fig. 17. Measured waveform of ST_ZCD (a) UP state (b) Down state and (c) Stay state.

Table I presents the analysis of the power losses of the DPWM DC-DC Buck Converter. Load

current is 10 mA and supply voltage is 1.5 V ~ 3.0 V for simulation and measurement conditions.

Hybrid DPWM Core, Type-III Digital Compensator, Adaptive Window ADC, Digital ST-ZCD, Clock

Generator, and Gate Driver blocks are checked with simulation results. The total current consumption

is 130 µA in simulation and measurement. The power loss in circuits with respect to the supply voltage

is 1.47 % ~ 2.72 %.

TABLE I
ANALYSIS OF THE POWER LOSSES OF THE DPWM DC-DC BUCK CONVERTER.
Power losses (%)

Supply Power 1.5 V 2.0 V 2.5 V 3.0 V

Hybrid DPWM Core 0.17 0.22 0.27 0.31
Type-III Digital Compensator 0.11 0.14 0.18 0.21
Adaptive Window ADC 0.17 0.22 0.27 0.31
Digital ST_ZCD 0.11 0.14 0.18 0.21
Clock Generator 0.57 0.73 0.90 1.05
Gate Driver 0.34 0.44 0.54 0.63
Total circuit consumption 1.47 1.89 2.34 2.72
Measured Conduction losses 4.38 7.03 8.06 9.38
Measured Switching losses 2.65 2.78 3.00 3.40
Measured Efficiency (%) 91.5 88.3 86.6 84.5

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Fig. 18 (a) shows the measured efficiency of the proposed DPWM DC-DC Buck Converter with

respect to load current when the input voltage of the DPWM DC-DC Buck Converter is 3 V. The peak

efficiency is 84.5 % when the load current is 10 mA. Fig. 18 (b) shows the measured efficiency of the

proposed DPWM DC-DC Buck Converter with respect to the input voltage when the load current is 10

mA. The peak efficiency is 91.5% when the input voltage is 1.5 V.

(a) (b)

Fig. 18. Measured efficiency of DC-DC Buck Converter with respect to (a) load current and (b) input voltage.

Table II shows the performance comparison of the DPWM DC-DC Buck Converter with prior works.

The proposed DC-DC Buck Converter has the best overall efficiency under 10 mA load current

condition. Also, the capacitor value and die area are smaller than those of [5], [21], [22], and [23].

TABLE II
PERFORMANCE COMPARISON OF THE DPWM DC-DC BUCK CONVERTER WITH PRIOR WORKS
[5] [21] [22] [23]
Reference This Work
ISSCC 07 JSSC 11 ISSCC 10 JSSC 11
0.18 μm 45 nm 40 nm 0.13 μm 55 nm
Technology
CMOS CMOS CMOS CMOS CMOS
Operating
DPWM PWM DPWM PWM DPWM
Mode
Peak
93.2 87.4 90 90 91.5
Efficiency (%)

5 2 3.125 7 kHz ~ 2
Operation Frequency
MHz MHz MHz 5 MHz MHz

Input Voltage Range

2.9 ~ 3.3 2.8 ~ 4.2 0 ~ 3.3 1.8 1.5 ~ 3
(V)
Load Current 10 m ~ 20 μ ~ 700 n ~ 1m~
-
(A) 450 m 100 m 107 μ 10 m
Output Voltage
1.0 ~ 1.7 0.4 ~ 1.2 0.1 ~ 3.3 0.575 ~ 1 1.2
(V)
Die Area
0.6 2.25 0.7 - 0.15
(mm2)
Inductor / 1 μH / 10 μH / 2.2 μH / 3 μH /
-
Capacitor 10 μF 2 μF 10 μF 3μF

20

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V. CONCLUSION

A high efficiency DPWM DC-DC Buck Converter and low power Digital ST-ZCD is proposed for

IoT and ultra-low power applications. The Hybrid DPWM Core with high linearity and low power

consumption is proposed to implement the high efficiency DPWM DC-DC Converter. It is composed

of a two-step delay control using the Counter and Delay Line, where the MSB of the DPWM duty

value is determined by the counter based method which has high linearity and he LSB of the DPWM

duty value is determined by the Delay Line method which has low power consumption. An Adaptive

Window ADC is proposed to reduce the output voltage ripple within 20 mV. A dead time generator is

implemented with the proposed ST-ZCD to minimize the reverse current. The ST-ZCD can improve

efficiency by reducing the control loss that accounts for a large proportion of the DC-DC Converter in

the light load current conditions. Also, all digital Type-III Compensator is implemented for the low

power and small die area.

This chip is fabricated with a 55 nm CMOS process, which uses the standard supply voltage of 1.5 ~

3 V to generate the output voltage of 1.2 V. The total active area is 500 µm x 300 µm. The measured

peak efficiency of the DPWM DC-DC Buck Converter is 91.5 % with a quiescent current consuming

only 130 µA.

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22

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23

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Sang-Yun Kim received his B.S. degree from the Department of Electronic

Engineering at Konkuk University, Seoul, Korea, in 2013, where he is currently

working toward the combined Ph.D. & M.S. Course in School of Information and

Communication Engineering, Sungkyunkwan University. His research interests

include high-speed interface IC and CMOS RF transceiver.

Young-Jun Park received the B.S degree in electronics engineering from Kumoh

National Institute of Technology, Gumi in 2013. Since then he has been working toward

the M.S. degree in electronics and computer engineering from Sungkyunkwan

University, Suwon, Korea. His research mainly focuses on the design of power

management integrated circuits for high efficiency and Wireless Power Transfer system.

Imran Ali received his B.S. and M.S. degrees in Electrical Engineering from

University of Engineering and Technology, Taxila, Pakistan, in 2008 and 2014,

respectively. From 2008 to 2015, he was with Horizon Tech. Services, Islamabad,

Pakistan, where he was a Senior Engineer of the Product Development Division and

worked on the design and development of hardware based crypto/non-crypto systems. He is currently

working toward Ph.D. degree in College of Information and Communication Engineering at

Sungkyunkwan University, Suwon, South Korea. His research interests include CMOS digital

controller, PLL, ADPLL, wireless power system and analog/digital mixed signal integrated circuits.

Truong Thi Kim Nga received B.S degree from Department of Electronics and

Telecommunication at Danang University of Technology, Danang- Vietnam and

M.S degree in School of Information and Communication Engineering,

Sungkyunkwan University, Suwon, Korea. She is currently working toward the

Ph.D degree at School of Information and Communication Engineering,

Sungkyunkwan University, Suwon, Korea. Her research interests include wireless power transfer

system and Power IC design.

24

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Transactions on Power Electronics

Hocheol Ryu received his B.S. degree from the Department of Electronic

Engineering at Sungkyunkwan University, Suwon, Korea, in 2015, where he is

currently working toward the Combined Ph.D. & M.S degree in School of

Information and Communication Engineering. His research interests include

CMOS RF transceiver, Phase Locked Loop.

Zaffar Hayat Nawaz Khan received his B.S. degree from the Department of

Electronic Engineering at Balochistan University of Information Technology,

Engineering and Management Sciences BUITEMS Pakistan. He is currently

working toward the Combined M.S & Ph.D. degree in School of Information and

Communication Engineering at Sungkyunkwan University, Suwon, South Korea.

His research interests include Power Management in I.C especially in DC-DC converter.

Seong-Mun Park received his B.S. degree from the Department of Electronic

Engineering at Sungkyunkwan University, Suwon, Korea, in 2016, where he is

currently working toward the M.S degree in School of Information and

Communication Engineering, Sungkyunkwan University. His research interests

include Power Management IC and CMOS RF transceiver.

YoungGun Pu received his B.S., M.S. and Ph.D. degrees from the Department of

Electronic Engineering at Konkuk University, Seoul, Korea, in 2006, 2008 and

2012, respectively. His research interest is focused on CMOS fully integrated

frequency synthesizers and oscillators and on transceivers for low-power mobile

communication.

Minjae Lee received his B.Sc. and M.S. degrees both in electrical engineering from

Seoul National University, Seoul, Korea in 1998 and 2000 respectively. He received the

Ph.D. degree in electrical engineering from the University of California, Los Angeles,

in 2008. In 2000, he was a consultant with GCT semiconductor, Inc., and Silicon Image

Inc., designing analog circuits for wireless communication and digital signal processing blocks for Gigabit

25

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2688387, IEEE
Transactions on Power Electronics

Ethernet. He joined Silicon Image Inc., Sunnyvale, CA in 2001, developing Serial ATA products. In August

2008, he joined Agilent Technologies in Santa Clara, CA, where he was involved with the development of

next generation high-speed ADCs and DACs. Since 2012, he has been with the School of Information and

Communications, Gwangju Institute of Science and Technology, Gwangju, Korea, where he is now an

Assistant Professor. He was the recipient of the 2007 Best Student Paper Award at the VLSI Circuits

Symposium in Kyoto, Japan and He received the GIST Distinguished Lecture Award in 2015.

Keum Cheol Hwang received his B.S. degree in electronics engineering from

Pusan National University, Busan, South Korea in 2001 and M.S. and Ph.D.

degrees in electrical and electronic engineering from Korea Advanced Institute of

Science and Technology (KAIST), Daejeon, South Korea in 2003 and 2006,

respectively. From 2006 to 2008, he was a Senior Research Engineer at the

Samsung Thales, Yongin, South Korea, where he was involved with the development of various

antennas including multiband fractal antennas for communication systems and Cassegrain reflector

antenna and slotted waveguide arrays for tracking radars. He was an Associate Professor in the

Division of Electronics and Electrical Engineering, Dongguk University, Seoul, South Korea from

2008 to 2014. In 2015, he joined the Department of Electronic and Electrical Engineering,

Sungkyunkwan University, Suwon, South Korea, where he is now an Associate Professor. His research

interests include advanced electromagnetic scattering and radiation theory and applications, design of

multi-band/broadband antennas and radar antennas, and optimization algorithms for electromagnetic

applications. Prof. Hwang is a life-member of KIEES, a senior member of IEEE and a member of

IEICE.

Youngoo Yang (S'99-M'02) was born in Hamyang, Korea, in 1969. He received

the Ph.D. degree in electrical and electronic engineering from the Pohang

University of Science and Technology(Postech), Pohang, Korea, in 2002. From

2002 to 2005, he was with Skyworks Solutions Inc., Newbury Park, CA, where he

designed power amplifiers for various cellular handsets. Since March 2005, he has

been with the School of Information and Communication Engineering, Sungkyunkwan University,

Suwon, Korea, where he is currently an associate professor. His research interests include power

26

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2688387, IEEE
Transactions on Power Electronics

amplifier design, RF transmitters, RFIC design, integrated circuit design for RFID/USN systems, and

modeling of high power amplifiers or devices.

Kang-Yoon Lee received the B.S., M.S. and Ph.D. degrees in the School of

Electrical Engineering from Seoul National University, Seoul, Korea, in 1996, 1998,

and 2003, respectively. From 2003 to 2005, he was with GCT Semiconductor Inc.,

San Jose, CA, where he was a Manager of the Analog Division and worked on the

design of CMOS frequency synthesizer for CDMA/PCS/PDC and single-chip CMOS RF chip sets for

W-CDMA, WLAN, and PHS. From 2005 to 2011, he was with the Department of Electronics

Engineering, Konkuk University as an Associate Professor. Since 2012, he has been with College of

Information and Communication Engineering, Sungkyunkwan University, where he is currently an

Associate Professor. His research interests include implementation of power integrated circuits, CMOS

RF transceiver, analog integrated circuits, and analog/digital mixed-mode VLSI system design.

27

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2688387, IEEE
Transactions on Power Electronics

Author affiliations

Sang-Yun Kim : College of Information and Communication Engineering, Sungkyunkwan University,

Suwon 440-746, Korea

Young-Jun Park : College of Information and Communication Engineering, Sungkyunkwan

University, Suwon 440-746, Korea

Imran Ali : College of Information and Communication Engineering, Sungkyunkwan University,

Suwon 440-746, Korea

Truong Thi Kim Nga : College of Information and Communication Engineering, Sungkyunkwan

University, Suwon 440-746, Korea

Ho-Cheol Ryu : College of Information and Communication Engineering, Sungkyunkwan University,

Suwon 440-746, Korea

Zaffar Hayat Nawaz Khan : College of Information and Communication Engineering,

Sungkyunkwan University, Suwon 440-746, Korea

Seong-Mun Park : College of Information and Communication Engineering, Sungkyunkwan

University, Suwon 440-746, Korea

YoungGun Pu : College of Information and Communication Engineering, Sungkyunkwan University,

Suwon 440-746, Korea

Minjae Lee : School of Information and Communications, Gwangju Institute of Science and

Technology, Gwangju, 61005, Korea

Keum Cheol Hwang : College of Information and Communication Engineering, Sungkyunkwan

University, Suwon 440-746, Korea

Youngoo Yang : College of Information and Communication Engineering, Sungkyunkwan University,

Suwon 440-746, Korea

Kang-Yoon Lee : College of Information and Communication Engineering, Sungkyunkwan University,

Suwon 440-746, Korea

28

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.