1.
Feature size:
Feature size refers to the smallest dimension (such as the width of the gate) in a transistor or
integrated circuit. It is typically associated with the technology node (e.g., 7nm, 5nm) and
affects the performance, density, and power consumption of the device.
2. Monolithic Microwave Integrated Circuits (MMICs)
3. GaAs MESFET (MEtal Semiconductor Field Effect Transistor)
4. SPICE (Simulation Program with Integrated Circuit Emphasis)
5. wells or tubs: To accommodate both nMOS and pMOS devices, special regions are created in
which the semiconductor type is opposite to the substrate type.
6. n-well CMOS: nMOS transistor is created in the ptype substrate, and the pMOS transistor is
created in the n-well, which is built into the ptype substrate.
7. Twin-tub CMOS: additional tubs of the same type as the substrate are created.
8. The process used to transfer a pattern to a layer on the chip is called lithography.
9. Photoresist: A light-sensitive, acid-resistant organic polymer, initially insoluble in the
developing solution. If the photoresist material is exposed to ultraviolet (UV) light, the
exposed areas become soluble so that they are no longer resistant to etching solvents.
10.
POSITIVE PHOTORESIST NEGATIVE PHOTORESIST
INITIALLY insoluble Soluble
AFTER UV soluble insoluble
EXPOSURE
Sensitive to light lesser more
Photolithographic higher lesser
Resolution
Usage manufacturing of high- where higher thickness and
density integrated circuits durability are needed
Pattern Same as mask Inverted to the mask
Formation
11. E-Beam Lithography uses a focused electron beam to write patterns directly onto a
photosensitive resist layer on a substrate. The resist is sensitive to electron exposure, and the
pattern is developed chemically.
Resolution: Capable of achieving extremely high resolutions, down to sub-10 nanometers,
which is much finer than optical lithography.
12. Polysilicon is used both as gate electrode material for MOS transistors and also as an
interconnect medium in silicon.
Undoped polysilicon has relatively high resistivity. The-resistivity of polysilicon can be
reduced by doping it with impurity atoms.
13. self-aligned process: the polysilicon gate, which is patterned first, directly defines the precise
location of the channel region. Consequently, the source and drain regions are subsequently
doped and naturally align themselves with the gate. This alignment is achieved without
additional alignment steps, as the gate pattern itself ensures that the source and drain
regions are correctly positioned relative to the gate. Hence, the term "self-aligned" reflects
this inherent alignment achieved through the gate patterning process.
