Metal ECO implementation using Mask Programmable cells

Tilak Wadhwa, Gaurav Gupta (NXP Semiconductor, India)

Introduction-
In deep sub-micron node SOCs with multimillion gates, along with the increase in design
complexity, chances of functional ECOs (engineering change orders) is equally increasing. Metal ECOs
play a vital role in absorbing such last minute design changes before tapeout and hence help save
millions in terms of mask cost. They also help avoid all layer mask change in re-spins to fix IP bugs found
from Si Validation. Though design fix belongs to logical domain, physical aspects of implementation are
poorly understood. In this article, we will focus on metal ECO implementation methodologies with
emphasis on mask programmable cells.

Traditional Approach-
Generally, metal ECOs are implemented using spare cells which are inserted during synthesis or
P&R in the form of ‘spare modules’. A spare module definition mostly includes a wide variety of
combinational & sequential cells. For Example - a minimum set will involve multiple instances & various
drives of BUF, INV, NOR, NAND, MUX, FF & Latch cells. These spare modules are then sprinkled across
the chip/block during P&R (refer pic 1 below). The input pins of functional cells in a spare module are
generally tied using TIEHI/LO cells so that they don’t remain floating as these cells are going to be
unused till they get used for an ECO.

Pic 1 – spare modules distribution in a block

There are some inherent problems in this approach due to its probabilistic nature -

1. It is not possible to include all library cell types in a spare module which causes problems
later in case an ECO demands a higher number of a particular cell type.
2. Limited drive strength of existing cells in a spare module leads to DRV Issues.

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Mask Programmable ECO methodology-
This methodology addresses the problems of traditional approach to a large extent. Though it
has been there in industry for a while now and most EDA tools & library vendors support the usage,
there is lesser awareness in wider designer community.

Understanding the ECO library-

Most library vendors include ECO Kits as part of their library offering (subject to IP licensing).
These kits generally include 2 type of cells –

1. ECO filler cells-

a. These cells are generally designed with various width multiples – say 4x, 8x, 16x,
48x. Note that these are not the cell drives, but width multiples.
b. ECO Filler cells have multiple parallel poly structures running over active. But they
don’t have any contact connections to poly/active. (refer ECO_filler pic – 2a)
c. Another variant can be ECO decap cells which have same FEOL layout as
corresponding ECO filler cell, but in addition, they have decap realized by
connecting source/drain to VDD/VSS.

Pic 2a – ECO_filler Pic 2b – ECO_func

2. ECO functional cells-

a. These include wide variety of combinational & seq elements with multiple drive
strengths realized using width multiples used for filler cells.
b. The cell layout has same FEOL footprint as that of ECO fill. E.g. smallest func gate,
ECO_func (ref pic 2b above) will use ECO_filler FEOL layout and have contact
connections to poly/active to realize a functional gate. Similarly multiple drive
strengths can be realized by using wider layout which has width-multiples same as
that of filler cells described in #1a above.

Note the difference of only contact layers in Pics 2a & 2b.

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ECO implementation flow-

•Sprinkle the ECO filler/decap cells across chip/block in pre-decided percentage after
placement
•Alternatively all available whitespace cen be filled with ECO filler/decap cells in a pre-
P&R decided row pattern say - F:F:D

•During logical ECO impementtaion, use the standard cells from ECO library set and
insert as new functional cells.
Design fix

•During physical implementation, identify the ECO filler/decap cells to be swapped

•Simply swap the filler/decap cells with new functional cells with keeping in mind the
width factor (e.g. _8 func cell can be swapped only with a _8 filler or 2 x _4 filler cells)
ECO •Use traditional flow to implement routing etc.

Note that decap benefit will be lost if swap is made using ECO decap cell.

Comparative analysis-
Let’s first look at the leakage comparison. Table-1 below presents the data on a block in 28nm.
Evidently, leakage numbers remain unchanged with ECO filler while spare cells add to leakage power.

Without With Spares With Spares

With ECO filler
spares (inputs tied low) (inputs tied high)
Internal_Power 7.2 7.2 7.2 7.2

Switching_Power 9.3 9.3 9.3 9.3

Leakage_Power 1248.01 1250.5 1250.27 1248.01

Table – 1 (Leakage comparison on a block with ~1K functional spare cells)

Above numbers are for a small block with ~0.47M flops. On a full chip design with ~2.9M flops (and
44.5K spare cells), leakage benefit seen is ~110 mw.

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Summarized below are all advantages of this methodology over traditional approach-

Pros –

1. Increased feasibility of ECO implementation as any required functional cell can be derived
through single filler cell.
2. As FEOL masks remain the same, huge cost saving through the reuse of a large number of
existing masks (compared to an all layer change).
3. No additional leakage penalty compared to traditional spare cells approach which adds to design
leakage.

Cons –

1. Compared to traditional approach (spare cells), there may be an additional mask cost involved
for contact layer.

Conclusion-
Mask programmable cells methodology has clear advantages over traditional spare cell
approach not only in terms of ease and increased probability of a metal ECO implementation but also in
leakage power savings. Though, there can be ECO situations where it is probable that spare cells are
available and are sufficient for the fix, hence additional mask cost of contact layer can be saved.
However, in situations which warrant an all layer change due to non-availability of required spare cells in
a certain chip area, pre-filler programmable fillers can surely save FEOL layers change.

About the authors-

Tilak Wadhwa is currently working as Staff Design Engineer at NXP Semiconductor, India. He has
more than 10 years of experience in Chip Level Implementation of Microcontrollers and Block Level
Implementation for Complex ASICs with emphasis on P&R, LVS, DRC and DFM. He has also worked
previously on RTL2GDSII of High speed DDR/DDLL interfaces and Core Cell Library development &
characterization. He can be reached at – tilak.wadhwa@nxp.com

Gaurav Gupta is working as STAFF Design Engineer at NXP Semiconductor, India. He has over
ten years of industry experience in various fields of VLSI and is currently working in physical design
team. He has experience in logical and Physical Synthesis, STA, Static Low Power Verification, Formal
Verification and has also worked in Standard Cells library characterization and validation domain. His
mail ID is g.gupta@nxp.com