11.

1 Sources of Power Dissipation

201

A1.1.1 Dynamic Power Dissipation

This refers to the power consumed by a circuit/system due to some activities within it.
For a
static CMOS realization, at steady-state, either the pull-up
(p) or the
pull-down (n) network
is OFF. Thus, when there are no activities in the
system, power consumption
is expected to
be very low. During circuit activities, the power consumed depend upon the
mechanisms.
following two
1. Short-circuit power: If there is finite rise and fall time at the input of a CMOS gate,
a
both p- and n-networks are ON simultaneously, shorting the power supply line to the
ground. If VpD is the supply voltage and Imean is the average current drawn during the
input transition, then the short-circuit power is given by,
Fshortcircuit mean X VDD

For properly sized and ratioed gates, the contribution to the overall dynamic power due
to Pshortcircuit is of the order of 10-20%.
2.
Switching power This is the power consumed due to charging and discharging
dissipation:
of capacitive loads when the circuit has some activities due to change in inputs. The
capacitive load at different circuit gates depends upon the fanout of the gate, output
capacitance, and wiring capacitances. It may be noted that a node with load capacitance
might not switeh when the clock is switching. To take care of this, a quantity called
switching activity (a) is often used. It determines how often switching occurs on a node
with load capacitance. If VoD is the supply voltage, Vawing is the change in voltage level
of the switched capacitance, C is the capacitance being switched and f is the frequency
of operation, the switching power is given by,
Pswitching=C X VDD x Vswing X a x f

Since in most of the cases, Vswing = VDD,

Pawitching =Cx VßD xaxf

11.1.2 Static Power Dissipationa

This is the power consumed when the circuit is not in active mode of operation. In such a
situation, there is still some power dissipation due to various leakage mechanisms. The sit-
uation is aggravated with the scaling of supply voltages. As the supply voltage is reduced.
to keep the delay of a gate unchanged, the transistors need to be turned ON early by reduc
ing their threshold voltages. This, in turn, increases the leakage current in the subthreshold
range of operation of the circuit. Due to the exponential nature of leakage current in the
subthreshold regime of the transistor, it can no longer be ignored. The International Tech-
nology Roadnap for Semiconductors (ITRS) has projected an exponential increase in leakage
power with minimization of devices. Also, leakage increases with temperature. Thus, the
increased heat dissipation resulting from increase in leakage power consumption has a positive
Teedback on leakage. There are three major leakage mechanisms subthreshold leakage, gate
direct tunneling and junction band-to-band tunneling. This has been shown in Fig. 11.1.

Subthreshold leakage: When gate voltage is below threshold voltage but very eloSe to
It is caused by
,Subthreshold conduction current flows between source and drain.
202 Low Power Embedded System Design

the diffhusion of minority carriers. It depends exponentially on the threshold voltage of

the transistor. In nano-scaled devices, short channel effect (SCE) reduces the threshold
voltage, thereby increasing the subthreshold current.
.Gate direet tunneling leakage: Due to ultra-thin gate oxide, a high electric field can cause
electrons to tunnel through the gate-oxide. This results in large gate leakage in nano-
reduction in oxide thickness
scale transistors. An increase in the supply
voltage and/or
results in an exponential increase in gate tunneling current.
Junction band-to-band tunneling leakage: Application of reverse bias across the highly
doped p-n junction results in tunneling of electrons from valence band of p-side to the
conduction band of n-side. This is called band-to-band tunneling. In nano-scale devices,
due to the use of high junction doping, large junction BTBT occurs at OFF state with
the drain at Vpp and substrate at ground. The junction BTBT increases exponentially
with an increase in junction doping and supply voltage.

Gate leakage Subthreshold

leakage
Gate
Source Drain

Reverse biased
Junction BTBT

Bulk
Fig. 11.1 Leakage components in a transistor.

11.2 Power Reduction Techniques

Power reduction can be
attempted at all levels of design hierarchy-algorithm, architecture,
logic, and device levels. In the following sub-sections
we give an overview of each of
(except the device level on which the embedded these
system designer often does not have any
control). Higher the level at which power minimization is
power saving addressed, higher is the expected

11.2.1
Algorithmic Power Minimization
lt mainly focuses on reducing the number of
plementation. For example, in operations requiring larger power in a target
iun
many processors, the cost of an
may be different from
hrst
a
logical addition/subtraction operatlo
operation. Thus, to check "whether x is equal to y", one
pertorm subtraction operation followed by
a
ay
the other
hand, if the logical operation takes checking the status register for
zero-bit.
uSing a comparison lesser power, 2 may be directly compared
instruction. The following are some of the wit
for selecting a important issues to be juageu
particular algorithm from alternatives:
1. Memory
reference: This is very important as
memory is normally off-chip from the
processor. A large number of accesses to the
memory mean good amount of actlvILy
11.2 Power Reduction Techniques
203

the address/data
bus lines. The memory access
pattern is also important. If the access
Dattern sequential, only the least significant bits of address bus
is
change, whereas for
random access through the memory, most of the address bits will switch, thus creating
higher power dissipation.
2. Presence of cache memory: The presence and structure of cache
memory plays an im-
portant role. Cache can be fruitfully utilized to reduce both execution time and power
of an implementation if the
underlying algorithm has got locality in its behaviour. The
locality may be both temporal and spatial in nature. While a
to the fact that a temporal locality refers
memory location accessed at some time is also
in near future, spatial locality means if a likely to be accessed
memory location is accessed at some time, its
neighbouring locations are also likely to be accessed in near future. Thus,
inside the CPU cache saves not only the caching them
memory access time, but also the bus energy
consumption is reduced.
3. Recomputation vs. memory load/store: Normal power minimization techniques at
rithm level attempt to reduce the number of arithmetic algo-
operations. However, it may so
happen that to reduce the number of operations, some repeatedly
tion is done only once and stored at a performed computa-
memory location. Later, as and when necessary
it is reloaded from the
memory. This may lead to increased power consumption due to
extra memory accesses. If the
operands are already available in CPU registers or on-chip
cache, it may be better to recompute the value, instead of loading it from
memory, fromn
power consumption point of view.
4. Compiler optimization technique: The typical techniques used by an optimizing
can be used to reduce power compiler
consumption of a piece of code. The strategies involve
strength reduction, common suberpression elimination, minimizing memory
Loop unrolling is also often beneficial as it reduces loop overhead. traffic etc.
5. Number representation: This is another area for
algorithmic power trade-off. The fol-
lowing points may be noted:
Fited vs.
floating point representation: Fixed point operations are much sinmpler
than floating point Thus, it
ones.
normally leads to power saving, though accuracy
may suffer.
Sign-nagnitude vs. 2's co0mplement: Selection of
sign-magnitude representation may
have significant power saving over 2's
complement, if input samples are uncorrelated
and range is minimized.
Precision of operations: This is inmportant, since having lower
precision allows one
to reduce the size of space needed to store the values. A
typical example of this
is to reduce the number of bits in mantissa
portion in several signal processing
applications including speech and image to improve circuit delay and power.

11.2.2 Architectural Power Minimization

The architectural level transformations can be used to introduce power saving in a
There
desigu.
are two generic techniques to save power at the cost ot extra area, keeping the
formance of the system unaltered. These are parallelism and piypelining. To understand their
per
mpact, suppose we have to design a system with supply voltage V and operating frequeney
f. Figure 11.2(a) shows such a system at a black-box level. The system is
expected to operate
204 Low Power Embedded System Design
-

on a sequence of input data arriving at a rate of f. Now, if we duplicate to have n such

similar modules and the input data is processed by the modules in an interleaved fashion, the
blocks may operate at a lower speed -ideally, at a rate of f/n. Since the system is capable
of running at frequency f and the speed of a system is proportional to the supply voltage.
we reduce the supply from V to V/n. This will effectively reduce the power consumed by
the individual blocks by a factor of n (as power consumption is proportional to the square

of supply voltage). Since all such systems are operating simultaneously, total power saving is

1/n of the original power. This has been shown in Fig. 11.2(b). A problem with the scheme
is that the hardware is duplicated with other necessary multiplexing and demultiplexing logic.
In this the schene,
Another possible architectural modification often suggested is pipelining.
functional block of Fig. 11.2(a) is divided into a sequence of sub-blocks, each of approximately

same delay. Thus, if the number of sub-blocks be n, from pipelining principle, the overall
system can produce output at a rate of about nx f. Now, if the supply voltage of individual
stages is reduced bya factor of n, power reduces by a factor of 1/n. However, we need to
accommodate extra latches between the stages for proper synchronization between them. This
introduces some overhead in terms of area, performance and power as well. The scherne has
been shown in Fig. 11.2(c).
Input
Vin
Sub-biock 0

Input
Latch

Vin
Sub-biock 1
V/n| V/n V/n
Latch
Supply
voltage
Input Copy 0 Copy 1 Copy (n-1)

Latch
Original
block Vin
Mod-n
Counter Sub-biock (n-1)

Output Output Output

(a) Original block (b) Parallelizing (c) Pipelining

Fig. 11.2 Architect ural transformations for low power.

11.2.3 Logic and Circuit Level Power Minimization

tive
power reduction approaches at logic and circuit level mostly target to reduce the enec can
Capacitance. The following are sone of the directions in which this minimizatl01
C out:
be tried
11.2 Power Reduction Techniques
205

1, Static dynamic logic families: CMOS logic can be realized as static or dynamic
vs.

CMOS. Depending upon the signal transition probabilities, one of the

have an edge over the other. For example, for a
design styles may
two-input NAND gate with uniform
probability distribution for the inputs, the probability that the output is zero is 0.25,
whereas, the probability of output being one is 0.75. Thus, the
probability of a
consuming 0 1 transition is 0.25 x 0.75 0.1875. On the other hand, for a power
=

circuit, output is always precharged to 1. Thus, power will be consumed whenever dynamic
output is zero. Hence, the probability of a power consuming transition is
0.25, which is
higher than a static gate. However, dynamic gate has lower input
by a factor of 2 to 3) compared to static gate, as the capacitance (almost
p-network
effective capacitance that a dynamic gate sees is much lower.
is absent. Hence, the

in distributing the
But, the power consumed
precharging signal also needs to be considered.
2. Glitches and hazards: This is another
potential source of power consumption, particularly
in static CMOS circuits. A
glitch at the output of a gate can come due to the differences
in arrival times of input signals. A typical example of it is AND-OR-INVERT based
implementation the function f ab + ac. The circuit is shown in Fig. 11.3(a).
of =

Assume that b and c are always 1, while a is

making a transition from 1 to 0. Ideally,
output should remain fixed at 1, however due to the delay introduced by the inverter,
the output z will continue to be 0, when
y is also 0. This changes the
However, after that small delay of the inverter, z again becomes 1, thus making ff = 1.
output to 0.

Thus, y, instead of remaining fixed at 1, will show a transition 1 0 1, introducing

a glitch.
The glitch can be removed by adding a redundant AND gate for the term bc
and feeding the output to the OR gate, as shown in Fig.
11.3(b). It may be noted that
dynamic logic does not suffer from any glitch power consumption since all inputs must
be valid before the gate evaluates.

(a)
D-
(b)
Fig. 11.3 (a) Circuit with hazard, (b) Circuit without hazard.
3. Technology mapping: The logic synthesis library often contains different
of the implementations
same logic module. They normally differ in terms of area,
delay, power, ete. A logic
synthesis procedure targeted to power minimization may choose implementations that
require higher area or delay, but score better in terms of power. For example, consider
a
four-input AND function. Two possible implementations are shown in Fi8 1.a
and Fig. 11.4(b), respectively. The ON-probabilities of the gates are also shown. Total

I transition probability of the first implementation is 0.25 x 0.75 + 0.25 x U.73 t

6 5 XO.0625 =0.4336. For the second implementation, it is, 0.25 x0.75 +0.125 x 0.875
206 Low Power Embedded System Design

+0.9375 x 0.0625 = 0.3555. Thus. the first implementation consumes more power than
the second one. In this case, though there is no area penalty, the second implementation
has one gate delay more than the first one.

p 0.25
P=0.25

P 0.0625 = 0.125
p 0.5 p 0.5
P 0.0625
P 0.25

(a) (b)
Fig. 11.4 Two different implementations of 4-input AND

11.2.4 Control Logic Power Minimization

Power optimization of controller circuitry is very important. This is because while the datapath
of a design can be selectively turned OFF when not in use, controller is always active. A
controller is often specified and realized as a Finite State Machine (FSM). The synthesis of
FSM targeting low power can be addressed from various angles as discussed next.
1. Storage element design: Several flip-flop design have been reported in the literature with
various area-power trade-offs. Detailed discussion on this is beyond the scope of this
book.
2. State assignment: This is the assignment of binary codes to the FSM states to realize it.
For low power state encoding. first the steady-state probability for each of the states is
determined. Next, the transition probabilities between the states are caleulated. Codes
with lesserHamming distance are allocated to the states having higher transition prob
abilities between them. This minimizes the number of transitions in the next-state and
output combinational logic.
3. FSM partitioning: Often it is the case that the FSM states form clusters. Once the FSNM
is in some state belonging to a cluster, the probability of its remaining within the states
of this cluster for few transitions is
quite a
high. Probabilities of inter-cluster transitiots
are low. Thus, the FSM can be partitioned into two or more sub-FSMs. At any point or
ime, only onesub-FSM is active. We can do two things with the renmaining
The first
submachinieS
alternative is to stop clocks to them and make sure that their primary mput
hnes are masked-off. This is commonly known as clock gating. The scheme
has ee
P Fig. 1.5. Thus, there is no dynamie power cousumption in these sub-FSAls.
ne other alternative is to use power gating by introducing sleep trunsistors to urtt OFF
power suPply to them. Figure 11.6 shows introduct ion of sleep transistors. Power gatig
uuces leakage power as well, however, wake-up takes time. Thus, either the t it
PeTIOrmance suffers, or we have to turn ON probable active sub-FSAls early
O
Wastage of power than
as more one sub-FSAMs are active.
 Level Power Management
11.3 System
207

Primary input Combinational Primary output

logic

State
Enable register
Clock CilockClock
Fig. 11.5 Clock gating of FSM.

VOD

Circuit Sleep
transistor

Active-

Fig. 11.6 Power gating of FSM.

11.3 System Level Power Management

The techniques
discussed so far are good to the extent
that they deal with local siubsstetuis.
In an embedded system, consisting of various subsystems, it may be possible that all of theu
are not needed simultaneously to remain active. Thus, it necds a system level umanagenent
policy to turn OFF and turn ON the subsystems. A suitable power umanagement poliey is
needed for the following purposes:

going tu0 a low power state takes time. The longer the duration for which we walnt to
shutdown higher is the time taken duriug
a system, reactivatio
avoiding a power-down mode will cost unnecessary power.
frequent power-down mode will affect system pertormance
A naive approach may be to power-down a system whenever there s o eqest This
will definitely affect performance severely. A more sophisticated nethod is to 1 pred ttre
shutdow. In this approach, the goal is to predict the next arrival of service qnest anut wake
up the system just before that. Prediction can be made in severd dtferent ways us foellws.
208 Low Power Embedded System Design
gn
1. Ficed times: If the system does not receive any service request during an interval of
length TON, it shuts down for a fixed period of time TorF. Choice of Ton and Topr
behaviour.
may be made experimentally by studying system
2. Analysing system state: In this approach, there is a constant monitoring of the ser-
vice requests. The monitoring is done via a power manager that observes the system

components-the service provider, the service requestor

between them
and the queue
Based on the observations, the power manager sends power management commands to
11.7.
the service provider. The situation has been shown in Fig.

Power
Manager

Power
management
commands
Status Status Status

Service Service
Provider Requestor
Queue

Fig. 11.7 Power analysis strategy.

11.3.1 Advanced Configuration and Power Interface (ACPI)

ACPI is an open industry standard for power management services. It is designed to

be compatible with a wide variety of operating systems. Initially targeted at Personal
Computers, ACPI provides some basic power nanagement facilities and abstracts the
hardware layer. Host operating system will have its own power management moduie
that determines the policy. The operating system utilizes ACPI to send the required
controls to the ACPI compliant hardware and observe the hardware's state as input to
the power The concept has been shown in
manager. Fig. 11.8.

Applications
Kernel Power
ACPI driver management
AML interpreter
Device
drivers ACPI
ACPI tables
ACPI registers
ACPI BIOOs

Hardware platform

Fig. 11.8 ACPI interface.