MODEL NO.: V400H1 - L05: TFT LCD Approval Specification
MODEL NO.: V400H1 - L05: TFT LCD Approval Specification
com
Issued Date: Aug. 02, 2010
Model No.: V400H1 - L05
Approval
Approved by:
Note:
TVHD
Approved By
CC Chung
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- CONTENTS -
REVISION HISTORY ------------------------------------------------------- 3
9. PACKAGING ------------------------------------------------------- 27
9.1 PACKING SPECIFICATIONS
9.2 PACKING METHOD
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REVISION HISTORY
Page
Version Date Section Description
(New)
Ver 2.1 Aug. 02,’10 All All Approval Specification was first issued.
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V400H1- L05 is a 40” TFT Liquid Crystal Display module with 14-CCFL Backlight unit and 2ch-LVDS
interface. This module supports 1920 x 1080 FHD format and can display true 16.7M colors (8-bit colors).
1.2 FEATURES
- High brightness (500 nits)
- Ultra-high contrast ratio (4000:1)
- Faster response time (Gray to gray average 6.5ms)
- High color saturation NTSC 72%
- Ultra wide viewing angle : 176(H)/176(V) (CR>20) with Super MVA technology
- DE (Data Enable) only mode
- LVDS (Low Voltage Differential Signaling) interface
- Color reproduction (nature color)
- Optimized response time for both 50/60 Hz Frame rate
- Low color shift function
- RoHS compliance
1.3 APPLICATION
- TFT LCD TVs
- Multi-Media Display
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100
90
80
60
Operating Range
40
20
10 Storage Range
-40 -20 0 20 40 60 80
Temperature (ºC)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE Ta = 25 ± 2 ºC
Value
Parameter Symbol Unit Note
Min. Typ. Max.
Power Supply Voltage VCC 10.8 12.0 13.2 V (1)
Power Supply Ripple Voltage VRP - - 350 mV
Rush Current IRUSH - - 4.5 A (2)
White - 1.2 1.5 A
Power Supply Current Black ICC - 0.6 - A (3)
Vertical Stripe - 1.0 - A
LVDS Common Input Voltage VLVC 1.125 1.25 1.375 V
Interface Terminating Resistor RT - 100 - ohm
CMOS Input High Threshold Voltage VIH 2.7 - 3.3 V
interface Input Low Threshold Voltage VIL 0 - 0.7 V
Note (1) The module should be always operated within above ranges.
Note (2) Measurement Conditions:
+12v
+12V
0.9Vcc
0.1Vcc
GND
470us
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f v = 60
Hz, whereas a power dissipation check pattern below is displayed.
R G B R G B
B R G B R G B R
B R G B R G B R
R G B R G B
Active Area
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4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
SCAN DRIVER IC
FRAME BUFFER
INPUT CONNECTOR
LVDS_SEL
(1920x3x1080)
SDA
SCL TIMING
WP CONTROLLER
ORX0(+/-)
ORX1(+/-)
DC/DC CONVERTER & DATA DRIVER IC
ORX2(+/-)
ORX3(+/-)
REFERENCE VOLTAGE
OCLK(+/-)
CNF1
Vcc
FI-RE51S-HF-J,JAE
GND
BACKLIGHT
SOCKET UNIT
LIPS
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34 GND Ground
35 ERX3- Even pixel Negative LVDS differential data input. Channel 3
36 ERX3+ Even pixel Positive LVDS differential data input. Channel 3
37 N.C. No Connection
(1)
38 N.C. No Connection
39 GND Ground
40 SCL EEPROM Serial Clock (SCL) (3)
41 N.C. No Connection (1)
42 N.C. No Connection (1)
43 WP EEPROM Write Protection (WP) (1)
44 SDA EEPROM Serial Data (SDA) (1)
45 LVDS_SEL LVDS Data Format Selection (2)
46 N.C. No Connection
47 N.C. No Connection (1)
48 N.C. No Connection
49 N.C. No Connection
50 N.C. No Connection (1)
51 N.C. No Connection
Note (1) Reserved for internal use. Please leave it open.
Note (2) Low : JEIDA LVDS Format, High or Open : VESA Format.
Note (3) Low = Connect to GND, High = Connect to +3.3V
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ERx0+ 51Ө
100pF RxOUT
TxIN ERx0-
ER0-ER7 51Ө ER0-ER7
ERx1+ 51Ө
EG0-EG7 100pF EG0-EG7
ERx1-
51Ө EB0-EB7
EB0-EB7
ERx2+ 51Ө
DE 100pF DE
ERx2-
51Ө
ERx3+ 51Ө OR0-OR7
OR0-OR7
100pF
OG0-OG7 ERx3- OG0-OG7
51Ө
OB0-OB7 OB0-OB7
ECLK+ 51Ө
DCLK PLL ECLK-
100pF
PLL DCLK
51Ө
Host
Graphics Timing
Controller Controller
ORx0+ 51Ө
100pF
ORx0-
51Ө
ORx1+ 51Ө
100pF
ORx1-
ORx2+ 51Ө
100pF
ORx2-
51Ө
ORx3+ 51Ө
100pF
ORx3-
51Ө
OCLK+ 51Ө
100pF
PLL OCLK- PLL
51Ө
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Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is old pixel and the
second pixel is even pixel.
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R0 R2 51 TxIN0 27 Rx OUT0 R0 R2
R1 R3 52 TxIN1 29 Rx OUT1 R1 R3
R2 R4 54 TxIN2 TA OUT0+ Rx 0+ 30 Rx OUT2 R2 R4
R3 R5 55 TxIN3 32 Rx OUT3 R3 R5
R4 R6 56 TxIN4 33 Rx OUT4 R4 R6
R5 R7 3 TxIN6 TA OUT0- Rx 0- 35 Rx OUT6 R5 R7
G0 G2 4 TxIN7 37 Rx OUT7 G0 G2
G1 G3 6 TxIN8 38 Rx OUT8 G1 G3
G2 G4 7 TxIN9 39 Rx OUT9 G2 G4
G3 G5 11 TxIN12 TA OUT1+ Rx 1+ 43 Rx OUT12 G3 G5
G4 G6 12 TxIN13 45 Rx OUT13 G4 G6
G5 G7 14 TxIN14 46 Rx OUT14 G5 G7
B0 B2 15 TxIN15 TA OUT1- Rx 1- 47 Rx OUT15 B0 B2
B1 B3 19 TxIN18 51 Rx OUT18 B1 B3
B2 B4 20 TxIN19 53 Rx OUT19 B2 B4
24 B3 B5 22 TxIN20 54 Rx OUT20 B3 B5
bit B4 B6 23 TxIN21 TA OUT2+ Rx 2+ 55 Rx OUT21 B4 B6
B5 B7 24 TxIN22 1 Rx OUT22 B5 B7
DE DE 30 TxIN26 6 Rx OUT26 DE DE
R6 R0 50 TxIN27 TA OUT2- Rx 2- 7 Rx OUT27 R6 R0
R7 R1 2 TxIN5 34 Rx OUT5 R7 R1
G6 G0 8 TxIN10 41 Rx OUT10 G6 G0
G7 G1 10 TxIN11 42 Rx OUT11 G7 G1
B6 B0 16 TxIN16 TA OUT3+ Rx 3+ 49 Rx OUT16 B6 B0
B7 B1 18 TxIN17 50 Rx OUT17 B7 B1
RSVD 1 RSVD 1 25 TxIN23 2 Rx OUT23 NC NC
RSVD 2 RSVD 2 27 TxIN24 TA OUT3- Rx 3- 3 Rx OUT24 NC NC
RSVD 3 RSVD 3 28 TxIN25 5 Rx OUT25 NC NC
DCLK 31 TxCLK IN TxCLK RxCLK 26 RxCLK OUT DCLK
OUT+ IN+
TxCLK RxCLK
OUT- IN-
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Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Basic Blue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Colors Cyan 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Magenta 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Red(0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(1) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(2) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Red(253) 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red
Red(254) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red(255) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green(0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Green(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Green(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Green(253) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
Green
Green(254) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
Green(255) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Blue(0) / Dark 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Blue(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Blue(2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Gray
: : : : : : : : : : : : : : : : : : : : : : : : :
Scale
: : : : : : : : : : : : : : : : : : : : : : : : :
Of
Blue(253) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1
Blue
Blue(254) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0
Blue(255) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Note (1) 0: Low Level Voltage, 1: High Level Voltage
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency 1/Tc 60 74 80 MHZ (1)
LVDS Receiver Clock Input cycle to
Trcl - - 200 ps
cycle jitter
Setup Time Tlvsu 600 - - ps
LVDS Receiver Data
Hold Time Tlvhd 600 - - ps
Frame Rate Fr6 57 60 63 Hz
Total Tv 1115 1125 1135 Th Tv=Tvd+Tvb
Vertical Active Display Term
Display Tvd 1080 1080 1080 Th -
Blank Tvb 35 45 55 Th -
Total Th 1050 1100 1150 Tc Th=Thd+Thb
Horizontal Active Display Term Display Thd 960 960 960 Tc -
Blank Thb 90 140 190 Tc -
Note (1) LVDS Clock should not over 80MHz even if H-total or V-total is in spec, and the frequency follows
the equation below.
LVDS CLK= Frame rate * H-total * V-total
Tv
Tvd
Tvb
DE
Th
DCLK
Tc
Thd
Thb
DE
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Tc
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T 3T 5T 7T 9T 11T 13T
14 14 14 14 14 14 14
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0.1VCC 0.1Vcc
0V
0.5ЉT1Љ10ms T1 T3
0ЉT2Љ50ms
0ЉT3Љ50ms
500ms ЉT4 T2 T4
VALID
0V
Power On Power Off
0ЉT7ЉT2
0ЉT8
T7 T8
Option Signals
(SELLVDS)
T5 T6
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
o
Ambient Temperature Ta 25±2 C
Ambient Humidity Ha 50±10 %RH
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current(HV) IL 8.0 ± 0.3 mA
Oscillating Frequency
FW 48±3 KHz
(Balance Board)
Frame rate 60 Hz
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Normal
θx = θy = 0º
θy- θy+
6 o’clock
y- x+ θX+ = 90º
θy- = 90º
100%
90%
Optical
Response
10%
0%
Time
Gray to gray Gray to gray
switching time switching time
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The driving signal means the signal of gray level 0, 63, 127, 191, 255.
Gray to gray average time means the average switching time of gray level 0 ,63,127,191,255 to each
other .
(b)
YA = Luminance of measured location without gray level 255 pattern (cd/m2)
YB = Luminance of measured location with gray level 255 pattern (cd/m2)
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LCD Module
LCD Panel
Horizontal Line
D
D/4 D/2 3D/4
Vertical Line
W/4 1 2
3W/4 3 4
Active Area
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8. DEFINITION OF LABELS
8.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
CM40H15XXXXXLXXLYMDNNNN
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9. PACKAGING
9.1 PACKING SPECIFICATIONS
(1) 4 LCD TV modules / 1 Box
(2) Box dimensionsΚ1040(L) X 310 (W) X 640(H)
(3) WeightΚapproximately 43Kg ( 4 modules per box)
LCD TV Module
Anti-static Bag
Cushion(Top)
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(Pallet:L1250*W1050*H140mm)
Air Transportation
(Pallet:L1250*W1050*H140mm)
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10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) It is recommended to assemble or to install a module into the user’s system in clean working areas.
The dust and oil may cause electrical short or worsen the polarizer.
(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.
(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
(5) Do not plug in or pull out the I/F connector while the module is in operation.
(6) Do not disassemble the module.
(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.
(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD
modules in the specified storage conditions.
(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
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