BTS-111(S)-(11.20/04.21)-1700 Reg. No.
B
B.Tech. Degree III Semester Supplementary Examination
November 2020/April 2021
EC 15-1304 DIGITAL ELECTRONICS
(2015 Scheme)
Time: 3 Hours
Maximum Marks: 60
PART A
(Answer ALL questions)
(10x 2 20)
I. (a) What is the purpose of the
() following
(1) BCD code
(2) Gray code
(3) Parity bit
(ii) Prove: A + A'B = A + B.
(b) (i) List the different
representations of signed numbers.
(ii) F(A,B,C, D) = A+BC. Find the Max terms.
(c) F2(X,Y,Z) =
XY+X°Z. Implement using NOR gates only.
(d) How many outputs are there for a 4 input
6) Decoder
ii) Encoder
(ii) Priority encoder
(iv) Multiplexer
(e) Design a 2bit x 2bit binary multiplier using half adders and AND gates.
(fDesign an
asynchronous Mod 3 counter that counts 1-2-3-1-2-3....
(g) Explain the need of the diode in the totem pole output stage of a TTL
inverter.
(h) Define:
i) Noise Margin
(ii) Fanout
ii) Sinking Current
iv) VIH
(i) Name the type of modelling associated with each of the
statements following
(i) Process
(ii) Port map
(iii) If Then else
iv) Case
G) Write the entity description of a Demultiplexer with 4 select inputs.
(P.T.O)
BTS-11I(S)11.20/04.21)-1700
PART B
(4x 10-40)
+ d(2, 14). Reduce using Quine ()
=
Em (0,1,4,5,8,9,10)
I. (a) F:(A,B,C,D)
McClusky method.
and one binary output.
The output goes 1 (3)
A circuit has 3 binary inputs the
(b) takes the value 1'. Design and implement
when more than one input
circuit using basic gates.
OR
Consider the number 48.
ll. (1)
(a) equivalent binary number.
Convert 48 to its 7 bit
code. (1)
number to its equivalent gray
(b) Convert this 7 bit binary even parity hamming
code (7)
Consider the 7 bit binary number as the
(c) receiver. Check whether there
is any single
received at the hamming code Correct the
If so in which position.
bit error in the received information.
error and write down the
data bits and parity bits separately.
the subtraction of (1)
Representing 4 and 8 as 5 bit binary numbers, perform
(d)
4-8 in 2's complement method.
BCD numbers and get the result in
BCD. (7)
IV. (a) Design a BCD adder to add two
serial adder. (3)
b) Draw and explain a
OR
how addition is made fast using such
adders. (7)
V. (a) Name a fast adder, Explain
A+BC. Implement using suitable PROM.
(3)
(b) Fa(A,B,C)
=
using JK Fip flops. Modify the (10)
V1. Design a synchronous Mod 4 counter
counter output to generate the following sequence where each digit is
represented in 4 bit binary.
Logic
Sync Circuit
Clk- Counter
Mod4
2-0-2-1-2-0-2-1-2-0-2-1... cach digit in 4 bit binary.
OR
VII. (a) Design a 3bit Ring/Johnson Counter. Draw the output waveforms. (7)
Compare the modulus of the two counters.
(b) Draw and explain the circuit of tristate logic. (3)
VIII. Write VHDL code with entity and architecture descriptions for a
(a) Full subtractor in data flow modelling 3)
(b)binary decoder with the following specifications (7)
) 3 inputs
i) Active low outputs
ii) Active high Enable input E
OR
IX. Explain with examples the different data types used in VHDL. (10)
**
