12-9 ROM Applications

• Here are some of the most common application

areas in which ROMs are used:
– Function generator.
• Produces waveforms such as sine waves, sawtooth
waves, triangle waves, and square waves.

A ROM look-up table and a DAC are used

to generate a sine-wave output signal.
Digital Systems: Principles and Applications, 11/e Copyright © 2011, 2007, 2004, 2001, 1998 by Pearson Education, Inc.
Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss Upper Saddle River, New Jersey 07458 • All rights reserved
 11-1 Interfacing With the Analog World

• Most physical variables are analog, and can take

on any value within a continuous range of values.
– Normally a nonelectrical quantity.
• A transducer converts the physical variable to
an electrical variable.
– Thermistors, photo-cells, photodiodes, flow meters,
pressure transducers, tachometers, etc.

Digital Systems: Principles and Applications, 11/e Copyright © 2011, 2007, 2004, 2001, 1998 by Pearson Education, Inc.
Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss Upper Saddle River, New Jersey 07458 • All rights reserved
Introduction
 An ADC inputs an analog electrical signal such as voltage
or current and outputs a binary number. In block diagram
form, it can be represented as such:
Introduction
 A DAC, on the other hand, inputs a binary number and
outputs an analog voltage or current signal. In block
diagram form, it looks like this:
Introduction
 Together, they are often used in digital systems to provide
complete interface with analog sensors and output devices
for control systems such as those used in automotive
engine controls:
Introduction
 It is much easier to convert a digital signal into an analog
signal than it is to do the reverse. Therefore, we will begin
with DAC circuitry and then move to ADC circuitry.
 Analog-to-digital converters
Vmax = 7.5V 1111 4 4
7.0V 1110
6.5V 1101 3 3

analog output (V)

analog input (V)
6.0V 1100
5.5V 1011
2 2
5.0V 1010
4.5V 1001
4.0V 1 1
1000
3.5V 0111
3.0V 0110 time time
t1 t2 t3 t4 t1 t2 t3 t4
2.5V 0101
2.0V 0100 0100 0110 0110 0101 0100 1000 0110 0101
1.5V 0011 Digital output Digital input
1.0V 0010
0.5V 0001
0V 0000

proportionality analog to digital digital to analog

Embedded Systems Design: A Unified

Hardware/Software Introduction, (c) 2000 Vahid/Givargis
The n
R/2 R DAC
The n
R/2 R DAC
 For a simple inverting summer circuit, all resistors must
be of equal value.
 If any of the input resistors were different, the input
voltages would have different degrees of effect on the
output, and the output voltage would not be a true sum.
 Let's consider, however, intentionally setting the input
resistors at different values. Suppose we were to set the
input resistor values at multiple powers of two: R, 2R, and
4R, instead of all the same value R
The n
R/2 R DAC
The n
R/2 R DAC

Vo  b n 1b n  2 ...b1b 0  n 1 VREF

RF
2 R
The n
R/2 R DAC
 If we chart the output voltages for all eight combinations
of binary bits (000 through 111) input to this circuit, we
will get the following progression of voltages:
Binary Output voltage
000 0.00 V
001 -1.25 V
010 -2.50 V
011 -3.75V
100 -5.00 V
101 -6.25 V
110 -7.50 V
111 -8.75 V
The n
R/2 R DAC
 We can adjust resistors values in this circuit to obtain
output voltages directly corresponding to the binary input.
For example, by making the feedback resistor 800 Ω
instead of 1 kΩ, the DAC will output -1 volt for the binary
input 001, -4 volts for the binary input 100, -7 volts for the
binary input 111, and so on.
The n
R/2 R DAC
 with feedback resistor set at 800 ohms

Binary Output voltage

000 0.00 V
001 -1.00 V
010 -2.00V
011 -3.00V
100 -4.00 V
101 -5.00 V
110 -6.00 V
111 -7.00 V
The n
R/2 R DAC
 If we wish to expand the resolution of this DAC (add
more bits to the input), all we need to do is add more input
resistors, holding to the same power-of-two sequence of
values:
The R/2R DAC
 An alternative to the binary-weighted-input DAC is the
so-called R/2R DAC, which uses fewer unique resistor
values.
 A disadvantage of the former DAC design was its
requirement of several different precise input resistor
values: one unique value per binary input bit.
 Manufacture may be simplified if there are fewer different
resistor values to purchase, stock, and sort prior to
assembly.
The R/2R DAC
 Of course, we could take our last DAC circuit and modify
it to use a single input resistance value, by connecting
multiple resistors together in series:
 The R/2R DAC
 This "ladder" network looks like this:

Vo  b n 1b n  2 ...b1b 0  n VREF

RF
2 R
The R/2R DAC
 Either way, you should obtain the following table of
figures:
Binary Output voltage
000 0.00 V
001 -1.25 V
010 -2.50 V
011 -3.75V
100 -5.00 V
101 -6.25 V
110 -7.50 V
111 -8.75 V
Flash ADC
 Also called the parallel A/D converter, this circuit is
the simplest to understand.
 It is formed of a series of comparators, each one
comparing the input signal to a unique reference
voltage.
 The comparator outputs connect to the inputs of a
priority encoder circuit, which then produces a binary
output.
 The following illustration shows a 3-bit flash ADC
circuit:
Flash ADC
 Vref is a stable reference voltage
provided by a precision voltage
regulator as part of the converter
circuit, not shown in the
schematic.
 As the analog input voltage
exceeds the reference voltage at
each comparator, the comparator
outputs will sequentially saturate
to a high state.
 The priority encoder generates a
binary number based on the
highest-order active input,
ignoring all other active inputs.
Flash ADC
 When operated, the flash ADC produces an output that
looks something like this:
Flash ADC
 For this particular application, a regular priority encoder
with all its inherent complexity isn't necessary. Due to the
nature of the sequential comparator output states (each
comparator saturating "high" in sequence from lowest to
highest), the same "highest-order-input selection" effect
may be realized through a set of Exclusive-OR gates,
allowing the use of a simpler, non-priority encoder:
Flash ADC
Flash ADC
 And, of course,
the encoder
circuit itself can
be made from a
matrix of diodes,
demonstrating
just how simply
this converter
design may be
constructed:
Digital ramp ADC
 Also known as the stairstep-ramp, or simply counter A/D
converter, this is also fairly easy to understand but
unfortunately suffers from several limitations.
 The basic idea is to connect the output of a free-running
binary counter to the input of a DAC, then compare the
analog output of the DAC with the analog input signal to
be digitized and use the comparator's output to tell the
counter when to stop counting and reset. The following
schematic shows the basic idea:
Digital ramp ADC
Digital ramp ADC
Digital ramp ADC
 Note how the time between updates (new digital output
values) changes depending on how high the input voltage
is. For low signal levels, the updates are rather close-
spaced. For higher signal levels, they are spaced further
apart in time:
Successive approximation ADC
 Without showing the inner workings of the successive-
approximation register (SAR), the circuit looks like this:
Successive approximation ADC
Tracking ADC
 A third variation on the counter-DAC-based converter
theme is, in my estimation, the most elegant. Instead of a
regular "up" counter driving the DAC, this circuit uses an
up/down counter.
 The counter is continuously clocked, and the up/down
control line is driven by the output of the comparator. So,
when the analog input signal exceeds the DAC output, the
counter goes into the "count up" mode.
 When the DAC output exceeds the analog input, the
counter switches into the "count down" mode. Either way,
the DAC output always counts in the proper direction to
track the input signal.
Tracking ADC
Tracking ADC
 Notice how no shift register is needed to buffer the binary
count at the end of a cycle. Since the counter's output
continuously tracks the input (rather than counting to meet
the input and then resetting back to zero), the binary
output is legitimately updated with every clock pulse.
 An advantage of this converter circuit is speed, since the
counter never has to reset. Note the behavior of this
circuit:
Tracking ADC
Slope (integrating) ADC
 So far, we've only been able to escape the sheer volume of
components in the flash converter by using a DAC as part
of our ADC circuitry. However, this is not our only option.
It is possible to avoid using a DAC if we substitute an
analog ramping circuit and a digital counter with precise
timing.
Slope (integrating) ADC
 The is the basic idea behind the so-called single-slope, or
integrating ADC.
 Instead of using a DAC with a ramped output, we use an
op-amp circuit called an integrator to generate a sawtooth
waveform which is then compared against the analog
input by a comparator.
 The time it takes for the sawtooth waveform to exceed the
input signal voltage level is measured by means of a
digital counter clocked with a precise-frequency square
wave (usually from a crystal oscillator).
Slope (integrating) ADC
 The basic schematic diagram is shown here:
Slope (integrating) ADC
 The IGFET capacitor-discharging transistor scheme
shown here is a bit oversimplified.
 In reality, a latching circuit timed with the clock signal
would most likely have to be connected to the IGFET gate
to ensure full discharge of the capacitor when the
comparator's output goes high.
 The basic idea, however, is evident in this diagram. When
the comparator output is low (input voltage greater than
integrator output), the integrator is allowed to charge the
capacitor in a linear fashion.
 Meanwhile, the counter is counting up at a rate fixed by
the precision clock frequency.
Slope (integrating) ADC
 The time it takes for the capacitor to charge up to the same
voltage level as the input depends on the input signal level
and the combination of -Vref, R, and C.
 When the capacitor reaches that voltage level, the
comparator output goes high, loading the counter's output
into the shift register for a final output.
 The IGFET is triggered "on" by the comparator's high
output, discharging the capacitor back to zero volts.
 When the integrator output voltage falls to zero, the
comparator output switches back to a low state, clearing
the counter and enabling the integrator to ramp up voltage
again.
Slope (integrating) ADC
 This ADC circuit behaves very much like the digital ramp
ADC, except that the comparator reference voltage is a
smooth sawtooth waveform rather than a "stairstep:"