TABLE 5.

1
Unloaded BJT Transistor Amplifiers

Configuration Zi Zo Av Ai
Fixed-bias: Medium (1 k) Medium (2 k) High (- 200) High (100)
VCC
Io = RB 7 bre = RC 7 r o (RC 7 ro) bRBro
RC = - =
RB re (ro + RC)(RB + bre)
Ii
+ ⬵ bre ⬵ RC
Vo RC ⬵ b
+ Zo
– (RB Ú 10bre) (ro Ú 10RC) ⬵ -
Vi re
Zi (ro Ú 10RC,
–
(ro Ú 10RC) RB Ú 10bre)

Voltage-divider Medium (1 k) Medium (2 k) High (- 200) High (50)

bias: VCC
Io RC = R1 7 R2 7 bre = RC 7 r o RC 7 r o b(R1 7 R2)ro
R1 = - =
Ii
re (ro + RC)(R1 7 R2 + bre)
+ ⬵ RC
+ Zo RC b(R1 7 R2)
Vo (ro Ú 10RC) ⬵ - ⬵
Vi Zi R2 re R1 7 R2 + bre
RE CE
– – (ro Ú 10RC) (ro Ú 10RC)

Unbypassed High (100 k) Medium (2 k) Low (- 5) High (50)

emitter bias: VCC
= RB 7 Zb = RC RC bRB
Io RC = - ⬵ -
RB r e + RE RB + Zb
Ii Zb ⬵ b(re + RE) (any level of ro)
+
+ Zo ⬵ RB 7 bRE ⬵ -
RC
Vo RE
Vi
Zi RE (RE W re)
(RE W re)
– –

Emitter- High (100 k) Low (20 ) Low ( ⬵1) High (- 50)
follower: VCC
= RB 7 Zb = RE 7 r e RE bRB
Ii RB = ⬵ -
RE + r e RB + Zb
Zb ⬵ b(re + RE)
+ ⬵ re
⬵ RB 7 bRE ⬵ 1
Vi Io RE + (RE W re)
Zi Vo
– Zo (RE W re)
–
Common-base: Low (20 ) Medium (2 k) High (200) Low (- 1)
Ii
= RE 7 r e = RC RC ⬵ -1
⬵
+ Io RC + re
Vi Zi
RE
Vo ⬵ re
Zo
VEE VCC
– – (RE W re)

Collector Medium (1 k) Medium (2 k) High (- 200) High (50)

feedback: VCC
Io
RC re ⬵ RC 7 RF RC bRF
RF = ⬵ - =
1 RC re RF + bRC
+ (ro Ú 10RC)
Ii + b RF
(ro Ú 10RC) RF
+ Zo Vo (ro Ú 10RC) ⬵
(RF W RC) RC
Vi Z
o
– –

293
 TABLE 5.2
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

- (RL 储 RC) RB 7 bre RC

re

Including ro:

(RL 7 RC 7 ro)
- RB 7 bre RC 7 r o
re

- (RL 7 RC) R1 7 R2 7 bre RC

re

Including ro:

- (RL 7 RC 7 ro)
R1 7 R2 7 bre RC 7 r o
re

RE = RL 7 RE Rs = Rs 7 R1 7 R2
Rs
⬵ 1 R1 7 R2 7 b(re + RE) RE 储 a + re b
b

Including ro:
Rs
⬵ 1 R1 7 R2 7 b(re + RE) RE 储 a + re b
b

- (RL 7 RC) RE 7 r e RC
⬵
re

Including ro:

- (RL 7 RC 7 ro)
⬵ RE 7 r e RC 7 r o
re

VCC

- (RL 7 RC)
R1 7 R2 7 b(re + RE) RC
RC RE
R1
Vo
Rs Vi Including ro:
Zo
- (RL 7 RC)
+ RL R1 7 R2 7 b(re + Re) ⬵ RC
Vs Zi R2 RE
RE
–

294
 TABLE 5.2 (Continued)
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

VCC

- (RL 7 RC)
RC RB 7 b(re + RE1) RC
RB RE1
Vo
Rs Vi

Zo Including ro:
+ RE1 RL
Zi - (RL 7 RC)
Vs RB 7 b(re + RE) ⬵ RC
– REt
RE2 CE

VCC

- (RL 7 RC) RF
RC bre 储 RC
re 兩 Av 兩
RF
Vo

Rs Vi
Zo
Including ro:
+ RL
- (RL 7 RC 7 ro) RF
Vs bre 储 RC 7 RF 7 r o
– Zi re 0 Av 0

VCC

- (RL 7 RC) RF
RC bRE 储 ⬵ RC 7 RF
RE 0 Av 0
RF
Vo

Rs Vi
Zo Including ro:

+ RL - (RL 7 RC) RF
⬵ ⬵ bRE 储 ⬵ RC 7 RF
Vs
Zi RE
L
RE 0 Av 0
–

packaged system relates to the actual amplifier or network. The system of Fig. 5.61 is
called a two-port system because there are two sets of terminals—one at the input and the
other at the output. At this point it is particularly important to realize that
the data surrounding a packaged system is the no-load data.
This should be fairly obvious because the load has not been applied, nor does it come with
the load attached to the package.

Ii Io

+ +
Zi Zo
Vi AvNL Vo

– –

Thévenin

FIG. 5.61
Two-port system.
295
 TABLE 7.1
FET Bias Configurations

Type Configuration Pertinent Equations Graphical Solution

VDD ID
RD IDSS
JFET VGSQ = - VGG
Fixed-bias RG VDS = VDD - IDRS Q-point
VGG –
+ VP VGG 0 VGS

ID
VDD
IDSS
RD
JFET VGS = - IDRS
I'D
Self-bias VDS = VDD - ID(RD + RS) Q-point
RG RS
VP V' 0 VGS
GS

VDD ID
R2VDD IDSS
JFET R1 RD VG =
R1 + R2 VG
Voltage-divider
VGS = VG - IDRS Q-point RS
bias R2 RS
VDS = VDD - ID(RD + RS)
VP 0 VG VGS

VDD ID
RD IDSS
JFET VGS = VSS - IDRS VSS
Q-point
Common-gate VDS = VDD + VSS - ID(RD + RS) RS
RS
–VSS VP 0 VSS VGS

ID
VDD VGS = - IDRS IDSS
RD
JFET VD = VDD
(RD = 0 ⍀) VS = IDRS I'D
Q-point
VDS = VDD - ISRS
VP V'GS 0 VGS

VDD ID
RD Q-point IDSS
JFET
VGSQ = 0 V
Special case VGS = 0 V
IDQ = IDSS Q
(VGSQ = 0 V) RG
VGG
VP 0 VGS

ID
VDD
Depletion-type Q-point
MOSFET VGSQ = + VGG IDSS
Fixed-bias RG VDS = VDD - IDRS
RS
(and MESFETs)
VP 0 VGG VGS

VG ID
Depletion-type VDD R2VDD
MOSFET R1 RD VG = RS Q-point
R1 + R2 IDSS
Voltage-divider
R2 VGS = VG - ISRS
bias RS
VDS = VDD - ID(RD + RS)
(and MESFETs) VP 0 VG VGS

VDD ID
Enhancement VDD
RD RD
type MOSFET RG ID(on)
VGS = VDS
Feedback Q-point
VGS = VDD - IDRD
configuration
(and MESFETs) 0 VGS(Th) VDD VGS
VGS(on)

Enhancement VDD VG ID
R2VDD RS
type MOSFET RD
R1 VG =
Voltage-divider R1 + R2 Q-point
bias R2 RS VGS = VG - IDRS
(and MESFETs) 0 VGS(Th) VG VGS

450
 TABLE 8.1
Zi, Zo, and Av for various FET configurations

Configuration Zi Zo Vo
Av =
Vi
Fixed-bias
[JFET or D-MOSFET]
Fixed-bias +VDD
[JFET or D-MOSFET] Medium (2 k) Medium (- 10)
RD
C2 High (10 M)
C1
Vo = RD 储 r d = - gm(rd 储 RD)
Vi = RG
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
RG (rd Ú 10 RD)
Zi
–V
GG
+
Self-bias
bypassed RS
[JFET or D-MOSFET]
Self-bias +VDD
bypassed RS Medium (2 k) Medium (- 10)
[JFET or D-MOSFET] RD High (10 M)
C2
Vo = RD 储 r d = - gm(rd 储 RD)
C1 = RG
Vi
Zo ⬵ RD ⬵ - gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Zi
RG
RS CS

Self-bias
unbypassed RS
[JFET or D-MOSFET]
Low (- 2)
Self-bias +VDD RS
unbypassed RS c 1 + gmRS + dR
rd D gmRD
[JFET or D-MOSFET] RD High (10 M) = =
C2 RS RD RD + RS
Vo c 1 + gmRS + + d 1 + gmRS +
C1 = RG rd rd rd
Vi
Zo
= RD gmRD
Zi rd Ú 10 RD or rd =   ⬵ -
RG 1 + gmRS 3 rd Ú 10 (RD + RS)4
RS

Voltage-divider bias
[JFET or D-MOSFET]
Voltage-divider bias +VDD
[JFET or D-MOSFET]
Medium (2 k) Medium (- 10)
RD High (10 M)
C2
R1
Vo = RD 储 r d = - gm(rd 储 RD)
C1
Vi = R1 储 R2
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
(rd Ú 10 RD)
Zi
R2
RS CS

514
 TABLE 8.1
(Continued)

Configuration Zi Zo Vo
Av =
Vi
Common-gate
[JFET or D-MOSFET]
Medium (+ 10)
Common-gate +VDD Low (1 k⍀)
[JFET or D-MOSFET] Medium (2 k⍀) RD
RD r d + RD gmRD +
C1 Q1 C2 = RS 储 c d rd
1 + gmrd = RD 储 r d =
Vi Vo RD
1 +
⬵ RD rd
1
Zi RS Zo ⬵ RS 储 (Rd Ú 10 RD)

RG CS gm ⬵ gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Source-follower
[JFET or D-MOSFET]
Low ( 6 1)
Source-follower Low (100 k⍀)
[JFET or D-MOSFET] +VDD
High (10 M⍀) gm(rd 储 RS)
C1 = rd 储 RS 储 1>gm =
Vi 1 + gm(rd 储 RS)
C2 = RG
Zi RG
Vo ⬵ RS 储 1>gm gmRS
RS
(rd Ú 10 RS)
⬵
Zo
1 + gmRS
(rd Ú 10 RS)

Drain-feedback bias
E-MOSFET
Drain-Feedback bias +VDD Medium (1 M⍀)
E-MOSFET Medium (2 k⍀) Medium (- 10)
RD RF + r d 储 RD
RF C2 = = RF 储 r d 储 RD = - gm(RF 储 rd 储 RD)
Vo 1 + gm(rd 储 RD)
C1
Vi RF ⬵ RD ⬵ - gmRD
(RF, rd Ú 10RD)
Zo ⬵ (RF, rd Ú 10RD)
1 + gmRD
Zi (rd Ú 10 RD)

Voltage-divider bias
E-MOSFET
Voltage-divider bias +VDD
E-MOSFET
Medium (2 k⍀) Medium (−10)
RD
C2 Medium (1 M⍀)
R1 D Vo
= RD 储 r d = - gm(rd 储 RD)
C1
G = R1 储 R2
Vi
Zo ⬵ RD ⬵ - gmRD
S (rd Ú 10 RD) (rd Ú 10 RD)
Zi R2 RS

515
 TABLE 8.2

Configuration AvL ⴝ Vo 储 Vi Zi Zo

- gm(RD 储 RL) RG RD

+
Vss Including rd:
–
- gm(RD 储 RL 储 rd) RG RD 储 r d

- gm(RD 储 RL) RG RD
1 + gmRS 1 + gmRS

Including rd:
+
Vs - gm(RD 储 RL) RD
– RG ⬵
RD + RS 1 + gmRS
1 + gmRS +
rd

- gm(RD 储 RL) R 1 储 R2 RD

+
Vs Including rd:
–
- gm(RD 储 RL 储 rd) R 1 储 R2 RD 储 r d ;

gm(RS 储 RL) RG RS 储 1>gm

1 + gm(RS 储 RL)

+ Including rd:
Vs RS
– gmrd(RS 储 RL) gmrdRS
= RG 1 +
rd + RD + gmrd (RS 储 RL) r d + RD

gm(RD 储 RL) RS RD
1 + gmRS
+
Including rd: RS
Vs Zi = RD 储 r d
– gmrdRS
⬵ gm(RD 储 RL) 1 +
r d + RD 储 RL

519
 V - V 50 mV - 40 mV SUMMARY 591
c. P = = = 0.2
V 50 mV
P 0.2
fLo = fs = a b (5 kHz) = 318.31 Hz
p p

9.15 SUMMARY
●
Important Conclusions and Concepts
1. The logarithm of a number gives the power to which the base must be brought to
obtain the same number. If the base is 10, it is referred to as the common loga-
rithm; if the base is e = 2.71828c, it is called the natural logarithm.
2. Because the decibel rating of any piece of equipment is a comparison between levels, a
reference level must be selected for each area of application. For audio systems the ref-
erence level is generally accepted as 1 mW. When using voltage levels to determine the
gain in dB between two points, any difference in resistance level is generally ignored.
3. The dB gain of cascaded systems is simply the sum of the dB gains of each stage.
4. It is the capacitive elements of a network that determine the bandwidth of a system.
The larger capacitive elements of the basic design determine the low-cutoff frequency,
whereas the smaller parasitic capacitors determine the high-cutoff frequencies.
5. The frequencies at which the gain drops to 70.7% of the midband value are called the
cutoff, corner, band, break, or half-power frequencies.
6. The narrower the bandwidth, the smaller is the range of frequencies that will permit
a transfer of power to the load that is at least 50% of the midband level.
7. A change in frequency by a factor of two, equivalent to one octave, results in a 6-dB
change in gain. For a 10:1 change in frequency, equivalent to one decade, there is a
20-dB change in gain.
8. For any inverting amplifier, the input capacitance will be increased by a Miller effect
capacitance determined by the gain of the amplifier and the interelectrode (parasitic)
capacitance between the input and output terminals of the active device.
9. A 3-dB drop in beta (hfe) will occur at a frequency defined by fB that is sensitive to
the dc operating conditions of the transistor. This variation in beta can define the
upper cutoff frequency of the design.
10. The high- and low-cutoff frequencies of an amplifier can be determined by the
response of the system to a square-wave input. The general appearance will immedi-
ately reveal whether the low- or high-frequency response of the system is too limited
for the applied frequency, whereas a more detailed examination of the response will
reveal the actual bandwidth of the amplifier.

Equations
Logarithms:
a
a = bx, x = logba, log10 = log10 a - log10 b
b
P2 V2
log10 ab = log10 a + log10 b, GdB = 10 log10 = 20 log10
P1 V1
GdBT = GdB1 + GdB2 + GdB3 + g + GdBn
Low-frequency response:
1 1
Av = , fL =
1 - j( fL >f ) 2pRC
BJT low-frequency response:
1
fLs = , Ri = R1 储 R2 储 bre
2p(Rs + Ri)Cs
1
fLC = , Ro = RC 储 ro
2p(Ro + RL)CC
592 BJT AND JFET 1 Rs
FREQUENCY RESPONSE fLE = , Re = RE 储 a + re b , Rs = Rs 储 R1 储 R2
2pReCE b
FET low-frequency response:
1
fLG = , Ri = RG
2p(Rsig + Ri)CG
1
fLC = , Ro = RD 储 rd
2p(Ro + RL)CC
1 RS 1
fLS = , Req = ⬵ RS " `
2pReqCS 1 + RS(1 + gmrd)>(rd + RD 储 RL) gm rd ⬵  
Miller effect capacitance:
1
CMi = (1 - Av)Cf, CMo = a 1 - b Cf
Av
BJT high-frequency response:
1 1
Av = , fHi = , RThi = Rs 储 R1 储 R2 储 Ri,
1 + j( f>fH) 2pRThiCi
Ci = CWi + Cbe + CMi
1
fHo = , RTho = RC 储 RL 储 ro, Co = CWo + Cce + CMo,
2pRThoCo
hfemid
hfe =
1 + j( f>fb)
1
fb ⬵
2pbmidre(Cbe + Cbc)
fT ⬵ hfemid fb
FET high-frequency response:
1
fHi = , RThi = Rsig 储 RG, Ci = CWi + Cgs + CMi,
2pRThiCi
CMi = (1 - Av)Cgd
1
fHo = , RTho = RD 储 RL 储 rd, Co = CWo + Cds + CMo,
2pRThoCo
1
CMo = a 1 - b Cgd
Av
Multistage effects:
fL
f L = , f H = (221>n - 1)fH
22 1>n
- 1
Square-wave testing:
0.35 P V - V
BW ⬵ fHi = , fLo = fs, P =
tr p V

9.16 COMPUTER ANALYSIS

●
The computer analysis of this section will verify the results of a number of examples
appearing in this chapter.

Low-Frequency BJT Response

The network of Example 9.12 with its various capacitors appears in Fig. 9.64. The sequence
Edit-PSpice Model was used to set Is to 2E-15A and beta to 100. The remaining parame-
ters of the PSpice Model for the transistor were removed to idealize the response to the
greatest degree possible. In the Simulation Settings dialog box AC Sweep/Noise was
selected under the Analysis type heading, and Linear was chosen under the AC Sweep
Type. The Start Frequency was set at 10 kHz, the End Frequency at 10 kHz, and the
714 POWER AMPLIFIERS 12.9 SUMMARY
●
Important Conclusions and Concepts
1. Amplifier classes:
Class A—the output stage conducts for a full 360° (a full waveform cycle).
Class B—the output stages each conduct for 180° (together providing a full cycle).
Class AB—the output stages each conduct between 180° and 360° (providing a full
cycle at less efficiency).
Class C—the output stage conducts for less than 180° (used in tuned circuits).
Class D—has operation using digital or pulsed signals.
2. Amplifier efficiency:
Class A—maximum efficiency of 25% (without transformer) and 50% (with trans-
former).
Class B—maximum efficiency of 78.5%.
3. Power considerations:
a. Input power is provided by the dc power supply.
b. Output power is that delivered to the load.
c. Power dissipated by active devices is essentially the difference between the
input and output powers.
4. Push–pull (complementary) operation is typically the opposite of that of devices with one
on at a time—one “pushing” for half the cycle and the other “pulling” for half the cycle.
5. Harmonic distortion refers to the nonsinusoidal nature of a periodic waveform—the
distortion being defined as that at the periodic frequency and multiples of that frequency.
6. Heat sink refers to the use of metal cases or frames and fans to remove the heat gen–
erated in a circuit element.

Equations
Pi (dc) = VCC ICQ
Po (ac) = VCE (rms)IC (rms)
= I 2C (rms)RC
V C2 (rms)
=
RC
VCE (p)IC (p)
Po (ac) =
2
2
I C (p)
=
2RC
2
V CE (p)
=
2RC
VCE (p@p)IC (p@p)
Po (ac) =
8
2
I C (p@p)
= RC
8
2
V CE (p@p)
=
8RC
Po(ac)
%h = * 100%
Pi(dc)
Transformer action:
V2 N2
=
V1 N1
I2 N1
=
I1 N2
Class B operation: COMPUTER ANALYSIS 715
2
Idc = I(p)
p
2
Pi (dc) = VCC a I(p)b
p
V L2 (rms)
Po (ac) =
RL
2
V CC
maximum Po (ac) =
2RL
2VCC 2V 2CC
maximum Pi(dc) = VCC (maximum Idc) = VCC a b =
pRL pRL
2
2V CC
maximum P2Q =
p 2RL
Harmonic distortion:
0 An 0
% nth harmonic distortion = % Dn = * 100%
0 A1 0
Heat sink:
uJA = uJC + uCS + uSA

12.10 COMPUTER ANALYSIS

●
Program 12.1—Series-Fed Class A Amplifier
Using Design Center, we draw the circuit of a series-fed class A amplifier as shown in
Fig. 12.28. Figure 12.29 shows some of the analysis output. Edit the transistor model for
values of only BF  90 and IS  2E-15. This keeps the transistor model more ideal so
that PSpice calculations better match those below.

FIG. 12.28
Series-fed class A amplifier.

The dc bias of the collector voltage is shown to be

Vc(dc) = 12.47 V
With transistor beta set to 90, the ac gain is calculated as follows:
IE = Ic = 95 mA (from analysis output of PSpice)
re = 26 mV>95 mA = 0.27