VISVESVARAYA TECHNOLOGICAL UNIVERSITY
JNANASANGAMA,BELAGAVI-590014
Integrated Laboratory Manual
for
“Digital Design & Computer Organization”
BACHELOR OF ENGINEERING
in
Department of CSE(Artificial Intelligence & Machine Learning)
Prepared by:
Lab Incharge
C.M.Sumana,Asst.prof
Dept.of CSE(AI & ML) ,RYMEC Ballari
V.V.SANGHA’S
RAOBAHADURY.MAHABALESWARAPPAENGINEERINGCOLLEGE
DEPARTMENT OF CSE(Artificial Intelligence & Machine Learning)
BALLARI- 583 104
2024-2025
DD&COLabManual
Syllabus
Digital Design and Computer Organization Semester:3
Course Code : BCS302 CIE Marks:50
PRACTICALCOMPONENTOFIPCC
1. Given a 4-variable logic expression,simplify it using appropriate technique and simulate the
same using basic gates.
2. Design a 4 bit full adder and subtractor and simulate the same using basic gates.
3. Design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.
4. Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and
Full Subtractor.
5. Design Verilog HDL to implement Decimal adder.
6. Design Verilog program to implement Different types of multiplexer like 2:1,4:1 and 8:1.
7. Design Verilog program to implement types of De-Multiplexer.
8. Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
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1. Given a 4-variable logic expression, simplify it using appropriate technique and implement
the same using basic gates
COMPONENTS REQUIRED:
IC7400, IC7408,IC7432, IC7404, IC7402,Connecting wires
THEORY:
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive normal
form (sum of min-terms) or conjunctive normal form (product of maxterms). A Boolean function can be
represented by a Karnaugh map in which each cell corresponds to a minterm. The cells are arranged in
such a way that any two immediately adjacent cells correspond to two minterms of distance 1. There is
more than one way to construct a map with this property.
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Result:A4-variable logic expression is simplified, designed and verified using truth table.
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2. Design a 4 bit full adder and subtractor and simulate the same using basic gates .
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Waveform
Result:A 4-bitadder subtractor circuit is designed and verified using basic gates.
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3. Design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.
(i) Verilog code for half adder(structural description):
BlockDiagram TruthTable
LogicDiagram
module half_adder(output sum, carry, input A,B);
xor(sum, A, B);
and(carry,A,B);
end module
Waveform:
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(ii) Verilog code for 2:1 mux(dataflow description):
BlockDiagram TruthTable
Input Output
2:1 S0 out
mux
0 I0
1 I1
module mux_2to1_dataflow ( input S, input I0, I1, output out);
assign Y = (S & ~I1) | (~S & I0);
end module.
(iii) Verilog code for 2:1mux(Behavioural description):
module mux_2_1(inp,sel,outp);
input [1:0] inp;
input[0:0]sel;
output outp;
reg outp;
always@(sel,inp)
begin
case(sel)
1’b0 : outp = inp[0];
default:outp=inp[1];
end case
end
end module
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Output:
Waveform
Result: Verilog HDL for simple circuits using structural, Data flow and Behavioural model is designed,
implemented and verified using truth table.
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4. Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and
Full Subtractor.
Verilogcodeforhalfadder:
BlockDiagram TruthTable
LogicDiagram
module half_adder(output sum, carry, input A,B);
xor(sum, A, B);
and(carry,A,B); endmodule
OUTPUT:
Result: Verilog HDL for Binary half-adder is designed implemented and verified using truth table.
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Verilog code for full adder
CircuitDiagram
BlockDiagram
TruthTable
module full_adder(outputsum,cout,
input A, B, Cin);
wires1, c1,c2;
half_adder ha1 (s1,c1,A,B);
half_adder ha2 (sum,c2,s1,Cin);
or o1(cout,c1,c2);
end module
Output:
Result:Verilog HDL for Binary full Adder is designed implemented and verified using truth table.
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Verilog code for half-subtractor
LogicDiagram
BlockDiagram TruthTable
module half_subtractor(inputa,b,outputD,B);
b assign D = a ^ b;
assign B=~a&b;
end module
OUTPUT:
Result:Verilog HDL for Binary half-subtractor is designed implemented and verified using truth table.
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Verilog code for full subtractor
CircuitDiagram
BlockDiagram
TruthTable
module full_subtractor(inputa,b,Bin,output
,outputD,Bout);
assign D = a ^ b ^ Bin;
assign Bout=(~a&b)|(~(a^b)&Bin);
end module
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Output:
Result:Verilog HDL for Binary full-subtractor is designed implemented and verified using truth table.
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5. Design Verilog HDL to implement Decimal adder.
module deci(a,b,sum,cout);
input [3:0] a;
input[3:0]b;
output[3:0]sum;
output cout;
reg[3:0]sum;
reg cout;
always@(a,b)
begin
{cout,sum} = a+b;
if(a>9||b>9||sum>9)
begin
{cout,sum}=sum+6;
end
end
end module
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OUTPUT:
Result: Verilog HDL for decimal adder is designed & verified.
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6. Design Verilog program to implement Different types of multiplexer like 2:1,4:1and 8:1.
Verilog code for 2:1 mux
Block Diagram
Truth Table
Input Output
2:1 S0 out
mux
0 I0
1 I1
module mux_2_1(inp,sel,outp);
input [1:0] inp;
input[0:0]sel;
output outp;
reg outp;
always@(sel,inp)
begin
case(sel)
1’b0 : outp = inp[0];
default:outp=inp[1];
end case
end
end module
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Verilogcodefor4:1mux
BlockDiagram
module mux_4_1(inp,sel,outp);
input [3:0] inp;
input[1:0]sel;
output outp;
reg outp;
always@(sel,inp)
begin
case(sel)
2’b00 : outp = inp[0];
2’b01: outp = inp[1];
2’b10: outp = inp[2];
default:outp=inp[3];
end case
end
end module
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Verilog code for 8:1 mux
Truth Table
Block Diagram
module mux_8_1(inp,sel,outp);
input [7:0] inp;
input[2:0]sel;
output outp;
reg outp;
always@(sel,inp)
begin
case(sel)
3’b000:outp=inp[0];
3’b001: outp = inp[1];
3’b010: outp = inp[2];
3’b011: outp = inp[3];
3’b100: outp = inp[4];
3’b101: outp = inp[5];
3’b110: outp = inp[6];
default: outp = inp[7];
end case
end
end module
Result:Verilog program for 2:1,4:1,8:1 mux is designed, implemented and verified using truth table.
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7. Design Verilog program to implement types of De-Multiplexer. a Write a Verilog code for
1:2 demux
module dmux_12(din,sel,dout);
input din;
input[0:0]sel;
output[1:0]dout;
reg [7:0] dout;
always@(sel,din)
begin
case(sel)
1'b0: dout[0]=din;
default:dout[1]=din;
end case
end
end module
Truth Table
Sel Dout0 Dout1
0 Din 0
1 0 Din
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b.Write a Verilog code for 1:4demux
module dmux_14(din,sel,dout);
input din;
input[1:0]sel;
output[3:0]dout;
reg [3:0] dout;
always@(sel,din)
begin
case(sel)
2'b00 : dout[0]=din;
2'b01 : dout[1]=din;
2'b10 : dout[2]=din;
default : dout[3]=din;
end case
end
end module
Truth Table
S0 S1 D0 D1 D2 D3
0 0 i 0 0 0
0 1 0 i 0 0
1 0 0 0 i 0
1 1 0 0 0 i
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c.Write a Verilog code for 1:8 demux
module dmux_18(din,sel,dout);
input din;
input[2:0]sel;
output[7:0]dout;
reg [7:0] dout;
always@(sel,din)
begin
case(sel)
3'b000 : dout[0]=din;
3'b001 : dout[1]=din;
3'b010 : dout[2]=din;
3'b011 : dout[3]=din;
3'b100 : dout[4]=din;
3'b101 : dout[5]=din;
3'b110 : dout[6]=din;
3'b111 : dout[7]=din;
end case
end
TruthTable
end module
S0 S1 S2 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 i 0 0 0 0 0 0 0
0 0 1 0 i 0 0 0 0 0 0
0 1 0 0 0 i 0 0 0 0 0
0 1 1 0 0 0 i 0 0 0 0
1 0 0 0 0 0 0 i 0 0 0
1 0 1 0 0 0 0 0 i 0 0
1 1 0 0 0 0 0 0 0 i 0
1 1 1 0 0 0 0 0 0 0 i
Result:Verilog program for 1:2,1:4,1:8 demux is designed, implemented and verified using truth table.
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8. Design Verilog program for implementing various types of Flip-Flops such as SR ,JK and
D FF
(a) Write a Verilog code for SR Flip-Flop with test bench forVerification.
modulesr_ff(sr,clk,q,qb);
input [1:0]sr;
input clk;
output q,qb;
reg q,qb;
always@(posedge(clk))
begin case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bz;
end case
qb=~q;
end
end module
TruthTableofSRFlip-Flop
CLK SR Q Qb State
Risingedge 00 Q Qb No change
Risingedge 01 0 1 Reset
Risingedge 10 1 0 Set
Risingedge 11 Z Z Undefined
1 or 0 XX Q Qb No change
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(b) Write a Verilog code forJKFlip-Flop with test bench for Verification.
module jk(jk,clk,q,qb);
input [1:0]jk;
input clk;
outputq,qb;
reg q,qb;
always@(posedge(clk))
begin
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
end case
qb=~q;
end
end module
Truth Table of JK Flip-Flop
CLK JK Q Qb State
Risingedge 00 Q Qb No change
Risingedge 01 0 1 Reset
Risingedge 10 1 0 Set
Risingedge 11 Q Q Toggle
1 or 0 XX Q Qb No change
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(c) Writea Verilog code for D Flip-Flop
module df(d,clk,q,qb);
input d,clk;
output q,qb;
reg q,qb;
always@(posedge(clk))
begin q=d;
qb=~q;
end
end module
TruthTableof DFlip-Flop
Clk D Q Qb State
Rising edge 1 1 0 Set
Rising edge 0 0 1 Reset
1 or 0 X Q Qb No Change
Result:Verilog program for SR,JK,D Flip flop is designed, implemented and verified using truth table.
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