Document Revision

DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE A

{pA_1}

Application Note for QFP_Design and Board Assembly Guide

-3/Entity/Geographical Procedures and Specs/ Technology
Design Manuals and Rules/ Product Design Document

Document Properties
Status ACTIVE
Status Date 09-May-2018
Alternate Name a
Classification ST Restricted
Hierarchy Level & Family -3/ Entity/Geographical Procedures and Specs
Hierarchy Sub-level & Type/Category -2/ Technology Design Manuals and Rules/ Product Design
Document
Applicability Entity
Business Domain / Business Sub-Domain
Original ID
Original Repository

PDP Deliverable No
Business Domain Technology R&D
Product Development
Quality
Business Sub-Domain

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying
 Document Revision
DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE B
{pA_1}

Document Actors

Name/Function Role Date

Loh Hung Meng Editor N/A

Package Development

Petit Luc Responsible N/A

Assembly Technologies Dev

Thapar Robbin Kumar Document Controller 07-May-2018

Technology & Manufactg Qual

Petit Luc Approver 07-May-2018

Assembly Technologies Dev

Yap Daniel Approver 09-May-2018

Package Development

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying
 Document Revision
DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE C
{pA_1}

Referenced Document

Alternate Name Document ID Document Document Title

Relation

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying
 Document Revision
DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE D
{pA_1}

Revision History

Typing error, amends and adding in of reference documents

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
1/20

CONTENTS Page
_____________________________________________________
1. INTRODUCTION ----------------- 2
2. SCOPE ----------------- 2
APPLICATION 3 PACKAGES ----------------- 3-4
4. BOARD DESIGN ----------------- 5-8
NOTE FOR -- Land Pattern Design ----------------- 6
QFP -- Thermal Pad (with Vias) Design ----- 7-8
5. BOARD ASSEMBLY ----------------- 9
-- Assembly Process Flow ----------------- 9
-- Stencil Design for Perimeter Pads --- 9
Design and Board Assembly
guide for Quad Flat Package -- Stencil Design for Thermal Pad -----10-11
with exposed Pad -- Solder Paste Printing ---------------- 11
-- Solder Paste Inspection --------------- 11
-- Component Placement --------------------12
-- Convection Reflow ----------------- 13
-- Double-Sided Process ----------------- 13
6. INSPECTION, DEFECT & ANALYSIS --- 14
7. MOUNTING OF EXPOSED PAD UP ------15
8. BOARD LEVEL RELIABILITY ---------- 16
9. REWORK GUIDELINES -------------- 17-18
10. HANDLING ---------------- 19
11. REFERENCES ---------------- 20
12. ABBREVIATIONS ----------------- 20
13. REVISION HISTORY ----------------- 20
14. DISCLAIMER ----------------- 20

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
2/20

1. INTRODUCTION

QFP is a package for Surface Mount Device. It has a flat rectangular or square body, usually square with
leads on the four sides. There are a few types of QFP depending on thickness such as PQFP, LQFP & TQFP.
PQFP stands for Plastic Quad Flat Package without exposed pad on top or bottom of package for heat
dissipation. TQFP / LQFP with exposed pad is made with a deep down-set leadframe such as the bottom
side as of the die paddle is flushed with the bottom side of the package and is exposed. This allows the
exposed pad to be soldered directly to the PCB and facilitates heat dissipation (as Figure 1 and Table 1).

Exposed-pad has no impact on the reflow profile, which is the same as for conventional PQFP/TQFP/LQFPs.
Obviously, wave soldering is not recommended at all as it will be impossible to solder correctly the
exposed pad. Although the land patterns for leads soldering on the PCB are not specific, extra features are
required during the PCB design and assembly process for mounting TQFP / LQFP with exposed pad.

Figure 1: Heat transfer schematic of QFP with Exposed Pad A QFP

Package/ soldering method Rth (j-a)

Full plastic (no exposed-pad) 43°C/W
Exposed pad not soldered to PCB 28°C/W
Exposed pad soldered to PCB, following the
23°C/W
recommendation of this document

Table 1: Example of thermal dissipation: LQFP 14x14 (4x4mm die, 6x6mm pad, board 2s2p)

2. SCOPE

This document provides guidelines for handling and assembly of STM QFP packages during Printed Circuit
Board (PCB) assembly, especially proper board and stencil design, assembly and rework conditions.
It is noted that the specific information about each device is not provided and serves only as a guideline to
help users develop a specific solution. Actual experience and development efforts are still required to
optimize the assembly process and application design per individual device requirements, industry
standards such as IPC and JEDEC, and prevalent practices in user’s assembly environment.

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
3/20

3. PACKAGES

3.1 QFP Packages

A QFP or Quad Flat Package is a surface mount integrated circuit package with "gull wing" leads extending
from each of the four sides. The leads are formed in a gull wing shape to allow solid footing during
assembly to a PCB pad as show in fig. 2.
The quad flat-pack has connections only around the periphery of the package. Typical QFP pitch are 0.4mm,
0.50mm, 0.65mm and 0.80mm.

Figure 3 show some of the available QFP manufacture by STMicroelectronics.

Gull Wing Lead

QFP 10X10-64_0.5p QFP 10X10-80_0.4p

Figure 2: QFP Leads Figure 3: Sample QFP

3.2 PQFP

PQFP design is without exposed pad and the body thickness is >2.00mm. Although the package is design
for SMT, it can also be use for wavesoldering process as there is no exposed pad to be solder providing
lead pitch is >1.00mm.

Wire
Die
Lead

Figure 4: Package Bottom View Fig. 5: X-section view of PQFP

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
4/20

3.3 LQFP & TQFP

Two type of body thicknesses are available, 1.4mm (LQFP) and 1.0mm (TQFP). LQFP will have both full
plastic and exposed pad, as for TQFP only exposed pad available. The exposed pad is made with a deep
down set lead frame such as bottom side of the die paddle is flush with the bottom side of the package and
is exposed as show in fig. 6. This allows the exposed pad to be soldered directly to the PCB for high heat
dissipation.

E-pad
Wire Die
Lead

With E-pad

Exposed Pad Down Exposed Pad Up

Figure 6: Package Bottom View Fig. 7: X-section view of Exposed Pad QFP

3.4 Package lead surface finishing

Package surface finishing is lead-free with either plated matt tin (Pb-free categorized as e3) or pre-plated
lead-frame (e.g. NiPdAu, categorized as e4), e3 and e4 refer to the JEDEC JEP 709 standard of Lead-free
labelling. Pin1 indicator is often done by special pattern on top & bottom of the package. See some
examples as below figure 8.

Matt Tin Finishing Pre Plated Finishing

Fig. 8: Leads Finishing
3.5 Packages sizes and designations

Packages designations are defined in JEDEC standard Publication 95 divided in several Design Guides.

QFP Size I/O’s Pitch min. Thickness Exposed

(mm) (mm) (mm) pad (e.g.)
TQFP 10x10 64 0.5 1.0 4.5x4.5
TQFP 10x10 80 0.4 1.0 5.4x5.4
LQFP 10x10 64 0.5 1.4 2.0x2.0
TQFP 14x14 100 0.5 1.0 7.0x7.0
TQFP 14x14 128 0.4 1.0 7.5x7.5
TQFP 20x20 144 0.5 1.0 7.0x7.0
LQFP 24x24 176 0.5 1.4 7.5x7.5

Table 2: Example of QFP packages produced by STMicroelectronics.

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
5/20

4. BOARD DESIGN

Correct PCB footprint and stencil designs are critical to surface mount assembly yields and subsequent
electrical and mechanical performance of the mounted package. The package design can be obtained from
STMicroelectronics Package Outline Assembly drawing as illustrated in Fig.9

Fig. 9: Example of TQFP10x10-64

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
6/20

4.1 Land Pattern Design

It is recommended to use a Non Solder Mask Defined (NSMD) pad, with opening slightly larger than the
solder land to adhere to the sides of the Cu land for better reliability.

Figure 10: comparison of NSMD pad and SMD pad.

The solder mask opening should be min. 0.050 mm, for the registration tolerance of the solder mask. For
very fine pitch of 0.4mm, solder mask opening with “trench” could be considered as not enough space for
solder mask web in between pads, see figure 11.

Solder Mask Solder Mask

Figure 11: Solder Mask Opening for Perimeter Lands with pitch 0.5mm and 0.4mm.

The typical QFP lead is used for illustration of land pattern with solder joint fillet as figure 12.

Figure 12: Solder joint fillet at toe, heel and side _ toe fillet is not required, as unlikely for exposed base
surface to wet after sawed, pending on solder paste flux and oxidation level (IPC A610)

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
7/20

4.2 Thermal Pad (with Vias) Design

Central thermal pad provides a solderable surface on the top of the PCB (for soldering the package
exposed die paddle on the board); thermal vias are needed to provide a thermal path to inner and bottom
layers of the PCB to remove/dissipate the heat.

The size of thermal pad can be matched with exposed die paddle, or smaller with consideration of
clearance for vias to route the inner row signals. Typical land pattern dimensions show in fig. 13 for QFP,
with some assumptions for 4 layers FR4 with ½ oz Cu as follows:
- Min. drill diameter : 0.300mm
- Min. finished hole diameter : 0.250mm
- Via capture pad diameter : 0.500mm
- Inner layer anti-pad diameter : 0.800mm

0.80mm

0.25mm

0.30mm

0.50mm

Fig.13 : Example of via design

The number of thermal vias will depend on the application operating environment and condition, power
dissipation, and electrical requirements. Typical design incorporates an array of thermal vias, e.g. about 1-
1.2mm pitch with via dia. 0.3 mm as per fig .14.

Figure 14: 1.2mm pitch on a 11x11mm E pad with solder mask plugged vias

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
8/20

Besides, it is recommended to plug with covered liquid photo-imageable (LPI) solder mask on via to avoid
solder wick down the vias during the reflow process. Some other methods like
- Capping via with metalized coating, that is more robust but expensive.
- Tented via with dry film solder mask (min. 100um larger than via diameter)

Figure 15: Example of a Single & Double sided plug Vias *(IPC-7093)

Some may suggest about 20% of solderable area on thermal pad be covered by solder mask ; in
conjunction with aperture opening for 50-80% solder coverage on solderable area to maintain effective
heat dissipation.

In general, more vias may allow better thermal heat flow, as illustrated in figure 16; while the efficiency of
thermal performance gradually diminish with continuous increasing number of vias.

Figure 16: Thermal images case A is showing 9% thermal improvement as compare with case B.

Some vias placed toward periphery of thermal pad could slightly improve the heat spreading.
The recommended thermal pad on board should be solder mask defined to avoid any solder bridging
between the perimeter pads and thermal pad. The respective thermal pad should exclude the grooves/
rings at the edge of package thermal paddle.

Common board finishing are Organic Solderability Preservative (OSP), Electroless Nickel Immersion Gold
(ENIG) with good flatness and acceptable land pad surface.

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
9/20

5. BOARD ASSEMBLY

Note: this application note is intended as a guide. Precise process development and experimentation are
needed to optimize specific applications or performance.

5.1 Assembly Process Flow

Figure 17: Typical surface mounting process flow.

5.2 Stencil Design for Perimeter Pads

Laser cut electro-polished Stainless Steel (or Nickel) stencil is recommended. Tapered aperture walls
(5° tapering) are recommended to facilitate paste release. For a nominal standoff of 0.10mm, suggest a
stencil thickness (T) of 127μm for 0.4mm and 152um for 0.5mm pitch. Stencil aperture should follow the
following Aspect and Area Ratio rules:

The stencil aperture is typically designed to match the PCB perimeter pad size (i.e., 1:1) as show in fig.18

Fig.18: Stencil aperture opening 1:1 to PCB pad

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
10/20

5.3 Stencil Design for Thermal Pad

A segmented (or multiple small openings, instead of one big opening) design is recommended for the
thermal pad apertures. This design helps to minimize voids as outgassing of flux better escape at gap (e.g.
0.2mm or more) in the thermal region.

Improper stencil thickness causing solder paste no contact to E

Correct stencil thickness will give good contact to E Pad

Air vent gap to allow flux solvent to
evaporate and help to minimize solder
voids.
Figure 19: Effect of solder paste deposition

It is noteworthy that too little solder volume may compromise the solder joint reliability especially the E
Pad which cause no full contact to solder after reflow. When there is a consideration to assemble fine pitch
or small component together with the QFP and unable to increase the stencil thickness, special care must
be taken care for the E pad solder volume. The solder volume can be increase with the following method.

1. Using Step stencil.

Step up stencil on the E-pad area to increase the solder paste volume during printing and this will
help to have full contact between the PCB pad and the exposed pad after reflow.
Step up for E pad to have more solder volume

Figure 20: Example of step up stencil

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
11/20

2. Masking of E pad

Proposed stencil opening (black outline for solder paste deposition) on the PCB thermal pad with
short stripes of soldermask (SM), this may enhance better air venting on each outer regions,
esp. to diverge/redirect the molten solder to move inner center to form a higher standoff lump
for better solder contact/joint on each region.
The stripes of solder mask on PCB thermal pad can be slightly bigger than outer border of multiple
stencil opening or partial underneath with pattern corresponding to the stencil opening.

Figure 21: Multiple stencil opening on PCB thermal pad design with stripes of solder mask.

5.4 Solder Paste Printing

Solder paste type 4 (or type 3) is recommended to optimize the deposition efficiency for fine pitch QFP.
No Clean, Halogen free solder paste with low voiding properties designed for fine pitch printing is
recommended. Avoid water soluble paste as its flux tends to corrode after prolong time if it is not well
cleaned due to very narrow gap hidden underneath the package. Printers with automatic stencil cleaning
is highly recommended to prevent solder paste bridging and clogging.

Solder Paste Type 3 4

Powder Size (um) 45-25 36-25
0.5mm √ √
Pitch
0.4mm √

Table 3: solder paste selection

5.5 Solder Paste Inspection

Inspection of the printed solder paste is highly recommended before placing parts. A 2D (X, Y) inspection or
an automated 3D (X, Y, Z) volume inspection or a statistical measurement process control plan should be
embedded inside the assembly process to assure a repeatable solder deposit and a high yield assembly
quality.

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
12/20

5.6 Component Placement

Precise and accurate component placement is required (tolerance of +/-50um & below) to have uniform
solder fillet coverage, especially with the high I/O configurations.

Misalignment can easily cause solder bridging and other solder fillet problems like incomplete fillet or
skewed fillet coverage.

The “Force control” placement is recommended and should be minimized where possible.
- Excessive pressure may cause short due to solder squeeze out from underneath part.
- Excessive bending of the substrate may also lead to package damage and should be avoided in the
assembly flow.

The guideline of the mounting before pre-reflow:

- Placement alignment out within 25% with respect to the lead width is still acceptable, as it will self-
centering during reflow. More than 25% may not self-align and it may cause solder joint reliability
issue as illustrated in figure 22.

Figure 22: View from QFP lead toe direction, Placement and self-alignment during reflow.

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
13/20

5.7 Convection Reflow

There are no special requirements necessary when reflowing QFP components. As with all SMT
components, it is important that profiles be checked on all new board designs. In addition, if there are
multiple packages on the board, the profile must be checked at different locations on the board.
The solder paste manufacturer’s temperature profile should be used to optimize flux activity and minimize
the voiding. The recommended lead-free reflow profile as illustrated on figure 23 and Table 4, as well as
thermocouple insertion on profile board; see figure 24.

Thermocouple

Figure 23: Typical lead-free reflow profile for QFP Figure 24: thermocouple insertion

Table 4: QFP recommended profile parameters (Lead-free mounting

Profile Ramp to spike Ramp-soak-Spike

Temperature gradient in preheat Temp. : 70°C to 150°C Temp. : 70°C to 150°C
0.8°C/sec to 1.0 °C/sec 1°C/sec to 3 °C/sec
Soak / Dwell (Refer to solder N/ A or Soak
paste supplier recommendation) Temp. :150°C to 200°C: 40 to 80s Temp. :150°C to 200°C: 40 to 100 s
Temperature gradient in preheat Temp. : 200°C to 225°C: Temp. : 200°C to 225°C:
1°C/sec. to 3°C/sec. 1°C/sec. to 3°C/sec.
Peak temperature 235°C to 245°C
Duration above 220°C 45 to 75 seconds
Temperature gradient in cooling - 1°C to – 5°C
Cooling time 150 to 230 seconds

5.8 Double-Sided Process

The double-sided process follows the same procedure as the single-sided process: mount and reflow the
packages on one side and simply turnover the board and repeat the process. However, more voids may
occur as additional outgassing at second reflow.

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
14/20

6. INSPECTION, DEFECTS AND ANALYSIS

After surface mount assembly, X-ray should be used for sample monitoring of the solder attachment
process; this identifies defects such as solder bridging, and opens. See Table 5.

Type of Defects Causes Remedy

1) Excessive solder volume especially 1) Optimize the stencil aperture opening
Solder Short
for fine pitch package 2) Ensure print accuracy and consistency for
2) Misaligned printing both print strokes.
3) Big gap in between stencil and 3) Zero print gap between stencil and PCB
PCB – paste oozes out beneath Check paste smear underneath stencil.
stencil during printing, increasing 4) Apply automatic stencil cleaning in printer
chance of wet solder paste bridges (Wet, Vacuum, Dry cleaning mode)

1) Solder paste adheres on the 1) Area ratio >0.66 for better paste release
Insufficient Solder stencil aperture walls 2) Verify print setup and Reduce print speed to
2) Printing parameter provide sufficient time for paste to roll into
3) Solder paste viscosity aperture.
3) Check paste conditions such as dry paste
phenomenon by verifying if paste rolls or skids
along print direction.

Insufficient Solder 1) Too low solder paste volume 1) Increase the stencil thickness.
contact on E pad causes by stencil thickness 2) Fabricate Step stencil to step up the E pad
area for higher solder paste volume

1) Due to moisture trap inside the 1) Make sure the package is properly kept
“Popcorn” Damage package after opening from MBB.
2) No proper baking of package 2) Bake the package as per J-STD-033 before
when the floor life exceed the assembly
requirement.

Table 5: Typical defects with causes and remedy

Typical Acceptance of Voiding:

Thermal pad : <50%

Figure25: Voiding acceptance criteria

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
15/20

7. MOUNTING OF EXPOSED PAD UP OPTION

The exposed pad up option of QFP packages is intended to further reduce the package-to-ambient thermal
resistance (< 5°C/W) by coupling the exposed pad with an external heatsink. Depending on the system
design, the mechanical joint between package heatsink and PCB can be achieved through the use of clips
or screws. The tolerances for all the dimensions related to the package height, the heat sink and their
surface planarity must be properly controlled to minimize the stress coming from the coupling package-
heatsink: excessive contact force, vibrations and thermal excursions can generate undesirable mechanical
stress which can damage the package leads or the integrity of the contact between the slug and heat sink.

The “zero stand-off” approach has been applied in all the pad up packages to minimize the stress on solder
joint when applying the external heat-sink: for pad down configuration the stand-off is fully positive, i.e.
lead tips are lower than bottom package in a range of 50 to 150 μm, for pad up option the stand-off is
across zero, typically ranging from – 40 μm to +40 μm.

In such a condition the package body can come in contact with the PCB after heatsink mounting thus
reducing the level of stress applied to the solder joints though the leads.
The thermal and mechanical efficiency can be further enhanced by placing a thermal interface material
(TIM) like grease or thermal conductive tape in between the package and the external heat sink:

A basic package characterization of induced mechanical stresses when applying the external heat sink is
done through a dedicated torque test; it is intended to characterize the package mechanical integrity while
simulating the mounting by screws onto an external heatsink.

The maximum allowable value out of torque test must be verified/confirmed by the Customer in the actual
application system and mounting conditions.

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
16/20

8. BOARD LEVEL RELIABILITY

STMicroelectronics has evaluated several QFP for board mounting and Solder Joints Reliability, especially
versus thermal cycling with good performance; thanks to the spring effect of gull wing leads peripheral
connection. See example in figure 26 to 31 for eLQFP 24x24-176 with 0.5mm pitch:

ReliaSoft Weibull++ 7 - www.ReliaSoft.com

Probability - Weibull(TCOB for eLQFP176-24x24x1.4_0.5p)
99.000
Probability-Weibull

-40/+125, 1cph
Weibull-2P
90.000 RRX SRM MED FM
F=13/S=107
Data Points
Probability Line

-40/+125, 2cph
Weibull-2P
RRX SRM MED FM
F=16/S=20
50.000 Data Points
Probability Line
Unreliability, F(t)

10.000
Figure 27: Example of Good Wetting
5.000

STMicroelectronics
10/8/2013
1.000 9:48:28 AM
100.000 1000.000 10000.000 20000.000
Number of Thermal Cycles to Failure (cycles)
-40/+125, 1cph: β=8.7106, η=6583.0069, ρ=0.9262
-40/+125, 2cph: β=6.5877, η=1.1968Ε+4, ρ=0.9232

Figure 26: Thermal cycling for QFP (JESD22-A104E) Figure 28: Failure Analysis after TCoB

ReliaSoft Weibull++ 7 - www.ReliaSoft.com

Probability - Weibull (JEDEC Drop Test for eLQFP176-24x24x1.4_0.5p)

99.000
Probability-Weibull
CB@90% 2-Sided [T]

90.000
1500G/0.5ms
Weibull-2P
RRX SRM MED FM
F=10/S=0
Data Points
Probability Line
Top CB-I
50.000
Bottom CB-I
Unreliability, F(t)

10.000

5.000 Figure 30: Failure Analysis after DT

STMicroelectronics
11/27/2012
1.000 9:21:52 AM
1.000 10.000 100.000
Number of Drops to Failure (drops)

β=7.0998, η=40.9656, ρ=0.9643

Figure 29: Drop Test for QFP (JESD22-B111) Figure 31: Crack in lead-shoulder

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
17/20

9. REWORK GUIDELINES

9.1 Reworking QFP solder shorts

Fig 32: QFP leads solder short

a) To remove solder shorts, a soldering iron, solder wire, solder wick & liquid flux is needed.
b) Apply adequate amount of flux on the defective joint.
c) Heat up the defective joint with soldering iron and solder wick to remove the solder short as show
in Fig. 33

Fig. 33: removing of solder short

d) Apply flux on the joint and solder the joint again with new solder. Make sure the joint is well solder
with reference to IPC 610 standard.
e) Clean up the rework area with IPA to remove flux residue.

9.2 Removal of QFP from PCB

When there is a need to remove a defective QFP from PCB and replace with a good unit, special care must
be taken into consideration.

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
18/20

9.2.1 Package w/o E Pad

a) Cover up the surrounding package with respect to the defective unit with high temperature tape,
such as Teflon tape to protect the package from damage during heating.
b) Heat up the defective QFP with a hot air gun by moving in a circular motion around the
circumference of the QFP or a rework machine.
c) When the joint of the leads has melted, lift up and remove the QFP with a tweezers.
As for rework machine, the package will be lifted up by a vacuum nozzle.
d) Remove old solder on the PCB QFP pads with solder iron & solder wick.
e) Clean up the QFP location with IPA to remove flux residue.
f) Manual align the QFP leads to the PCB pad.
g) Once align, solder the 4 corner of the leads to temporary secure the package to the PCB.
h) Solder all the leads with a solder iron and solder wire.
i) Clean up the area with IPA to remove flux residue.

9.2.2 Package with E-Pad

a) Cover up the surrounding package with respect to the defective unit with high temperature tape,
such as Teflon tape to protect the package from damage during heating.
b) Heat up the defective QFP with a hot air gun by moving in a circular motion around the
circumference of the QFP or a rework machine.
c) When the joint of the leads has melted, lift up and remove the QFP with a tweezers.
As for rework machine, the package will be lifted up by a vacuum nozzle.
d) Remove old solder on the PCB QFP pads with solder iron & solder wick.
e) Clean up the QFP location with IPA to remove flux residue.
f) Manual print solder paste on the PCB leads & E pad using a mini rework stencil.
g) Once solder paste is deposited, place the PCB on the rework station and align the new QFP package
to the PCB QFP pad.
h) Solder the package according to the rework station instruction.
i) After solder, clean up the QFP area with IPA to remove flux residue.
j) Proceed to X ray machine to check for E pad solder condition and make sure the E pad has full
contact between E pad and PCB pad.

Figure 34: Typical QFP Mini Rework Stencil Figure 35: Example of Repair Station

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
19/20

10. HANDLING

10.1 Handling ESD Package

Integrated Circuit and components are ESD sensitive, so proper precaution are required for handling
and the way to process them during assembly. Electrostatic Discharge will cause damage and failure to
the package. So it is advisable to have proper ESD control during the handling process. Industry standard
requirements for proper handling of ESD controls can be based on IPC JEDS625-B

10.2 Handling Moisture Sensitive Package

QFP are moisture and reflow sensitive and proper handling are require for handling, packing and in the
SMT assembly. Improper handling could cause quality and reliability concerns during the solder reflow
process. Assembly process in SMT expose the package to a temperature higher than 200oC in the reflow
process. With such a rapid change of temperature, the package material could cause cracking or
delamination and this will lead to failure and reliability issue in the field.

Moisture sensitive SMD is pack in tape & Reel or JEDEC tray and vacuum seal in MBB (Moisture Barrier Bag
for proper storage and transportation. It is seal with desiccant material & HIC (Humid Indicator Card). The
shelf life is 12 months from the date the package is packed.

After opening the MBB for assembly, the package should be handle and store according to J-STD-033
standard. After opening the package must be mounted within the floor life as specific by MSL. Improper
use and storage could lead to quality and reliabilities risk.

Baking is required before assembly if the following condition occurs:-

a) Package is exposed to floor life more than specific requirements
b) Humidity Indicator Card show more than the specific percent level
c) Package are store according to J-STD-033 standard

The baking procedure can be found in J-STD-033.

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
 DM00501826 2.0 CONTROLLED DOCUMENT ACTIVE 09-May-2018 PAGE {pN_1}
20/20

11. REFERENCES

a) IPC-7351, “Generic Requirements for Surface Mount Design and Land Pattern Standard”, February 2005
b) IPC-A-610G, “Requirements for Soldered Electrical and Electronic Assemblies”, Nov 2017
c) JEDEC J-STD-033D, “Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices”,
January 2007
d) JEDEC 625-B “Requirements for Handling Electrostatic-Discharge Sensitive (ESDS) Devices”.
e) IPC 7351, “Generic Requirements for Surface Mount Design and Land Pattern Standard”, June 2010
f) IPC SM-782A, “Surface Mount Design and Land Pattern Standard”, Aug 1993
g) IPC 7525, “ Stencil Design Guidelines”, Feb 2007
h) JEP95, “ JEDEC Solid State Products Outline”, Jan 2001
i) JESD 22A104E, JEDEC Standard Thermal Cycling, Oct 2014
j) JESD 22B111, JEDEC Standard Board Level Drop Test, July 2003

12. ABBREVIATIONS

CTE Coefficient of Thermal Expansion OSP Organic Solvent Protectant

ENIG Electroless Nickel Immersion Gold PCB Printed Circuit Board
IMC Intermetallic Compound QFP Quad Flat Package
MSL Moisture Sensitivity Level SMD Solder Mask Defined
NSMD Non Solder Mask Defined
Package T : Thin = 1.00mm
Thickness L : Low =1.40mm
Classification P: Plastic =>2.00mm

13. REVISION HISTORY

Revision Date Description of Change

1-a 30th Apr 2018 Initial version
1-b 7th May 2018 Amends and adding in of reference
documents

14. DISCLAIMER

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2014 STMicroelectronics – All rights reserved

Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited

NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.