Answers to Questions and Problems in

Memory Devices

1 1. What types of connections are common

to all memory devices?
Answer: Common connections include:

• Address inputs for selecting memory locations.

• Data inputs and outputs for data transfer.

• Control inputs (like Chip Enable (CE), Output Enable (OE), Write
Enable (WE)) to manage read/write operations.

• Power supply pins to provide necessary voltage.

2 2. List the number of words found in each

memory device for the following numbers
of address connections:
1. (a) 8: 28 = 256 words

2. (b) 11: 211 = 2048 words

3. (c) 12: 212 = 4096 words

4. (d) 13: 213 = 8192 words

5. (e) 20: 220 = 1048576 words

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3 3. List the number of data items stored in
each of the following memory devices and
the number of bits in each datum:
1. (a) 2K × 4: 2048 data items, each 4 bits

2. (b) 1K × 1: 1024 data items, each 1 bit

3. (c) 4K × 8: 4096 data items, each 8 bits

4. (d) 16K × 1: 16384 data items, each 1 bit

5. (e) 64K × 4: 65536 data items, each 4 bits

4 4. What is the purpose of the CE pin on a

memory component?
Answer: The Chip Enable (CE) pin activates the memory device for read
or write operations. When CE is low (active), the memory device is enabled
and responds to address inputs.

5 5. What is the purpose of the OE pin on a

memory device?
Answer: The Output Enable (OE) pin controls the data output buffers.
When OE is low, data stored in memory can be read out; when OE is high, the
outputs are in a high-impedance state, preventing data from being output.

6 6. What is the purpose of the WE pin on

a SRAM?
Answer: The Write Enable (WE) pin determines whether the data on the
data inputs should be written into the SRAM. When WE is low, data is
written into the memory location specified by the address lines.

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7 7. How many bytes of storage do the fol-
lowing EPROM memory devices contain?
1. (a) 2708: 1 KB = 1024 bytes

2. (b) 2716: 2 KB = 2048 bytes

3. (c) 2732: 4 KB = 4096 bytes

4. (d) 2764: 8 KB = 8192 bytes

5. (e) 27512: 64 KB = 65536 bytes

8 8. Why won’t a 450 ns EPROM work di-

rectly with a 5 MHz 8088?
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Answer: The 5 MHz 8088 operates with a clock period of 5 MHz = 200 ns.
A 450 ns EPROM has a longer access time than the clock period, meaning it
cannot provide data fast enough for the CPU, leading to data access errors.

9 9. What can be stated about the amount of

time needed to erase and write a location
in a flash memory device?
Answer: Erasing a location in flash memory typically takes longer than
writing to a location. Writing can often be completed in microseconds, while
erasing can take milliseconds because entire blocks of memory must be erased
before new data can be written.

10 10. SRAM is an acronym for what type

of device?
Answer: SRAM stands for Static Random-Access Memory.

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11 11. The 4016 memory has a CE pin, an
OE pin, and a WE pin. What are these
pins used for in this RAM?
Answer:

• CE (Chip Enable) pin: Activates the RAM for reading or writing.

• OE (Output Enable) pin: Controls the data output; data is available

when OE is low.

• WE (Write Enable) pin: Controls whether data on the data inputs is

written to memory; data is written when WE is low.

12 12. How much memory access time is re-

quired by the slowest 4016?
Answer: The access time for the slowest 4016 SRAM is typically around 70
ns.

13 13. DRAM is an acronym for what type

of device?
Answer: DRAM stands for Dynamic Random-Access Memory.

14 14. The 256M DIMM has 28 address in-

puts, yet it is a 256M DRAM. Explain
how a 28-bit memory address is forced
into 14 address inputs.
Answer: The 256M DIMM uses a technique called bank addressing. It has
multiple banks of memory, and each bank is addressed using fewer address
lines. For example, 14 address inputs can select which bank is active, and

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the remaining address lines are used to access the specific memory locations
within that bank.

15 15. What are the purposes of the RAS

and CAS inputs of a DRAM?
Answer:

• RAS (Row Address Strobe): Activates the row in the DRAM array. It
is used to latch the row address.

• CAS (Column Address Strobe): Activates the column in the DRAM

array. It is used to latch the column address for reading or writing
data.

16 16. How much time is required to refresh

the typical DRAM?
Answer: Typically, refreshing DRAM requires around 60 µs to 200 µs per
row, depending on the specific DRAM technology used.

17 17. Why are memory address decoders

important?
Answer: Memory address decoders are crucial because they enable specific
memory locations to be accessed without conflicts. They translate the ad-
dress inputs from the CPU into select signals for specific memory devices,
ensuring that only the intended device responds to the address.

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18 18. Modify the NAND gate decoder of
Figure 10–13 to select the memory for ad-
dress range DF800H–DFFFFH.
Answer: To select this address range, you need to ensure that the NAND
gate inputs correspond to the upper bits of the address. Modify the inputs so
that they enable the range DF800H to DFFFFH based on the address lines
relevant to this range.

19 19. Modify the NAND gate decoder in

Figure 10–13 to select the memory for ad-
dress range 40000H–407FFH.
Answer: You will need to configure the NAND gates to respond to the
specific upper address bits that define the range 40000H to 407FFH, ensuring
the address lines are appropriately connected to select this range.

20 20. When the G1 input is high and both

G2A and G2B are low, what happens to
the outputs of the 74HCT138 3-to-8 line
decoder?
Answer: When G1 is high and both G2A and G2B are low, the decoder
is enabled, and the outputs will correspond to the selected address lines.
Specifically, one of the outputs will go low based on the input address, while
the others will remain high.

21 21. Modify the circuit of Figure 10–15 to

address memory range 70000H–7FFFFH.
Answer: To address this memory range, the address lines need to be config-
ured to enable the appropriate upper address bits corresponding to 70000H

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to 7FFFFH. Adjust the connections to the decoder to reflect these address
requirements.

22 22. Modify the circuit of Figure 10–15 to

address memory range 40000H–4FFFFH.
Answer: Similar to the previous question, adjust the address inputs of
the decoder to select the appropriate upper bits corresponding to the range
40000H to 4FFFFH.

23 23. Describe the 74LS139 decoder.

Answer: The 74LS139 is a dual 2-to-4 line decoder/demultiplexer. It has
two enable inputs and provides four outputs for each decoder. It converts the
binary inputs into a one-hot output format, allowing for address decoding in
memory systems.

24 24. What is VHDL?

Answer: VHDL (VHSIC Hardware Description Language) is a hardware
description language used to model and design electronic systems. It allows
designers to describe the structure and behavior of digital circuits at a high
level.

25 25. What are the five major keywords in

VHDL for the five major logic functions
(AND, OR, NAND, NOR, and invert)?
Answer: The five major keywords in VHDL are:

• AND

• OR

• NAND

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 • NOR

• NOT (for invert)

26 26. Equations are placed in what major

block of a VHDL program?
Answer: Equations are typically placed in the architecture block of a
VHDL program.

27 27. Modify the circuit of Figure 10–19

by rewriting the PLD program to address
memory at locations A0000H–BFFFFH for
the ROM.
Answer: Adjust the logic in the PLD program to ensure the outputs are
driven low for the address range A0000H to BFFFFH, using the appropriate
address lines to configure the selection logic.

28 28. The minimum mode control signals

are replaced by what two control signals
in the 8086 maximum mode?
Answer: In maximum mode, the minimum mode control signals are replaced
by QS1 (Queue Status) and QS0 (Queue Status) signals.

29 29. Modify the circuit of Figure 10–20 to

select memory at location 60000H–77FFFH.
Answer: Adjust the logic inputs to the decoder so that it selects the appro-
priate range corresponding to the address lines for 60000H to 77FFFH.

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30 30. Modify the circuit of Figure 10–20 to
select eight 27256 32K × 8 EPROMs at
memory locations 40000H–7FFFFH.
Answer: Connect the outputs of the decoder to enable each EPROM based
on the address lines, ensuring that the first 32K of each EPROM corresponds
to the specified memory range.

31 31. Add another decoder to the circuit of

Figure 10–21 so that an additional eight
62256 SRAMs are added at locations C0000H–FFFFH.
Answer: Add a second decoder that takes the upper address lines corre-
sponding to C0000H to FFFFFH and connects its outputs to enable the
62256 SRAMs.

32 32. The 74LS636 error-correction and de-

tection circuit stores a check code with
each byte of data. How many bits are
stored for the check code?
Answer: The 74LS636 stores 4 bits of check code with each byte of data for
error correction.

33 33. What is the purpose of the SEF pin

on the 74LS636?
Answer: The SEF (Self-Error Flag) pin indicates whether an error has
been detected in the data stored in memory, allowing the system to respond
appropriately.

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34 34. The 74LS636 will correct
b itsthatareinerror.

Answer: The 74LS636 can correct one bit that is in error.

35 35. Outline the major difference between

the buses of the 8086 and 8088 micropro-
cessors.
Answer: The major difference is that the 8086 has a 16-bit data bus, while
the 8088 has an 8-bit data bus. This means the 8086 can transfer more data
at once compared to the 8088.

36 36. What is the purpose of the AEN and

A0 pins on the 8086 microprocessor?
Answer:

• AEN (Address Enable): Indicates whether the address bus is active or

not.

• A0: This pin indicates whether the current data transfer is accessing
an odd or even byte in memory.

37 37. What is the ALE pin and what other

pin has it replaced?
Answer: The ALE (Address Latch Enable) pin signals when the address is
valid and is used to latch the address onto an external bus. It has replaced
the earlier AD (Address/Data) pins in some configurations.

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38 38. What two methods are used to select
the memory in the 8086 microprocessor?
Answer: The two methods used to select memory in the 8086 microprocessor
are:
• Address decoding using memory address decoders.
• Directly using the address bus lines to access specific memory locations.

39 39. If AEN is a logic 0, then the

m emorybankisselected.

Answer: If AEN is a logic 0, then the first memory bank is selected.

40 40. If A0 is a logic 0, then the

m emorybankisselected.

Answer: If A0 is a logic 0, then the even memory bank is selected.

41 41. Why don’t separate bank read (RD)

strobes need to be developed when inter-
facing memory to the 8086?
Answer: Separate bank read strobes are not needed because the 8086 mi-
croprocessor utilizes multiplexed address and data lines, allowing it to deter-
mine read operations based on the state of the address lines without needing
additional strobes.

42 42. Modify the circuit of Figure 10–30 so

that the RAM is located at memory range
30000H–4FFFFH.
Answer: Adjust the address decoding logic in the circuit to ensure that the
range from 30000H to 4FFFFH is properly selected by the address lines.

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43 43. Develop a 16-bit-wide memory inter-
face that contains SRAM memory at loca-
tions 200000H–21FFFFH for the 80386SX
microprocessor.
Answer: Design the interface with address lines to select the appropriate
range and configure the control signals to ensure proper read and write op-
erations to the SRAM.

44 44. Develop a 32-bit-wide memory inter-

face that contains EPROM memory at lo-
cations FFFF0000H–FFFFFFFFH.
Answer: Create an interface that utilizes 32-bit data buses and connects
the EPROM to the appropriate address lines to access the specified memory
range.

45 45. Develop a 64-bit-wide memory for the

Pentium–Core2 that contains EPROM at
locations FFF00000H–FFFFFFFFH and SRAM
at locations 00000000H–003FFFFFH.
Answer: Construct a memory interface capable of supporting both EPROM
and SRAM, ensuring that the address decoding properly allocates the two
memory types to their respective ranges.

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46 46. On the Internet, search for the largest
size EEPROM you can find. List its size
and manufacturer.
Answer: As of the latest search, the largest EEPROM available is from
Microchip Technology, with a size of 32 Mb (megabits). Please verify for
the most current data as availability may change.

47 47. What is a memory-mapped I/O cycle?

Answer: A memory-mapped I/O cycle uses the same address space for
both memory and I/O devices. This allows the CPU to read and write to
I/O devices using standard memory instructions.

48 48. Can a DRAM refresh be done while

other sections of the memory operate?
Answer: Yes, in modern DRAM systems, refresh operations can often occur
concurrently with read and write operations in other sections of memory,
minimizing performance impacts.

49 49. If a 1M × 1 DRAM requires 4 ms for a

refresh and has 256 rows to be refreshed,
no more than
o f timemustpassbef oreanotherrowisref reshed.

Answer: If 4 ms is required for a complete refresh of 256 rows, the maximum

time between refreshing each row is:
4 ms
≈ 15.625 s
256 rows
So, no more than 15.625 s must pass.

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50 50. How wide is the data bus in the Intel
Itanium?
Answer: The data bus in the Intel Itanium is 64 bits wide.

51 51. Scour the Internet to find the largest

DRAM currently available.
Answer: As of the latest search, the largest DRAM available is 64 GB
(gigabytes) from Samsung. Please verify for the most current data as avail-
ability may change.

52 52. Write a report on DDR memory.

Answer: DDR (Double Data Rate) memory allows data to be transferred
on both the rising and falling edges of the clock signal, effectively doubling
the data rate compared to traditional SDRAM. This technology enhances the
performance of computers and other devices by allowing faster data access
without increasing the clock speed. DDR has evolved through several gener-
ations (DDR2, DDR3, DDR4, and DDR5), each improving performance and
reducing power consumption.

53 53. Write a report that details RAMBUS

RAM. Try to determine why this technol-
ogy appears to have fallen by the wayside.
Answer: RAMBUS RAM was designed to provide high-speed memory ac-
cess by using a unique interface and bus architecture. It offered significantly
higher bandwidth compared to traditional SDRAM. However, the high cost,
proprietary nature, and latency issues led to its decline. As technologies like
DDR memory advanced, providing similar or better performance at lower
costs, RAMBUS lost market share. Legal disputes and the inability to adapt
to industry standards also contributed to its fall from favor.

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