RAiO

RA8877

Character/Graphic
TFT LCD Controller

Datasheet

Version 1.1
March 31, 2016

RAiO Technology Inc.

©Copyright RAiO Technology Inc., 2015, 2016

RAiO TECHNOLOGY INC. www.raio.com.tw

 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

1. Introduction
This is the Hardware Functional Specification for the RA8877 TFT LCD Controller. RA8877 supports LVDS
type interface (FPD-Link). Including in this document are system block diagrams, Pin information, AC/DC
characteristics, each block’s function description, detail register descriptions, and power mode control.

1.1 Overview Description

The RA8877 is a low power color LCD Controller with support for up to 512M-bits external SDRAM memory.
The RA8877 supports an 8/16-bit asynchronous parallel host bus while providing high performance
bandwidth into the external display memory allowing for fast screen updates. The RA8877 also provides
support for multiple display buffers, Picture-in-Picture, Opacity control, and display rotation/mirror … etc.

1.2 System Diagram & Chip Diagram

8/16 MPU Host I/F Key Pad I/F Button

Host
or SPI/I2C Host I/F
I2C
I2C master I/F
Device
RAiO
SDRAM 16-bits SDRAM
RA8877
LVDS Panel I/F Panel
Serial
Flash
SPI master I/F Back-
or PWM I/F
Light
GT Font

Figure 1-1 : System Diagram

PLLs

1.2V FIFO
LDO+POR

ISO8859 ROM

Text/Graphic
TFT LCD
Controller

LQFP-128

Figure 1-2 : Chip Diagram

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

2. Features
2.1 Frame Buffer
z Supported SDRAM density:16Mb, 32Mb, 64Mb, 128Mb, 256Mb or 512Mb
z Supported SDRAM configuration: x16
z 16-bit SDRAM bus, maximum frame buffer: 256MB/512MB

2.2 Host Interface

z Support 8080/6800 8/16-bit asynchronous parallel bus interface (MIPI DBI Type A)
„ Provide xnwait event to extend MPU cycle
z Support serial host Interface. Ex. IIC, 3/4-wire SPI
z Mirror and rotation functions are available for image data writes.

2.3 Display Input Data Formats

z 1bpp: monochrome data (1-bit/pixel)
z 8bpp: RGB 3:3:2 (1-byte/pixel)
z 16bpp: RGB 5:6:5 (2-byte/pixel)
z 24bpp: RGB 8:8:8 (3-byte/pixel or 4-byte/pixel)
„ Index 2:6 (64 index colors/pixel with opacity attribute)
„ αRGB 4:4:4:4 (4096 colors/pixel with opacity attribute)

2.4 Display Mode

z Always output 24bpp (RGB 8:8:8) on LVDS channel and support VESA/JEDIA format

2.5 Support Various Panel Resolution

z Embedded LVDS transmitter to support FPD-Link (LVDS interface type panel)
„ LVDS outputs meets or exceed the requirements of ANSI EIA/TIA-644 standard
z Support panel’s resolution up-to 2048 dots by 2048 dots. (*Note :The real panel resolution is based on
the limitations of pixel clock and color depth.)
„ QVGA: 320 x 240 x 16/18/24-bit LCD panel
„ WQVGA: 480 x 272 x 16/18/24-bit LCD panel
„ VGA: 640 x 480 x 16/18/24-bit LCD panel
„ WVGA: 800 x 480 x 16/18/24-bit LCD panel
„ SVGA: 800 x 600 x 16/18/24-bit LCD panel
„ QHD: 960 x 540 x 16/18/24-bit LCD panel
„ WSVGA: 1024 x 600 x 16/18/24-bit LCD panel
„ XGA: 1024 x 768 x 16/18/24-bit LCD panel
„ WXGA: 1280 x 768 x 16/18/24-bit LCD panel
„ WXGA: 1280 x 800 x 16/18/24-bit LCD panel
„ WXGA: 1366 x 768 x 16/18/24-bit LCD panel

2.6 Display Features

z Provide 4 User-defined 32x32 pixels Graphic Cursor
z Display Window
The display window is defined by the size of the LCD display. Complete or partial updates to the
display window are done through canvas image’s setting. The active window size and start position are
specified in 8 pixel resolution (horizontal) and 1 line resolution (vertical). Window coordinates are
referenced to top left corner of the display window (even when flip is enabled or rotate text, no host
side translation is required).

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

z Virtual display
Virtual display is available to show an image which is larger than LCD panel size. The image may scroll
easily in any direction.
z Picture-in-Picture (PIP) display
Two PIP windows are supported. Enabled PIP windows are always displayed on top of Main window.
The PIP windows sizes and start positions are specified in 4 pixel resolution (horizontal) and 1 line
resolution (vertical). Image scrolling can be performed by changing the start address of a PIP window.
The PIP1 window is always on top of PIP2 window.
z Multi Buffer
Multi buffering allows the main display window to be switched among buffers. The number of buffers
depends on the external SDRAM size and the desired size of the write buffers. Multi buffering allows a
simple animation display to be performed by switching the buffers.
z Wake-up display
Wake-up display is available to show the display data quickly which data is stored in SDRAM. This
feature is used when returning from the Standby mode or Suspend mode.
z Vertical Flip display
Vertical Flip display functions are available for image data reads. PIP window will be disabled if flip
display function enable.
z Color Bar Display
It could display color bar on panel and need not SDRAM. Default resolution is 640 dots by 480 dots

2.7 Initial Display

z Embed a tiny processor and use to show display data which stored in the serial flash and need not
external MPU participate. It will auto execute after power-on, until program execute complete then
handover control rights to external MPU. It supports 12 instructions. They are:
„ EXIT: Exit instruction (00h/FFh) -- one byte instruction
„ NOP: NOP instruction (AAh) -- one byte instruction
„ EN4B: Enter 4-Byte mode instruction (B7h) -- one byte instruction
„ EX4B: Exit 4-Byte mode instruction (E9h) -- one byte instruction
„ STSR: Status read instruction (10h) -- two bytes instruction
„ CMDW: Command write instruction (11h) -- two bytes instruction
„ DATR: Data read instruction (12h) -- two bytes instruction
„ DATW: Data write instruction (13h) -- two bytes instruction
„ REPT: Load repeat counter instruction (20h) -- two bytes instruction
„ ATTR: Fetch Attribute instruction (30h) -- two bytes instruction
„ JUMP: Jump instruction (80h) -- five bytes instruction
„ DJNZ: Decrement & Jump instruction (81h) -- five bytes instruction

2.8 Block Transfer Engine (BTE)

z 2D BitBLT Engine
z Copy with ROP & color expansion
z Solid fill & Pattern fill
„ Provide User-defined Patterns with 8x8 pixels or 16x16 pixels
z Opacity (Alpha-Blend) control
It allows two images to be blended to create a new image which can then be displayed using a PIP
window. The processing speed of Alpha-blend function varies depending on the image size. Optionally,
a single input image can be processed.
„ Chroma-keying function: Mixes images with applying the specified RGB color according to
transparency rate
„ Window Alpha-blending function: Mixes two images according to transparency rate in the specified
region (fade-in and fade-out functions are available).
„ Dot Alpha-blending function: Mixes images according to transparency rate when the target is a
graphics image in the RGB format.

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

2.9 Geometric Drawing Engine

z Draw dot, Line, Curve, Circle, Ellipse, Triangle, Square & Circular Square

2.10 SPI Master Interface

2.10.1 Text Features
z Embedded 8x16,12x24,16x32 Character Sets of ISO/IEC 8859-1/2/4/5.
z Supporting Genitop Inc. UNICODE/BIG5/GB etc. Serial Character ROM with 16x16/24x24/32X32 dots
Font Size. The supporting product numbers are GT21L16T1W, GT30L16U2W, GT30L24T3Y,
GT30L24M1Z, and GT30L32S4W, GT20L24F6Y, GT21L24S1W.
z User-defined Characters support half size (8x16/12x24/16x32) & full size
z Programmable Text Cursor for Writing with Character
z Character Enlargement Function X1, X2, X3, X4 for Horizontal/Vertical Direction
z Support Character 90 degree Rotation

2.10.2 DMA function

z Support direct data transfer from external serial flash to frame buffer

2.10.3 General SPI master

z Compatible with Motorola’s SPI specifications
z 16 bytes entries deep read FIFO
z 16 bytes entries deep write FIFO
z Interrupt generation after Tx FIFO empty and SPI Tx/Rx engine idle

2.11 IIC Interface

z IIC master interface
„ For the expand I/O device, external touch screen controller for panel control
„ Support Standard mode (100kbps) and Fast mode (400kbps)

2.12 PWM Timer

z Two 16-bit timers
z One 8-bit pre-scalars & One 4-bit divider
z Programmable duty control of output waveform (PWM)
z Auto reload mode or one-shot pulse mode
z Dead-zone generator

2.13 Key-scan Interface

z Support up-to 5x5 key matrix (share with the GPIO pin)
z Programmable scan period
z Support long Key & repeat key
z Support up to 2 keys are pressed simultaneously
Note: Restricted support 3-keys are pressed simultaneously (3-keys cannot form 90°)
z Support Key-Scan Wakeup function

2.14 Power Saving

z Support 3 kind of power saving mode
„ Standby mode, Suspend mode & Sleep mode
z It may wakeup by host, key & external event

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

2.15 Clock Source

z Embedded programmable PLL for system core clock, LCD panel scan clock and the SDRAM clock
z Single crystal clock input: (XI/XO: 10-15MHz)
z Internal system clock (Maximum 120MHz)
z SDRAM clock (Maximum 166MHz)
z LCD panel scan clock (Maximum 100MHz)

2.16 Reset
z Accept external hardware reset to synchronize with system
z Software command reset

2.17 Power Supply

z I/O voltage: 3.3V +/- 0.3V
z Embedded 1.2V LDO for core power

2.18 Package
z LQFP-128
z Operation temperature: -40℃ ~ 85℃

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

3. Symbol and Package

3.1 RA8877 Symbol & Pin Assignment

Figure 3-1

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

3.2 Package Outline Dimensions

Figure 3-2 : RA8877 Package Outline Dimensions

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

4. Signal Description
4.1 Parallel Host Interface (25 signals)
Pin Name Dir/Drv. Pin Description
Data Bus
These are data bus for data transfer between parallel host and RA8877.
IO XDB[15:8] will become GPIO (GPIO-A[7:0]) if parallel host 8080/6800 16-bits
XDB[15:0]
(8mA) data bus mode doesn’t set.
XDB[7:0] are multiplex with serial host signals if serial host mode set. Please
refer to serial host interface section.
Command / Data Select Input
XA0 I The pin is used to select command/data cycle.
XA0 = 0, status read / command write cycle is selected.
XA0 = 1, data read / Write cycle is selected.
Chip Select Input
XnCS I Low active chip select pin.
If host I/F set as serial host mode then this pin can be read from GPI-B0.
With internal pull-high with resistor.
Enable/Read Enable
When MPU interface (I/F) is 8080 series, this pin is used as XnRD signal
XnRD (Data Read), active low.
I When MPU I/F is 6800 series, this pin is used as XEN signal (Enable), active
(XEN)
high.
If host I/F set as serial host mode then this pin can be read from GPI-B1.
With internal pull-high with resistor.
Write/Read-Write
When MPU I/F is 8080 series, this pin is used as XnWR signal (data write) ,
XnWR active low.
I When MPU I/F is 6800 series, this pin is used as XRnW signal (data
(XRnW)
read/write control). Active high for read and active low for write.
If host I/F set as serial host mode then this pin can be read from GPI-B2.
With internal pull-high with resistor.
O Interrupt Signal Output
XnINTR
(8mA) The interrupt output for host to indicate the status.
Wait Signal Output
O
XnWAIT
(8mA) When high, it indicates that the RA8877 is ready to transfer data. When low,
then microprocessor is in wait state.
Parallel /Serial Host I/F Select
00X: (parallel host) 8080 interface with 8/16-bits data bus
01X: (parallel host) 6800 interface with 8/16-bits data bus
100: (serial host) 3-Wire SPI
XPS[2:0] I 101: (serial host) 4-Wire SPI
11x: (serial host) IIC
Note:
If host I/F set as parallel host mode, then XPS[0] pin is external interrupt pin.

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

4.2 Serial Host Interface (Multiplex with Parallel Host Interface)

Pin Name Dir/Drv. Pin Description
XSSCL SPI or IIC Clock
I
(XDB[7]) XSSCL, 3-wire, 4-wire Serial or IIC I/F clock.
XSSDI IIC data /4-wire SPI Data Input
XSSDA I 3-wire SPI I/F: NC, please connect it to GND.
(XDB[6]) 4-wire SPI I/F: XSSDI, Data input for serial I/F.
IIC I/F: XSSDA, Bi-direction data for serial I/F
XSSD 3-wire SPI Data /4-wire SPI Data Output/IIC Slave Address Select
XSSDO IO 3-wire SPI I/F: XSSD, Bi-direction data for serial I/F
(XDB[5]) 4-wire SPI I/F: XSSDO, Data output for serial I/F.
IIC I/F: XIICA[5], IIC device address bit [5].
XnSCS SPI Chip Select/IIC Slave Address Select
I XnSCS, Chip select pin for 3-wire or 4-wire serial I/F.
(XDB[4])
IIC I/F : XIICA[4], IIC device address bit [4].
IIC I/F: IIC Slave Address Select.
XIICA[3:0]
I XIICA[3:0], 3|4-wire SPI I/F: NC, please connect it to GND.
(XDB[3:0])
IIC I/F : IIC device address bit [3:0]

4.3 SDR SDRAM Interface (39 signals)

Pin Name Dir/Drv. Pin Description
Clock enable / Clock 2 input (memory clock)
XMCKE IO
When XTEST[0] set low, this pin is SDR memory clock enable
(XCLK2) (8mA)
When XTEST[0] set high, this pin is external clock 2 input for SDR access.
IO SDR memory Clock out
XMCLK
(8mA) It derives from MPLL or XCLK2
O
XnMCS
(4mA) Chip select
O Command outputs: XnMRAS, XnMCAS and XnMWR (along with XnMCS)
XnMRAS
(4mA) define the command being entered
O
XnMCAS
(4mA) Command outputs
O
XnMWR
(4mA) Command outputs
O
XMBA[1:0]
(4mA) Bank address
O
XMA[12:0]
(4mA) Address
I/O
XMD[15:0]
(4mA) Data bus.
O
XMDQM[1:0]
(4mA) Input/Output mask

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

4.4 Serial Flash or SPI master Interface (5 signals)

Pin Name Dir/Drv. Pin Description
Chip Select 0 for External Serial Flash/ROM or SPI device
IO SPI Chip select pin #0 for serial Flash/ROM or SPI device.
XnSFCS0
(8mA) * If SPI master I/F is disabled then it can be programmed as GPIO (GPIO-C3);
default is GPIO-C3 input function.
Chip Select 1 for External Serial Flash/ROM or SPI device
IO SPI Chip select pin #1 for serial Flash/ROM or SPI device.
XnSFCS1
(8mA) * If SPI master I/F is disabled then it can be programmed as GPIO (GPIO-C4);
default is GPIO-C4 input function.
*auto pull-high in reset period if xtest[2:1] is not equal to 01b..
SPI Serial Clock
IO Serial clock output for serial Flash/ROM or SPI device.
XSCK
(8mA) * If SPI master I/F is disabled then it can be programmed as GPIO
(GPIO-C0); default is GPIO-C0 input function.
Master Output Slave Input
Single mode: Data input of serial Flash/ROM or SPI device. For RA8877, it is
output.
XMOSI IO
Dual mode: The signal is used as bi-direction data #0(SIO0). Only valid in
(XSIO0) (8mA)
serial flash DMA mode.
* If SPI master I/F is disabled then it can be programmed as GPIO
(GPIO-C1); default is GPIO-C1 input function.
Master Input Slave Output
Single mode: Data output of serial Flash/ROM or SPI device. For RA8877, it is
input.
XMISO IO
Dual mode: The signal is used as bi-direction data #1(SIO1). Only valid in
(XSIO1) (8mA)
serial flash DMA mode.
* If SPI master I/F is disabled then it can be programmed as GPIO
(GPIO-C2); default is GPIO-C2 input function.

4.5 PWM Interface (2 signals)

Pin Name Dir/Drv. Pin Description
PWM signal output 1 / Initial Display Enable
Pull-high this pin will enable Initial Display function.
This pin has internal pull-down in reset period to disable Initial Display function
IO
XPWM0 by default. i.e. after reset complete, internal pull-down resistor will be disabled.
(8mA)
XPWM 0 output mode is decided by configuration register.
If PWM function disabled then it can be programmed as GPIO (GPIO-C7),
default is GPIO-C7 input function, or output core clock.
PWM signal output 2 / Clock 3 input (panel scan clock)
When XTEST[0] set low:
XPWM1 IO XPWM1 set as output mode & output function is decided by configuration
(XCLK3) (8mA) register. It may normal XPWM1 function, oscillator clock output or error flag
for Scan bandwidth insufficient or Memory access out of range.
When XTEST[0] set high:
XPWM1 pin is external panel scan clock input

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 RA8877
Brief Datasheet Character/Graphic TFT LCD Controller

4.6 KEYSCAN Interface (9 signals)

Pin Name Dir/Drv. Pin Description
Keypad Data Line or GPIs (General Purpose Input)
XKIN[0]/ IO
Keypad data inputs (Default), with internal pull-up resister.
XSCL (8mA)
XKIN[0] also has IIC master’s XSCL function.
Keypad Strobe Line or GPOs (General Purpose Output)
XKOUT[0]/ O
Keypad matrix strobe lines outputs with open-drain. (Default).
XSDA (8mA)
XKOUT[0] also has IIC master’s XSDA function.
XKIN[4:1] I Keypad Data Line or GPIs (General Purpose Input)
Keypad data inputs (Default), with internal pull-up resister.
O Keypad Strobe Line or GPOs (General Purpose Output)
XKOUT[3:1]
(8mA) Keypad matrix strobe lines outputs with open-drain. (Default).

4.7 LCD Panel LVDS Interface/FPD-Link (12 signals)

Pin Name Dir/Drv. Pin Description
AVDD33 P Analog positive voltage power supply
AVSSIO P Analog ground
XTX0P A Transmit positive terminal. LVDS signals. Channel 0
XTX0N A Transmit negative terminal. LVDS signals. Channel 0
XTX1P A Transmit positive terminal. LVDS signals. Channel 1
XTX1N A Transmit negative terminal. LVDS signals. Channel 1
XTX2P A Transmit positive terminal. LVDS signals. Channel 2
XTX2N A Transmit negative terminal. LVDS signals. Channel 2
XTX3P A Transmit positive terminal. LVDS signals. Channel 3
XTX3N A Transmit negative terminal. LVDS signals. Channel 3
XCKP A Output TX clock. Positive terminal. LVDS levels
XCKN A Output TX clock. Negative terminal. LVDS levels

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Brief Datasheet Character/Graphic TFT LCD Controller

4.8 Clock, Reset & Test Mode (6 signals)

Pin Name Dir/Drv. Pin Description
Crystal Input Pin / Clock 1 input (core clock)
Crystal Oscillator range is 10MHz ~ 15MHz.
XI
I When XTEST[0] set low, this input pin for internal crystal circuit. It should be
(XCLK1) connected to external crystal circuit. That will generate the clock for RA8877.
When XTEST[0] set high, this pin is external clock 1 input.
Suggested OSC frequency is 11.0592MHz.
Crystal Output Pin
XO O This is an output pin for internal crystal circuit. It should be connected to
external crystal circuit.
Reset Signal input
XnRST I/OC To avoid noise interfere XnRST signal and cause fake reset behavior, external
XnRST level will be admitted only if it keep its signal level at least 256 OSC
clocks.
Clock Test Mode
Internal pull down.
XTEST[0] I For chip test function, should be connected to GND for normal operation.
0: Normal mode, Use internal PLL clock.
1: bypass internal PLL clock and instead them with CLK1I, CLK2I & CLK3I.
Chip Test Mode
XTEST[2:1] I 00: normal mode
01: Force SPI master I/F pin floating (for in-system-programming)
1X: RESERVED

4.9 Power and Ground

Pin Name Dir/Drv. Pin Description
LDO1_CAP12
LDO2_CAP12 P Loading Capacitor for each LDO
LDO3_CAP12 Connect a 1uF capacitor to ground.

VDD33 P IO VDD
3.3V IO power input.
VSS P GND
IO Cell/Core ground signal
AVSSIO P Analog IO GND
Analog IO ground signal
AVSS P Analog IO GND
Analog Core ground signal

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