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DD Lab 10 Zobiya

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DD Lab 10 Zobiya

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EXPERIMENT-10

Counters

7493-Binary Counter

4 bit binary Up-Down Counter


Name & ID:……………………………………Date: ……………………….

Run 1 Up/ Down Counter:

Write Verilog code for 4-bit synchronous UP/DOWN counter and implement it on DE10
Lite Board.

Verilog code
Name & ID:……………………………………Date: ……………………….

Truth Table
Name & ID:……………………………………Date: ……………………….

OUTPUT

Run 2 Even Counter:

Write Verilog code for even counter and implement it on DE10 Lite Board.

Verilog code

Truth Table
Name & ID:……………………………………Date: ……………………….

OUTPUT

Assignment All assignments are to be submitted strictly before start of next lab session
through online only. Late assignments will not be entertained and will be awarded ‘0’
marks.
1. Below is the code for counter which counts first 5 values mod-3 values. Write the
testbench for the same and show the proper output waveforms and understand
the code.

module countseq (input clk, rst, output reg [2:0] modfive, output [1:0] cnt);
wire s1;
wire [2:0] b1, b2;
wire [1:0] b3, b4;
assign s1 = (modfive ==5);
assign b1 = modfive +1;
Name & ID:……………………………………Date: ……………………….

assign b2 = s1 ? 1 : b1;
always @ ( posedge clk, posedge rst) begin
if (rst)
modfive <= 1;
else modfive <= b2;
end

Ans: Link1 https://www.edaplayground.com/x/Saew

Verilog Code (Screenshot)-

EDA Playground waveform (Screenshot)—

2. Write Verilog code and testbench for 4-bit ring counter.


Ans: Link2 https://www.edaplayground.com/x/rsDy

Verilog Code (Screenshot)-

EDA Playground waveform (Screenshot)—

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