COMPUTER ARCHITECTURE

UNIT-II

Combinational Circuits: Half and full Adder Subtractor, Decoders, Multiplexer, Demultiplexer
Sequential Circuits: Flip-Flops- CLK SR Flip- Flop, D Flip-Flop, J-K Flip Flop, T Flip-Flop.
Register: 4-bit shift register (SISO) Binary Counter- 4-bit synchronous and Asynchronous binary counter.

COMBINATIONAL LOGIC CIRCUITS

Combinational circuit is a circuit in which we combine the different gates in the circuit, for example
encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits
are following −
• The output of combinational circuit at any instant of time, depends only on the levels present at input
terminals.
• The combinational circuit do not use any memory. The previous state of input does not have any effect
on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m number of outputs

BINARY ADDER:
 HALF ADDER
 FULL ADDER

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WORKING OF HALF ADDER:

WHEN INPUTS ARE:
 A=0, B=0 THEN ; 0+0 THEN SUM=0 & CARRY=0
 A=0, B=1 THEN ; 0+1 THEN SUM=1 & CARRY=0
 A=1, B=0 THEN ; 1+0 THEN SUM=1 & CARRY=0
 A=1, B=1 THEN ; 1+1 THEN SUM=0 & CARRY=1
 The carry output is 0 unless both the inputs are 1.
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 Sum is obtained through two input Ex-Or gate and Carry is obtained through two input AND gate.

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FULL ADDER EX:

 Consider an ex: A=1, B=0, Cin=1

EXPRESSIONS FOR SUM AND CARRY

 SUM S=A’.B’.Cin+ A’.B.Cin’+ A.B’.Cin’+ A.B.Cin

 CARRY Cout= A’.B.Cin+ A.B’.Cin+ A.B.Cin’+ A.B.Cin

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BINARY SUBTRACTOR:

 HALF SUBTRACTOR
 FULL SUBTRACTOR

HALF SUBTRACTOR

 The half subtractor is also a building block for subtracting two binary numbers. It has two inputs and
two outputs. This circuit is used to subtract two single bit binary numbers A and B. The 'diff'
and 'borrow' are two output states of the half subtractor.
• A' and 'B' are the input variables whose values are going to be subtracted.
• The 'Diff' and 'Borrow' are the variables whose values define the subtraction result, i.e., difference and
borrow.
• The first two rows and the last row, the difference is 1, but the 'Borrow' variable is 0.
• The third row is different from the remaining one. When we subtract the bit 1 from the bit 0, the borrow
bit is produced.

WORKING OF HALF SUBTRACTOR:

 WHEN INPUTS ARE:
 A=0, B=0 THEN ; 0-0 THEN DIFFERENCE=0 & BORROW=0
 A=0, B=1 THEN ; 0-1 THEN DIFFERENCE = 1& BORROW =1
 A=1, B=0 THEN ; 1-0 THEN DIFFERENCE =1 & BORROW =0
 A=1, B=1 THEN ; 1-1 THEN DIFFERENCE =0 & BORROW =0
 The BORROW output is 0 unless both the inputs are A=0 & B=1.
 DIFFERENCE is obtained through two input Ex-Or gate and BORROW is obtained through two input
AND gate.

FULL SUBTRACTOR
 A full subtractor is a combinational circuit that performs subtraction of two bits, one is minuend and
other is subtrahend, taking into account borrow of the previous adjacent lower minuend bit. This
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circuit has three inputs and two outputs. The three inputs A, B and Bin, denote the minuend,
subtrahend, and previous borrow, respectively. The two outputs, D and Bout represent the difference
and output borrow, respectively.

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LOGIC CIRCUIT OF FULL SUBTRACTOR

FULL SUBTRACTOR EX:

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DECODERS

• A decoder is a combinational logic circuit that converts a N-bit binary code into M output lines such that
only one output line is activated for each one of the possible combinations of inputs.
• In other words, we can say that a decoder identifies or recognizes or detects a particular code. § In its
general form, a decoder has N input lines to handle N bits and form one to 2N output lines to indicate
the presence of one or more N-bit combinations. Since each of N inputs can be a 0 or a 1, there are 2 N
possible input combinations or codes.
• For each of these input combinations, only one of the M outputs will be active (HIGH), all other
outputs will remain inactive (LOW). Some decoders are designed to produce active LOW output, while
all other outputs remain HIGH.
• Some decoders do not utilize all of the 2N possible input codes. For example, a BCD to decimal decoder
has a 4-bit input code and 10 output lines that correspond to the 10 BCD code groups 0000 through
1001. Decoders of this type are often designed so that if any of the unused codes are applied to the input,
none of the outputs will be activated.
• A binary decoder is usually implemented as either a stand-alone integrated circuit (IC) or as part of a
more complex IC. Widely used decoders are often available in the form of standardized ICs.

2:4 DECODER

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• The truth table of a 2:4 decoder is shown below in which four input combinations 00, 10, 01 and 11 on
the select lines produce the respective outputs. That means when S1=0 and S0 =0, the output at Y 0=0,
similarly Y1=0 if the select inputs S1=0 and S0= 1 and so on.
From the above truth table, we can write the output expressions as
• If S1=0 and S0=0, then Y0=0
• If S1= 0 and S0=1, then Y1=0
• If S1=1 and S0=0, then Y2=0
• If S1=1 and S0=1, then Y3=0
•
INPUTS OUTPUTS
EN S1 S0 Y3 Y2 Y1 Y0

0 X X 1 1 1 1

1 0 0 1 1 1 0

1 0 1 1 1 0 1

1 1 0 1 0 1 1

1 1 1 0 1 1 1

LOGIC DIAGRAM OF 2:4 DECODER

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DESCRIPTION OF 2:4 DECODER

• The logic circuit design of the 2-to-4 line decoder is given below which is implemented by using NOT
and NAND gates.
• Two NOT gates or inverters provide the complement of select inputs.
• • A common enable line is connected to each NAND gate such that when EN= 0 all the outputs are zero
and if EN=1, depends on the select inputs S1 and S0, outputs are produced.
• It is possible to design 2-to-4 decoder using 4 NAND gates as shown in figure, along with truth table.
• If both inputs are zero (S1=S0=0),Y0 will be zero , if S1 = 0 and S0= 1, thenY1 will be 0 and so on.
• Therefore, only one output will be low for any combinations of inputs at a given time and all other
outputs will be high.

3:8 DECODER

INPUTS OUTPUTS

EN S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 1 1 1 1 1 1 1 1

1 0 0 0 1 1 1 1 1 1 1 0

1 0 0 1 1 1 1 1 1 1 0 1

1 0 1 0 1 1 1 1 1 0 1 1

1 0 1 1 1 1 1 1 0 1 1 1

1 1 0 0 1 1 1 0 1 1 1 1

1 1 0 1 1 1 0 1 1 1 1 1

1 1 1 0 1 0 1 1 1 1 1 1

1 1 1 1 0 1 1 1 1 1 1 1

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LOGIC DIAGRAM OF 3:8 DECODER

• The truth table of a 3:8 Decoder is shown below in which eight input combinations 000,
001,010,011,100,101,110 and 111 on the select lines produces Y0=0 …..then Y7=0 respectively.
• That means when S2=0,S1=0 and S0 =0, the output at Y0=0, similarly Y1=0 if the select inputs S2=0,
S1=0 and S0=1 and so on.
From the truth table, we can write the output expressions as
• If S2=0, S1=0 and S0=0, then Y0=0
• If S2=0,S1= 0 and S0=1, then Y1=0
• If S2=0 ,S1=1 and S0=0, then Y2=0
• If S2=0 ,S1=1 and S0=1, then Y3=0
• If S2=1, S1=0 and S0=0, then Y4=0
• If S2=1,S1= 0 and S0=1, then Y5=0
• If S2=1 ,S1=1 and S0=0, then Y6=0
• If S2=1 ,S1=1 and S0=1, then Y7=0

DESCRIPTION OF 3:8 DECODER

• The logic circuit design of the 3-to-8 line decoder is implemented by using NOT and NAND gates.
• Three NOT gates or inverters provide the complement of select inputs.
• A common enable line is connected to each NAND gate such that when EN= 0 all the outputs are zero
and if EN=1, depends on the select inputs S2, S1 and S0, outputs are produced.
• It is possible to design 3-to-8 decoder using 8 NAND gates as shown in figure, along with truth table.
• If both inputs are zero (S2=S1=S0=0),Y0 will be zero , if S2=0, S1 = 0 and S0= 1, thenY1 will be 0 and
so on.
• Therefore, only one output will be low for any combinations of inputs at a given time and all other
outputs will be high.

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MULTIPLEXER

Multiplexer means transmitting a large number of information units over a smaller number of channels
or lines. A digital multiplexer is a combinational circuit that selects binary information from one of
many input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2 n input lines and n selection lines whose bit
combination determine which input is selected.
A multiplexer is also called as a Data Selector as it selects one of the inputs and passes it in the output
based on the values of select input sequence.

2:1 MULTIPLEXER

• A 2:1 multiplexer consists two data input lines as I 0 and I1 , only one select lines as S0 and a single
output line Y. The select lines S0 select one of the two input lines to connect the output line. The
particular input combination on select lines selects one of input (I 0 and I1 ) to the output.
• The figure below shows the block diagram of a 2:1 multiplexer in which the multiplexer decodes the
input through select line.

LOGIC DIAGRAM OF 2:1 MULTIPLEXER

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• The truth table of a 2:1 multiplexer is shown below in which two input combinations 0 and 1 on the
select lines respectively switches the inputs I0 and I1 the output.
• That means when S0 =0, the output at Y is I0, similarly Y is I1 if the select inputs S0 =1 and so on.

INPUTS OUTPUT

EN’ S0 Y
1 X 0
0 0 I0
0 1 I1

From the above truth table, we can write the output expressions as
• If S0 =0, then Y = I0
• If S0 =1 then Y = I3
WORKING:
• When select inputs are S0 =0, then the output Y = I0
• When select inputs are S0 =1 , then the output Y = I1

4:1 MULTIPLEXER
• A 4:1 multiplexer consists four data input lines as I 0 ,I1 ,I2 and I3, two select lines as S0 and S1 and a
single output line Y. The select lines S0 and S1 select one of the four input lines to connect the output
line. The particular input combination on select lines selects one of input (I 0 ,I1 ,I2 and I3) to the output.
• The figure below shows the block diagram of a 4:1 multiplexer in which the multiplexer decodes the
input through select line.

• The truth table of a 4:1 multiplexer is shown below in which four input combinations 00, 10, 01 and 11
on the select lines respectively switches the inputs I0 ,I1 ,I2 and I3 to the output. That means when S0 =0
and S1 =0 , the output at Y is I0, similarly Y is I1 if the select inputs S0 =0 and S1 =1 and so on.

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INPUTS OUTPUT

EN’ S1 S0 Y
1 X X 0

0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3

From the above truth table, we can write the output expressions as
• If S0 =0 and S1 =0 , then Y = I0
• If S0 =0 and S1 =1 , then Y = I1
• If S0 =1 and S1 =0 , then Y = I2
• If S0 =1 and S1 =1 , then Y = I3

• From the expressions of the truth table, a 4:1 multiplexer can be implemented by using basic logic gates.
The below figure shows the logic circuit of 4:1 MUX:

WORKING:
• When S0 =0 and S1 =0 , then Y = I0
• When S0 =0 and S1 =1 , then Y = I1
• When S0 =1 and S1 =0 , then Y = I2
• When S0 =1 and S1 =1 , then Y = I3
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8:1 MULTIPLEXER
• An 8:1 multiplexer consists eight data input lines as I 0 ,I1 ,I2, I3 ,I4 ,I5,I6 and I7;three select lines as S0 S1
and S2 and a single output line Y. The select lines S0 S1 and S2 select one of the eight input lines to
connect the output line. The particular input combination on select lines selects one of input (I 0 ,I1 ,I2, I3
,I4 ,I5,I6 and I7) to the output.
• The figure below shows the block diagram of a 8:1 multiplexer in which the multiplexer decodes the
input through select line.

• The truth table of a 8:1 multiplexer is shown below in which eight input combinations 000,
001,010,011,100,101,110 and 111 on the select lines respectively switches the inputs I 0 ,I1 ,I2, I3 ,I4 ,I5,I6
and I7 to the output. That means when S0 =0,S1 =0 and S2 =0 the output at Y is I0, similarly Y is I1 if the
select inputs S0 =0,S1 =0 and S2 =1 and so on.
From the truth table, we can write the output expressions as
• If S2 =0,S1 =0 and S0 =0 , then Y = I0
• If S2 =0,S1 =0 and S0 =1, then Y = I1
• If S2 =0,S1 =1 and S0 =0, then Y = I2
• If S2 =0,S1 =1 and S0 =1 , then Y = I3
• If S2 =1,S1 =0 and S0 =0 , then Y = I4
• If S2 =1,S1 =0 and S0 =1 , then Y = I5
• If S2 =1,S1 =1 and S0 =0 , then Y = I6
• If S2 =1,S1 =1 and S0 =1 , then Y = I7

INPUTS OUTPUT
EN’ S2 S1 S0 Y
1 X X X 0
0 0 0 0 I0
0 0 0 1 I1
0 0 1 0 I2
0 0 1 1 I3
0 1 0 0 I4
0 1 0 1 I5
0 1 1 0 I6
0 1 1 1 I7

• From the expressions of the truth table, a 8:1 multiplexer can be implemented by using basic logic gates.
The below figure shows the logic circuit of 8:1 MUX:

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WORKING:
• when S2 =0,S1 =0 and S0 =0 , then Y = I0
• when S2 =0,S1 =0 and S0 =1, then Y = I1
• when S2 =0,S1 =1 and S0 =0, then Y = I2
• when S2 =0,S1 =1 and S0 =1 , then Y = I3
• when S2 =1,S1 =0 and S0 =0 , then Y = I4
• when S2 =1,S1 =0 and S0 =1 , then Y = I5
• when S2 =1,S1 =1 and S0 =0 , then Y = I6
• when S2 =1,S1 =1 and S0 =1 , then Y = I7

DEMULTIPLEXER
A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several digital
output lines. A demultiplexer of 2n outputs has n select lines, which are used to select which output line
to send the input. A demultiplexer is also called a data distributor.

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1:4 DEMULTIPLEXER

DESCRIPTION OF 1:4 DEMUX

• The 1:4 Demultiplexer consists of 1 input signal, 2 select input signals and 4 output signals. The number
of the output signal is always decided by the number of the control signal and vice versa.
• There are 2 NOT gates through which select inputs are passed, and 4 NAND gates, which decides or
control the output. The combination of the input signal along with control signals will decide that the
output through which input signal will pass through.
• The truth table of a 1:4 demultiplexer is shown below in which four input combinations 00, 10, 01 and 11
on the select lines switches the input I at the terminals Y0 ,Y1 ,Y2 and Y3 output in complement form. That
means when S1 =0 and S0 =0 , the output at Y is Y0 in complement form, similarly Y is Y1 if the select
inputs S1 =0 and S0 =1 and so on.

SELECT OUTPUT ‘I’ available in

INPUTS complement form
S1 S0 Y
0 0 Y0

0 1 Y1

1 0 Y2

1 1 Y3

From the above truth table, I is available in complement form at Y 0 ,Y1 ,Y2 and Y3 ,we can write
the output expressions as
• If S1 =0 and S0 =0 , then Y = Y0 (in complement form)
• If S1 =0 and S0 =1 , then Y = Y1(in complement form)
• If S1 =1 and S0 =0 , then Y = Y2(in complement form)
• If S1 =1 and S0 =1 , then Y = Y3(in complement form)

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LOGIC DIAGRAM OF 1:4 DEMULTIPLEXER

1:8 DEMULTIPLEXER

DESCRIPTION OF 1:8 DEMUX

• The 1:8 Demultiplexer consists of 1 input signal, 3 select signals and 8 output signals. The number of the
output signal is always decided by the number of the control signal and vice versa.
• There are 3 NOT gates through which select inputs are passed, and 8 NAND gates, which decides or
control the output. The combination of the input signal along with control signals will decide that the
output through which input signal will pass through.
• The truth table of a 1:8 demultiplexer is shown below in which eight input combinations
000,001,010,011,100,101,110 and 111 on the select lines switches the input I at the terminals Y 0 ,Y1 ,Y2
,Y3 , Y4 , Y5 , Y6 and Y7 output in complement form. That means when S2 =0 ,S1 =0 and S0 =0 , the
output at Y0 in complement form of I , similarly output is Y1 if the select inputs S2 =0 ,S1 =0 and S0
=1 and so on.
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SELECT INPUTS OUTPUT ‘I’ available in complement form

S2 S1 S0 Y
0 0 0 Y0
0 0 1 Y1
0 1 0 Y2
0 1 1 Y3
1 0 0 Y4
1 0 1 Y5
1 1 0 Y6
1 1 1 Y7
WORKING OF 1:8 DEMUX
From the above truth table, I is available in complement form at Y 0 ,Y1 ,Y2 and Y3 ,we can write the output
expressions as
• If S2 =0 ,S1 =0, S0 =0 , then Y = Y0 (in complement form)
• If S2 =0 ,S1 =0 and S0=1 , then Y = Y1 (in complement form)
• If S2 =0 ,S1 =1 and S0 =0 , then Y = Y2 (in complement form)
• If S2 =0 ,S1 =1 and S0 =1 , then Y = Y3 (in complement form)
• If S2 =1 ,S1 =0, S0 =0 , then Y = Y4 (in complement form)
• If S2 =1 ,S1 =0 and S0=1 , then Y = Y5 (in complement form)
• If S2 =1 ,S1 =1 and S0 =0 , then Y = Y6 (in complement form)
• If S2 =1 ,S1 =1 and S0 =1 , then Y = Y7 (in complement form)

LOGIC DIAGRAM OF 1:8 DEMULTIPLEXER

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Sequential Circuits: Flip-Flops- CLK SR Flip- Flop, D Flip-Flop, J-K Flip Flop, T Flip-Flop.

Flip Flops

Flip flops are an application of logic gates. With the help of Boolean logic you can create memory with
them.
When a certain input value is given to them, they will be remembered and executed, if the logic gates
are designed correctly.
There are mainly four types of flip flops that are used in electronic circuits. They are
 The basic Flip Flop or S-R Flip Flop
 D Flip Flop [Delay Flip Flop]
 J-K Flip Flop
 T Flip Flop[Toggle Flip Flop]
 MS JK FF

Clocked S-R Flip Flop

It is also called a Gated S-R flip flop.

The problems with S-R flip flops using NOR and NAND gate is the invalid state.
This problem can be overcome by using a bistable SR flip-flop that can change outputs when certain
invalid states are met, regardless of the condition of either the Set or the Reset inputs.

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Clocked S-R Flip Flop

► It can be formed by using NAND or NOR gates, the o/p is either low or high and remains same. To
change o/p, i/p trigger is given.
► High voltage applied to S i/p is called setting the flip-flop & gives binary o/p as ‘1’.
► High voltage applied to R i/p is called resetting the flip-flop & gives binary o/p as ‘0’.
► This device is commonly referred to as a gated/clocked SR latch , since the control signal can be thought
of as opening a gate through which signals on the S & R inputs can propagate to the output. A clock
pulse[CP] is given to the inputs of the NAND gate.
Clocked S-R Flip Flop
A clock pulse(A signal used to synchronize the operations of an electronic system. Clock pulses are
continuous, precisely spaced changes in voltage. ) [CP] is given to the inputs of the AND Gate.
When the value of the clock pulse is ‘0’, the outputs of both the AND Gates remain ‘0’. As soon as a
pulse is given the value of CP turns ‘1’.
This makes the values at S and R to pass through the NOR Gate flip flop. But when the values of both S
and R values turn ‘1’, the HIGH value of CP causes both of them to turn to ‘0’ for a short moment.
As soon as the pulse is removed, the flip flop state becomes intermediate.
Thus either of the two states may be caused, and it depends on whether the set or reset input of the flip-
flop remains a ‘1’ longer than the transition to ‘0’ at the end of the pulse.
Thus the invalid states can be eliminated.

The two NAND gates apply the control signal S & R during time intervals when the enable signal CP is
logic 1.
When CP is logic 0, the inputs are held in the S=R=0 state. So the operation of the latch is as follows-
When CP=0, no change occurs. As soon as a pulse is given the value of CP turns ‘1’.
 This makes the values at S & R to pass through the flip-flop. But when the values of both S & R values
turn ‘1’, the high value of CP causes both of them to turn to ‘0’ for a short moment.
 As soon as the pulse is removed, the flip-flop state becomes intermediate.
 Thus, either of the two states may be caused & it depends on whether the set or reset i/p of flip-flop
remains ‘1’ longer than the transition to ‘0’ at the end of the pulse.
 Thus the invalid states can be eliminated.

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D Flip-flop:

It is also called as Delay flip-flop or Data flip-flop.

The circuit diagram and truth table is given below.

It is slight modification of the clocked SR flip-flop

• The D input is connected to the S input and the complement of the D input is connected to the R input.
• The D input is passed on to the flip flop when the value of CP is ‘1’.
• When CP is HIGH, the flip flop moves to the SET state. If it is ‘0’, the flip flop switches to the CLEAR
state.
• The D flip flop will allows the value of D to reach the o/p only when clock pulse occurs when a clock is
low both the AND gates are disabled and D can change its value without affecting o/p Q.
• A high or 1 clock will transfer the data from D to o/p ,the value of D is immaterial when clk is 0 and
mark as don’t care, the Q will be the same as D while CLK is HIGH and Q will remain latched(constant
regardless of change in D) when CLk goes LOW.

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J-K flip flop

JK flip flop was invented by Jack Kilby. So it is also called as JK flip-flop.

The basic gated SR NAND flip flop suffers from two basic problems: the S = 1 and R = 1 condition
(S = R = 1) must always be avoided. To overcome these two fundamental design problems with the SR
flip-flop design, the JK flip Flop was developed.
“JK flip flop” has no invalid or forbidden input states of the SR Latch even when S and R are both at
logic “1”.
With the addition of a clock input circuitry that prevents the illegal or invalid output condition that can
occur when both inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK
flip-flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”.(every
time the J and K inputs are in 1. When a rising clock pulse appears, will change both outputs Q and /Q.
If Q was 1, then with the clock pulse will change to 0, and /Q will be always the opposite to Q.)

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called the
J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: S=J.Q’ and R=K.Q
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input NAND
gates with the third input of each gate connected to the outputs at Q and Q’. This cross coupling of the
flip-flop allows the previously invalid condition of S = “1” and R = “1” state to be used to produce a
“toggle action” as the two inputs are now interlock(join).

CIRCUIT DIAGRAM OF JK FLIP-FLOP

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JK flip-flop is basically an SR flip flop with feedback which enables only one of its two input terminals,
either SET or RESET to be active at any one time thereby eliminating the invalid condition seen
previously in the SR flip flop circuit. Also when both the J and the K inputs are at logic level “1” at the
same time, and the clock input is pulsed either “HIGH”, the circuit will “toggle” from its SET state to a
RESET state, or visa-versa.
JK flip-flop has four states. They are shown in truth table. The description of each combination and
corresponding result is given below:
1) J=0, K=0—>Q & Q’ = Remember[previous value]
If both the values of J &K are switched to 0, then the circuit remembers the value of J&K in their
previous state. So there is no change in the output Q.
2)J=0, K=1—>Q=0, Q’=1 [RESET state]
When J=0 and K=1 then output Q=0.This state is known as the RESET state.
3) J=1, K=0—>Q=1, Q’=0 [SET state]
When J=1 and K=0 then output Q=1. This state is called the SET state.
4)J=1, K=1—>Q & Q’ TOGGLE
When J=1 and K=1 then output Q and Q’ toggles. This is an toggle state because the values of both Q and Q’
are complimented forms of their previous values.

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T Flip Flop
This is a simpler version of the J-K flip flop. Both the J and K inputs are connected together and thus are
also called a single input J-K flip flop. When clock pulse is given to the flip flop, the output begins to
toggle.

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Register: 4-bit shift register (SISO) Binary Counter- 4-bit synchronous and Asynchronous binary counter.

Shift Registers
• Registers are used for storage and transfer of binary information in system.
• The difference between a register and counter is that a register has no specified sequence states
• They are used for purpose of storing and shifting binary data
• They also used in operations such as complementation, multiplication and division, storing of binary bit
done with a flip flop,
• FF has two states 1 and 0 ,if the circuit is 0 state it continues to remain in this state as also if it is 1 ,this
property is called memory.
• An array of FFs suitable for storing a binary information is referred as register.
• The storage capacity of register is the number of bits of digital data it can store.

SISO SHIFT REGISTER

• SISO RIGHT SHIFT REGISTER
• SISO LEFT SHIFT REGISTER

Serial-in to Serial-out (SISO)

• The data is shifted serially “IN” and “OUT” of the register, one bit at a time in either a left or right
direction under clock control.
• The data is allowed to flow straight through the register and out of the other end. Since there is only one
output, the DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in
to Serial-Out Shift Register or SISO.
• The SISO shift register is one of the simplest of the four configurations as it has only three connections,
the serial input (SI) which determines what enters the left hand flip-flop, the serial output (SO) which is
taken from the output of the right hand flip-flop and the sequencing clock signal (Clk).
• What is use of shift register if the output data is exactly the same as the input data. this type of Shift
Register also acts as a temporary storage device or it can act as a time delay device for the data, with the
amount of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying
the application of the clock pulses. Commonly available IC’s include the 74HC595 8-bit Serial-in to
Serial-out Shift Register all with 3-state outputs.

SISO RIGHT SHIFT REGISTER

A Serial-In Serial-Out shift register is a sequential logic circuit that allows data to be shifted in and out one bit
at a time in a serial manner. It consists of a cascade of flip-flops connected in series, forming a chain. The input
data is applied to the first flip-flop in the chain, and as the clock pulses, the data propagates through the flip-
flops, ultimately appearing at the output.
The logic circuit provided below demonstrates a serial-in serial-out (SISO) shift register. It comprises four D
flip-flops that are interconnected in a sequential manner. These flip-flops operate synchronously with one
another, as they all receive the same clock signal.
Each D flip-flop in the circuit has a Data (D) input, a Clock (CLK) input, and an output (Q). The D input represents
the data to be loaded into the flip-flop, while the CLK input is connected to the common clock signal. The output
(Q) of each flip-flop is connected to the D input of the next flip-flop, forming a cascade.

In a right-shift SISO shift register, data bits move towards the right with each clock pulse.

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COMPUTER ARCHITECTURE

Shift registers wherein input enters from left side and numbers already present on it, effuse or excrete from right
side, are called shift right registers. In other words, registers which transfers or shifts input data rightwards, are
called shift right registers. In figure 7.2, a shift right register has been illustrated, which contains four flip-flops
(it means that this register can store only a 4 – bits binary number). According to this figure, every Q output
keeps on setting D input of every next flip-flop. When rising clock edge arrives, then stored bits shift rightward
according to the “one–bit position per clock pulse” principle. For example, D in value is 1 (i.e. Din = 1) and Q =
0000, then upon influx of the first positive clock edge (i.e. clock pulse), leftward flip-flop tends to set. In such a

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COMPUTER ARCHITECTURE

situation, all data inputs except input on the left side, are 0s. Thus, as a result of flip-flop D3 being set, the word
stored within a register is as follows;
Q=1000
Q=1000
With the appearance of this word, values of D2 and D3 turn out 1 (i.e. D2 = D3 = 1s), because Q3 output tends to
set output D3 (see figure). Similarly, following results with the advent of second rising clock edge.
Q=0100
Similarly, following changes take place as a result of 3rd clock pulse and 4th clock pulse.
Q=0010
Q=0001

SISO LEFT SHIFT REGISTER

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COMPUTER ARCHITECTURE

A left-shift SISO shift register works similarly but moves data bits from right to left.
A shift register, wherein input data is entered from the right side, whereas digits already present on the register
leave out/ remove from the left side, are called shift left registers. In other words, registers which shift input
data towards left, are called shift left registers.
In figure 7.5, a shift left register has been elucidated, which consists of four D type flip-flops. According to the
figure, Din sets the right most flip-flop, Q0 sets the second flip-flop, Q1 sets third flip-flop and Q2 sets fourth or
final flip-flop. Remember that every time this register receives next positive clock pulse its stored bits shift
leftwards as per one position / clock pulse principle. For example, if a state of D in = 1 and Q = 0000 exits on
register, in such a situation, the rightmost flip-flop (Q0) sets with the arrival of first clock pulse (or rising clock
edge), as a result values of all data inputs are 0, except 1 existing on the right end. In other words, stored word
in the register is as follows;

Q=0000
Q=0001
Similarly, as a result of third and fourth positive clock pulses, following changes take place in the register;
Q=0010
Q=0100
Q=1000

APPLICATIONS OF SHIFT REGISTERS

Applications of SISO Shift Registers
Serial-In Serial-Out shift registers find applications in a wide range of digital systems. Here are a few common
examples:
 Data Storage and Retrieval: SISO shift registers are often used to store and retrieve data in applications
where serial transmission is more efficient or feasible. For instance, in communication systems, data is
often transmitted serially, and a shift register allows for temporary storage before further processing.
 Serial-to-Parallel Conversion: By using a SISO shift register in combination with additional circuitry,
serial data can be converted into parallel form. This conversion is useful when interfacing between serial
and parallel devices, such as microprocessors and peripheral devices.
 Delay and Time-Sequence Generation: The cascaded nature of shift registers enables the generation of
delayed versions of a signal or the generation of complex time sequences. By tapping into different stages
of the shift register, various delayed versions of the input signal can be obtained.
 Data Encryption and Decryption: Shift registers can be employed in cryptographic applications for
data encryption and decryption. By utilizing feedback connections and appropriate logical operations, the
shift register can act as a key generator or cipher unit.
 Frequency Division and Counting: Serial-In Serial-Out shift registers are used in frequency division and
counting applications. By connecting the output of a flip-flop back to the input, the shift register can
function as a binary counter, dividing the input frequency by a factor of two with each clock pulse.
• Serial adder
• Parity generator
• Ring counter
• Up-down counter
• Used in digital voltmeter and analog converter
• Time delay
• Sequence generator
• Serial to parallel data converter
• Parallel to serial data converter
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Advantages of SISO Shift Register

 Simplicity : The SISO shift registers are simple to implement and understand since they contain only one
input and one output. This keeps the design to be simple to be fabricated, hence widely used in many
applications.
 Space Efficiency : A SISO can store the required data using only a few storage elements as compared to
that in a parallel shift register, which may require more storage devices. Thus, in a limited-space
application, the SISO is in preference.
 Economical : This is mainly because use of the above disadvantages of the parallel shift registers is more
economical than the parallel shift register or preference of the SISO shift register to any other composite
system for storing information.
 Sequential Processing : SISO registers process data in a serial order, which can be very useful if the data
has to be treated in some given order or sequence.
 Compatibility : Serial communication systems predominantly use SISO shift registers, and they may
conveniently use this technology when adapting to various communication protocols and standards.

Disadvantages of SISO Register

 Slower Data Transmission : Due to processing data series ways, SISO shift registers may have lower
data transfer rates than their parallel counterparts which transfer multiple bits at once. This is a
disadvantage especially in cases where high-speed data processing is needed.
 Limited Capability for Parallel Processing : The SISO Shift Registers process one bit at a time, thus
restrict the ability to parallel processing. They are not suitable for applications where parallel processing
is of the essence.
 Complexity for Performing Multiple Operations : In case an application requires both sequential and
parallel logic operations simultaneously on multi-bit inputs, this need may become impractical since
several SISO will be required rather than a single one thus increasing complexity and making it less
efficient than using a PIS register.
 Data Synchronization Difficulties : As far as synchronization with respect to the synchronization input
and output is concerned, it becomes difficult due to sequential nature of SISO shift registers in systems
where such aspects are crucial.
 High propagation delays : When using a SISO register, we will often see higher bureaucratic losses
should we try transmitting data through it too fast because it just cannot do such things like an analog
circuit would have been able to perform those actions.

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COUNTERS

• Circuits for counting events are frequently used in computers and other digital systems. Since a
counter circuit must remember its past states, it has to possess memory.
• FF can be connected to each other to perform counting operations, such combination of FF is called as
counters.
• A single FF have its o/p one of two logic states 0 or 1 ,i.e. it can count one to two.
• Similarly 2 FF count 4 possible states and so on ,in general counter with n number of FF can count
max. 1 to 2n
• A counters can be synchronous( they need clk pulse) or asynchronous(no need of clock pulse)

COUNTERS

ASYNCHRONOUS SYNCHRONOUS
COUNTERS COUNTERS

• Counters can be classified into two broad categories according to the way they are clocked:
• Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse, and then each
successive flip-flop is clocked by the Q or Q' output of the previous flip-flop.
• Synchronous Counters - all memory elements are simultaneously triggered by the same clock.

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COMPUTER ARCHITECTURE

4-bit (MOD-16) Asynchronous Up Counter

(RIPPLE COUNTER)

CLOCK Q3 Q2 Q1 Q0
PULSE

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

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COMPUTER ARCHITECTURE

MOD 16 Asynchronous Up counter:

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All
subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also
called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
CONSTRUCTION:
• To implement a 4-bit (MOD-16) Asynchronous Up Counter, 4 JK flip flops are used.
• All the preset terminals of the flip flops are connected to PRE’ & All the clear terminals of the flip flops
are connected to the CLR’.
• The clock of 1Hz is provided to first flip flop .The o/p Q0 of first ff is provided as clock to second ff.
The o/p Q1 of second ff is provided as clock to third ff. The o/p Q2 of third ff is provided as clock to
fourth ff. Q0 ,Q1, Q2 & Q3 are the required o/ps of the counter.
The initial state of the o/p of counter is denoted as 0000 during clock 0 and on providing the clock pulses , the
counter starts counting and generating the o/p from 0000 to 1111 as it is 4-bit Asynchronous Up Counter.

WORKING:
• When clock 0 is applied, all the FFs are reset so the output Q3 Q2 Q1 Q0 =0 0 0. This is the initial position
of the counter.
• When clock 1 is applied, we get the output as Q3 Q2 Q1 Q0 =0 0 0 1
• When clock 2 is applied, we get the output as Q3 Q2 Q1 Q0 =0 0 1 0
• When clock 3 is applied, we get the output as Q3 Q2 Q1 Q0 =0 0 1 1
• When clock 4 is applied, we get the output as Q3 Q2 Q1 Q0 =0 1 0 0
• When clock 5 is applied, we get the output as Q3 Q2 Q1 Q0 =0 1 0 1
• When clock 6 is applied, we get the output as Q3 Q2 Q1 Q0 =0 1 1 0
• When clock 7 is applied, we get the output as Q3 Q2 Q1 Q0 =0 1 1 1
• When clock 8 is applied, we get the output as Q3 Q2 Q1 Q0 =1 0 0 0
• When clock 9 is applied, we get the output as Q3 Q2 Q1 Q0 =1 0 0 1
• When clock 10 is applied, we get the output as Q3 Q2 Q1 Q0 =1 0 1 0
• When clock 11 is applied, we get the output as Q3 Q2 Q1 Q0 =1 0 1 1
• When clock 12 is applied, we get the output as Q3 Q2 Q1 Q0 =1 1 0 0
• When clock 13 is applied, we get the output as Q3 Q2 Q1 Q0 =1 1 0 1
• When clock 14 is applied, we get the output as Q3 Q2 Q1 Q0 =1 1 1 0
• When clock 15 is applied, we get the output as Q3 Q2 Q1 Q0 =1 1 1 1
• Thus we have implemented MOD 16 or 4-Bit Asynchronous Up counter which starts to count from
the initial value ie 0000 and counts in forward manner till it reaches the final value of 1111.
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COMPUTER ARCHITECTURE

4-bit (MOD-16) Asynchronous Down Counter

(RIPPLE COUNTER)

CLOCK Q3 Q2 Q1 Q0
PULSE

0 1 1 1 1
1 1 1 1 0
2 1 1 0 1

3 1 1 0 0
4 1 0 1 1
5 1 0 1 0

6 1 0 0 1
7 1 0 0 0

8 0 1 1 1
9 0 1 1 0
10 0 1 0 1

11 0 1 0 0
12 0 0 1 1
13 0 0 1 0

14 0 0 0 1
15 0 0 0 0

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COMPUTER ARCHITECTURE

MOD 16 Asynchronous Down counter:

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All
subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also
called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
CONSTRUCTION:
• To implement a 4-bit (MOD-16) Asynchronous Down Counter, 4 JK flip flops are used.
• All the preset terminals of the flip flops are connected to PRE’ & All the clear terminals of the flip flops
are connected to the CLR’.
• The clock of 1Hz is provided to first flip flop .The o/p Q0’ of first ff is provided as clock to second ff.
The o/p Q1’ of second ff is provided as clock to third ff. The o/p Q2’ of third ff is provided as clock to
fourth ff. Q0 ,Q1, Q2 & Q3 are the required o/ps of the counter.
The initial state of the o/p of counter is denoted as 1111 during clock 0 and on providing the clock pulses , the
counter starts counting and generating the o/p from 1111 to 0000 as it is 4-bit Asynchronous Down Counter.

WORKING:
• When clock 0 is applied, all the FFs are reset so the output Q3 Q2 Q1 Q0 =1111. This is the initial
position of the counter.
• When clock 1 is applied, we get the output as Q3 Q2 Q1 Q0 =1110
• When clock 2 is applied, we get the output as Q3 Q2 Q1 Q0 =1101
• When clock 3 is applied, we get the output as Q3 Q2 Q1 Q0 =1100
• When clock 4 is applied, we get the output as Q3 Q2 Q1 Q0 =1011
• When clock 5 is applied, we get the output as Q3 Q2 Q1 Q0 =1010
• When clock 6 is applied, we get the output as Q3 Q2 Q1 Q0 =1001
• When clock 7 is applied, we get the output as Q3 Q2 Q1 Q0 =1000
• When clock 8 is applied, we get the output as Q3 Q2 Q1 Q0 =0111
• When clock 9 is applied, we get the output as Q3 Q2 Q1 Q0 =0110
• When clock 10 is applied, we get the output as Q3 Q2 Q1 Q0 =0101
• When clock 11 is applied, we get the output as Q3 Q2 Q1 Q0 =0100
• When clock 12 is applied, we get the output as Q3 Q2 Q1 Q0 =0011
• When clock 13 is applied, we get the output as Q3 Q2 Q1 Q0 =0010
• When clock 14 is applied, we get the output as Q3 Q2 Q1 Q0 =0001
• When clock 15 is applied, we get the output as Q3 Q2 Q1 Q0 =0000
• Thus we have implemented MOD 16 or 4-Bit Asynchronous Down counter which starts to count
from the initial value ie 1111 and counts in backward or reverse manner till it reaches the final
value of 0000.
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SYNCHRONOUS COUNTERS
• Synchronous Counters are so called because the clock input of all the individual flip-flops within the
counter are all clocked together at the same time by the same clock signal.
• In Synchronous Counter, the external clock signal is connected to the clock input of EVERY
individual flip-flop within the Counter so that all of the flip-flops are clocked together simultaneously
(in parallel) at the same time giving a fixed time relationship. i.e. changes in the output occur in
“synchronization” with the clock signal.
• The result of this synchronization is that all the individual output bits changing state at exactly the same
time in response to the common clock signal with no ripple effect and therefore, no propagation delay.

4-bit (MOD-16) SYNCHRONOUS UP COUNTER

CLOCK PULSE Q3 Q2 Q1 Q0

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

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• It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each of
the J-K flip-flops in the counter chain and that both the J and K inputs are all tied together in toggle
mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing
the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a predetermined
sequence of states in response to the common clock signal, advancing one state for each pulse.
• The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but
the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also
supplied with signals from the input and output of the previous stage. These additional AND gates
generate the required logic for the JK inputs of the next stage.
• If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are
“HIGH” we can obtain the same counting sequence as with the asynchronous circuit but without the
ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time.
• Then as there is no inherent propagation delay in synchronous counters, because all the counter stages
are triggered in parallel at the same time, the maximum operating frequency of this type of frequency
counter is much higher than that for a similar asynchronous counter circuit.

WORKING:
• When clock 0 is applied, all the FFs are reset so the output Q3 Q2 Q1 Q0 =0 0 0. This is the initial
position of the counter.
• When clock 1 is applied, we get the output as Q3 Q2 Q1 Q0 =0 0 0 1
• When clock 2 is applied, we get the output as Q3 Q2 Q1 Q0 =0 0 1 0
• When clock 3 is applied, we get the output as Q3 Q2 Q1 Q0 =0 0 1 1
• When clock 4 is applied, we get the output as Q3 Q2 Q1 Q0 =0 1 0 0
• When clock 5 is applied, we get the output as Q3 Q2 Q1 Q0 =0 1 0 1
• When clock 6 is applied, we get the output as Q3 Q2 Q1 Q0 =0 1 1 0
• When clock 7 is applied, we get the output as Q3 Q2 Q1 Q0 =0 1 1 1
• When clock 8 is applied, we get the output as Q3 Q2 Q1 Q0 =1 0 0 0
• When clock 9 is applied, we get the output as Q3 Q2 Q1 Q0 =1 0 0 1
• When clock 10 is applied, we get the output as Q3 Q2 Q1 Q0 =1 0 1 0
• When clock 11 is applied, we get the output as Q3 Q2 Q1 Q0 =1 0 1 1
• When clock 12 is applied, we get the output as Q3 Q2 Q1 Q0 =1 1 0 0
• When clock 13 is applied, we get the output as Q3 Q2 Q1 Q0 =1 1 0 1
• When clock 14 is applied, we get the output as Q3 Q2 Q1 Q0 =1 1 1 0
• When clock 15 is applied, we get the output as Q3 Q2 Q1 Q0 =1 1 1 1
• Thus, we have implemented MOD 16 or 4-Bit synchronous Up counter which starts to count from
the initial value ie 0000 and counts in forward manner till it reaches the final value of 1111.

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COMPUTER ARCHITECTURE

4-bit (MOD-16) SYNCHRONOUS DOWN COUNTER

CLOCK Q3 Q2 Q1 Q0
PULSE

0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

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COMPUTER ARCHITECTURE

• It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each of
the J-K flip-flops in the counter chain and that both the J and K inputs are all tied together in toggle
mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic “1” allowing
the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a predetermined
sequence of states in response to the common clock signal, advancing one state for each pulse.
• The J and K inputs of flip-flop FFB are connected directly to the output Q’A of flip-flop FFA, but
the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also
supplied with signals from the input and output of the previous stage. These additional AND gates
generate the required logic for the JK inputs of the next stage.
• If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q’) are
“HIGH” we can obtain the same counting sequence as with the asynchronous circuit but without the
ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time.
• Then as there is no inherent propagation delay in synchronous counters, because all the counter stages
are triggered in parallel at the same time, the maximum operating frequency of this type of frequency
counter is much higher than that for a similar asynchronous counter circuit.

WORKING:
• When clock 0 is applied, all the FFs are reset so the output Q3 Q2 Q1 Q0 =1111. This is the initial
position of the counter.
• When clock 1 is applied, we get the output as Q3 Q2 Q1 Q0 =1110
• When clock 2 is applied, we get the output as Q3 Q2 Q1 Q0 =1101
• When clock 3 is applied, we get the output as Q3 Q2 Q1 Q0 =1100
• When clock 4 is applied, we get the output as Q3 Q2 Q1 Q0 =1011
• When clock 5 is applied, we get the output as Q3 Q2 Q1 Q0 =1010
• When clock 6 is applied, we get the output as Q3 Q2 Q1 Q0 =1001
• When clock 7 is applied, we get the output as Q3 Q2 Q1 Q0 =1000
• When clock 8 is applied, we get the output as Q3 Q2 Q1 Q0 =0111
• When clock 9 is applied, we get the output as Q3 Q2 Q1 Q0 =0110
• When clock 10 is applied, we get the output as Q3 Q2 Q1 Q0 =0101
• When clock 11 is applied, we get the output as Q3 Q2 Q1 Q0 =0100
• When clock 12 is applied, we get the output as Q3 Q2 Q1 Q0 =0011
• When clock 13 is applied, we get the output as Q3 Q2 Q1 Q0 =0010
• When clock 14 is applied, we get the output as Q3 Q2 Q1 Q0 =0001
• When clock 15 is applied, we get the output as Q3 Q2 Q1 Q0 =0000
• Thus we have implemented MOD 16 or 4-Bit synchronous Down counter which starts to count
from the initial value ie 1111 and counts in backward or reverse manner till it reaches the final
value of 0000.
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COMPUTER ARCHITECTURE

APPLICATIONS OF COUNTERS
1. Frequency divider
2. Frequency measurement
3. Clock generator
4. Object counter
5. Digital multimeters
6. Digital clock
7. Analog to digital converters
8. Parallel to serial data conversion
9. Count occurrences of any event
10. Frequency division
11. Generating timing sequence to control operations of digital system
12. Ex: Digital clock use to keep time in hrs, mins and seconds

Advantages of Asynchronous Counter

1. Simple design and construction – Asynchronous counters are easy to design and build due to their
straightforward nature. This simplicity makes them ideal for many applications.
2. Requires fewer flip-flops – They need fewer flip-flops than other types of counters. This reduces
complexity, making them easier to implement.
3. Faster than synchronous counters – In terms of speed, asynchronous counters are quicker than their
synchronous counterparts. They don’t require the clock signal to reach every flip-flop simultaneously.
4. Easier troubleshooting and maintenance – Troubleshooting and maintenance are easier with
asynchronous counters. Their simple design allows for quick identification and resolution of issues.
5. Lower power consumption – They consume less power compared to other counters. This makes them
a more energy-efficient choice, contributing to cost savings in the long run.
Disadvantages of Asynchronous Counter
1. Limited frequency range – Asynchronous counters have a restricted frequency range, which means
they can’t count or operate beyond a certain speed limit.
2. Propagation delay issues – The occurrence of propagation delay is another issue, where the output
doesn’t change instantaneously, causing timing problems.
3. Not suitable for high speed – These counters are not ideal for high-speed operations because the delay
in each flip-flop accumulates, slowing down the overall speed.
4. Difficult to design – Designing asynchronous counters is challenging because each flip-flop must be
individually set up and carefully synchronized.
5. Unpredictable state transitions – Unpredictable state transitions can happen, where the counter may
jump to an unexpected state due to timing issues.

Advantages of Synchronous Counter

 Faster Operation: All the flip-flops in the counter change at the same time, which makes the counter
work faster.
 Precise Timing: Since everything is synchronized, there are fewer timing errors, making the counter
more reliable and accurate.
 Reduced Propagation Delay: There’s no waiting for each flip-flop to trigger the next one, so the
counter has less delay in changing states.
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COMPUTER ARCHITECTURE

 More Reliable: Synchronous counters are more stable because everything happens at the same time,
reducing the chance of errors.
 Better for High-Speed Applications: These counters can handle high-speed operations, making them
suitable for things like fast timers or processing systems.
 Easier to Control: Since all flip-flops are controlled by one clock, it’s easier to manage the timing of
the counter, especially in complex circuits.
Disadvantages of Synchronous Counter
 Complex Design: Synchronous counters are harder to design because they need extra components like a
common clock and control circuits to make sure everything works together.
 Higher Power Consumption: Because all flip-flops change at the same time, it uses more power than
counters where flip-flops change one at a time.
 Requires More Components: You need more parts (like clock drivers and buffers) to make sure
everything stays synchronized, which makes the design more complicated and expensive.

Synchronous Counter Asynchronous Counter

In synchronous counter we use a universal In asynchronous counter main clock is only applied to
clock that is common to all flip flops the first flip flop and then for rest of flip flops the
through out the circuit. output of previous flip flop is taken as a clock.

Synchronous Counter is faster in operation Asynchronous Counter is slower as compared to

as compared to Asynchronous Counter. synchronous counter in operation.

Synchronous Counter does not produce any

Asynchronous Counter produces decoding error.
decoding errors.

Synchronous Counter is also called Parallel

Asynchronous Counter is also called Serial Counter.
Counter.

Synchronous Counter designing as well

Asynchronous Counter designing as well as
implementation are complex due to
implementation is very easy.
increasing the number of states.

Synchronous Counter will operate in any Asynchronous Counter will operate only in fixed count
desired count sequence. sequence (UP/DOWN).

Synchronous Counter examples are: Ring Asynchronous Counter examples are: Ripple UP
counter, Johnson counter. counter, Ripple DOWN counter.

In synchronous counter, propagation delay In asynchronous counter, there is high propagation

is less. delay.

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