Unit-IV

RIPPLE ADDER:

(1): 1-bit full adder:

A one-bit full adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs (Xo, Yo and Ci) and two outputs (S and Co)as illustrated in Figure 1.
The Truth table and gate implementation of 1-bit full adder is shown in Figure 2 & 3.

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RIPPLE CARRY ADDER:

Fig:(4) :

A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascaded, with the carry
output from each full adder connected to the carry input of the next full adder in the chain.
Figure 4 shows the interconnection of four full adder(FA) circuits to provide a 4-bit ripple
carry adder. Notice from Figure 4 that the input is from the right side because the first cell
traditionally represents the least significant bit (LSB). Bits and in the figure represent the
least significant bits of the numbers to be added. The sum output is represented by the bits.

Carry lookahead adder (CLA):

A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead

adder improves speed by reducing the amount of time required to determine carry bits.

The carry look ahead adder (CLA) solves the carry delay problem by calculating the carry
signals in advance, based on the input signals. It is based on the fact that a carry signal will
be generated in two cases:

(1) when both bits aiand bi are 1, or

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(2) when one of the two bits is 1 and the carry-in is 1

Thus, one can write,

The above two equations can be written in terms of two new signals Pi and Gi which are
shown in below figure 5.

Where ,

Gi and Pi are called the carry generate and carry propagate terms, respectively. The
generate and propagate terms only depend on the input bits and thus will be valid after one
and two gate delay, respectively.

If one uses the above expression to calculate the carry signals, one does not need to wait for
the carry to ripple through all the previous stages to find its proper value.

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Let’s apply this to a 4-bit adder to make it clear.

Now implement the carry look ahead generator using above equations.

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N-Bit Parallel Adder

The Full Adder is capable of adding only two single digit binary number along with a carry
input. But in practical we need to add binary numbers which are much longer than just one
bit. To add two n-bit binary numbers we need to use the n-bit parallel adder. It uses a
number of full adders in cascade. The carry output of the previous full adder is connected to
carry input of the next full adder.

4 Bit Parallel Adder

In the block diagram, A0 and B0 represent the LSB of the four bit words A and B. Hence Full
Adder-0 is the lowest stage. Hence its Cin has been permanently made 0. The rest of the
connections are exactly same as those of n-bit parallel adder is shown in fig. The four bit
parallel adder is a very common logic circuit.

Block diagram

N-Bit Parallel Subtractor

The subtraction can be carried out by taking the 1's or 2's complement of the number to be
subtracted. For example we can perform the subtraction (A-B) by adding either 1's or 2's
complement of B to A. That means we can use a binary adder to perform the binary
subtraction.

4 Bit Parallel Subtractor

The number to be subtracted (B) is first passed through inverters to obtain its 1's
complement. The 4-bit adder then adds A and 2's complement of B to produce the
subtraction. S3 S2 S1 S0 represent the result of binary subtraction (A-B) and carry output Cout
represents the polarity of the result. If A > B then Cout =0 and the result of binary form (A-B)
then Cout = 1 and the result is in the 2's complement form.

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Block diagram

Multiplexers

Multiplexer is a special type of combinational circuit. There are n-data inputs, one output
and m select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs
and routes it to the output. The selection of one of the n inputs is done by the selected
inputs. Depending on the digital code applied at the selected inputs, one out of n data
sources is selected and transmitted to the single output Y. E is called the strobe or enable
input which is useful for the cascading. It is generally an active low terminal, that means it
will perform the required operation when it is low.

Block diagram

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Multiplexers come in multiple variations

 2 : 1 multiplexer
 4 : 1 multiplexer
 16 : 1 multiplexer
 32 : 1 multiplexer

Demultiplexers

A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input
and distributes it over several outputs. It has only one input, n outputs, m select input. At a
time only one output line is selected by the select lines and the input is transmitted to the
selected output line. A de-multiplexer is equivalent to a single pole multiple way switch as
shown in fig.

Demultiplexers come in multiple variations

 1 : 2 demultiplexer
 1 : 4 demultiplexer
 1 : 16 demultiplexer
 1 : 32 demultiplexer

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Decoder :-

A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs.

Decoder is identical to a de-multiplexer without any data input. It performs operations
which are exactly opposite to those of an encoder.

Block diagram

2 to 4 Line Decoder : -

The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs
where D through D are the four outputs. Truth table explains the operations of a decoder. It
shows that each output is 1 for only a specific combination of inputs.

Logic Circuit

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3 to 8 DECODER:

Imagine you are a COLLEGE PRINCIPAL. In your office is a very important and unique public
announcement (PA) phone. The phone has three dialing buttons (A, B, C) and is connected
to eight different speakers, as shown in Table 1. Consequently, you get to choose which
section of the college hears your announcement based on the set of buttons you press. For
example, if you press A and B and start speaking into the phone (ABC = 001), DLD sir cabin
(D1) is the only place that can hear you. However, if you press A and C (ABC = 101) then the
Library Room (D5) is the only place that can hear you.

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 TRUTH TABLE

Input Output

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

Fig: Truth table of 3 to 8 Decoder

Such a public announcement phone (or PA system) is an example of a 3-to-8 decoder. Since
the phone has three buttons each of which can either be in one of two possible states —
pressed (=1) or not pressed (= 0) — then the phone can dial eight possible different
numbers (23 = 2*2*2 = 8) as shown in below Table .

A B C COLLEGE AREA
0 0 0 PRINCIPAL ROOM (D0)
0 0 1 DLD Sir CABIN (D1)
0 1 0 CSE HOD ROOM (D2)
0 1 1 DS LAB (D3)
1 0 0 EDC LAB (D4)
1 0 1 LIBRARY (D5)
CLOUD COMPUTING
1 1 0
LAB(D6)
1 1 1 BIG DATA LAB (D7)

Designing such a phone system is straightforward. We just need a switching circuit that
energizes one of the eight output lines based on the combination of the input buttons.

Because each line in the truth table corresponds to a specific output, and because each line
in the table is unique, then we have the eight unique switching expressions that we need:

D0 = A’B’C’

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D1 = A’B’C
D2 = A’BC’
D3 = A’BC
D4 = AB’C’
D5 = AB’C
D6 = ABC’
D7 = ABC

Encoder

Encoder is a combinational circuit which is designed to perform the inverse operation of the
decoder. An encoder has n number of input lines and m number of output lines. An encoder
produces an m bit binary code corresponding to the digital input number. The encoder
accepts an n input digital word and converts it into an m bit another digital word.

Block diagram

Examples of Encoders are following.

 Priority encoders
 Decimal to BCD encoder
 Octal to binary encoder
 Hexadecimal to binary encoder

Priority Encoder

This is a special type of encoder. Priority is given to the input lines. If two or more input line
are 1 at the same time, then the input line with highest priority will be considered. There
are four input D0, D1, D2, D3 and two output Y0, Y1. Out of the four input D3 has the highest
priority and D0 has the lowest priority. That means if D3 = 1 then Y1Y1 = 11 irrespective of the
other inputs. Similarly if D3 = 0 and D2 = 1 then Y1 Y0 = 10 irrespective of the other inputs.

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Block diagram

Truth Table

Logic Circuit

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