uP6109

5V/12V Synchronous-Rectified
Buck Controller with Enable Input
General Description Features
The uP6109 is a compact synchronous-rectified buck † Operate from 5V or 12V Supply Voltage
controller specifically designed to operate from 5V or 12 † 3.3V to 12V VIN Input Range
supply voltage and to deliver high quality output voltage as
† 0.8 VREF with 1.5% Accuracy
low as 0.8V. This (P)SOP-8 device operates at fixed 300
kHz frequency and provides an optimal level of integration † Output Range from VREF to 80% of VIN
to reduce size and cost of the power supply. † Simple Single-Loop Control Design
This controller integrates internal MOSFET drivers that † Voltage-Mode PWM Control
support 12V+12V bootstrapped voltage for high efficiency † Fast Transient Response
power conversion. The bootstrap diode is built-in to simplify † High-Bandwidth Error Amplifier
the circuit design and minimize external part count.
† 0% to 80% Duty Cycle
Other features include internal softstart, undervoltage † Lossless, Programmable Overcurrent Protection
protection, overcurrent protection and shutdown function.
† Uses Lower MOSFET RDS(ON)
With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and † 300 kHz Fixed Frequency Oscillator
cost-effective solutions. This part is available in (P)SOP-8 † Internal Soft Start
packages. † Integrated Bootstrap Diode
Ordering Information Applications
Order Number Package Type Remark † Power Supplies for Microprocessors or
Subsystem Power Supplies
uP6109ASA8 SOP-8
† Cable Modems, Set Top Boxes, and xDSL
uP6109ASU8 PSOP-8 Modems
Note: uPI products are compatible with the current IPC/ † Industrial Power Supplies; General Purpose
JEDEC J-STD-020 and RoHS requirements. They are 100% Supplies
matte tin (Sn) plating and suitable for use in SnPb or Pb-
free soldering processes. † 5V or 12V Input DC-DC Regulators
† Low Voltage Distributed Power Supplies

Pin Configuration & Typical Application Circuit

VIN

VCC
BOOT 1 8 PHASE 5
EN BOOT
UGATE 2 7 EN 7 1

GND 3 6 FB Disable
UGATE
uP6109

LGATE 4 5 VCC Enable 2

SOP-8 VOUT
PHASE
8
BOOT 1 8 PHASE

UGATE 2 7 EN FB LGATE
GND 6 4
GND 3 6 FB
3
LGATE 4 5 VCC GND

PSOP-8 Option

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 uP6109
Functional Pin Description
N o. Pin Name Pin Function
B ootstrap Supply for the floati ng upper gate dri ver. C onnect the bootstrap capaci tor C BOOT
between BOOT pi n and the PHASE pi n to form a bootstrap ci rcui t. The bootstrap capaci tor
1 BOOT
provides the charge to turn on the upper MOSFET. Typical values for CBOOT range from 0.1uF to
0.47uF. Ensure that CBOOT is placed near the IC.
Upper Gate Driver Output. Connect this pin to the gate of upper MOSFET. This pin is monitored
2 UGATE by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has
turned off.
Signal and Pow er Ground for the IC. All voltages levels are measured with respect to this pin.
3 GND
Tie this pin to the ground island/plane through the lowest impedance connection available.
Low er Gate Driver Output. Connect this pin to the gate of lower MOSFET. This pin is monitored
4 LGATE by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turn
off.
Supply Voltage. This pin provides the bias supply for the uP6109 and the lower gate driver. The
supply voltage is internally regulated to 4VDD for internal control circuit. Connect a well-decoupled
5 VC C
4.5V to 13.2V supply voltage to this pin. Ensure that a decoupling capacitor is placed near the
IC.
Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from
6 FB the output to GND is used to set the regulation voltage. Use this pin in combination with the
COMP/EN pin to compensate the voltage control feedback loop of the converter.
Chip Enable. Pulling this pin lower than 0.3V disables the controller and causes the oscillator to
7 EN
stop, the UGATE and LGATE outputs to be held low.
PHASE Sw itch Node. Connect this pin to the source of the upper MOSFET and the drain of the
lower MOSFET. This pin is used as the sink for the UGATE driver, and to monitor the voltage
drop across the lower MOSFET for over current protection. This pin is also monitored by the
8 PHASE
adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off.
A Schottky diode between this pin and ground is recommended to reduce negative transient
voltage which is common in a power supply system.

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 uP6109
Functional Block Diagram
VCC
5

Internal
1 BOOT
4VDD Regulator

2 UGATE
VOCP
Soft
POR
Start OCP
SS Comparator

FB 6 PWM
Error Gate
0.8V
Amplifier Control 8 PHASE
Logic
VCC
VCC

Oscillator 4 LGATE
30K

EN 7 Enable
0.3V

3
GND

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 uP6109
Functional Description
The uP6109 is a compact synchronous-rectified buck
VCC
controller specifically designed to operate from 5V or 12
supply voltage and to deliver high quality output voltage as uP6109
low as 0.8V. This (P)SOP-8 device operates at fixed 300 30kohm
kHz frequency and provides an optimal level of integration
EN
to reduce size and cost of the power supply. Enable
0.3V
Supply Voltage
Disable
The VCC pin receives a well-decoupled 4.5V to 13.2V Enable

supply voltage to power the uP6109 control circuit, the

lower gate driver and the bootstrap circuit for the higher
gate driver. A minimum 0.1uF ceramic capacitor is
Figure 1. Enable Implementation of uP6109.
recommended to bypass the supply voltage. Place the
bypassing capacitor physically near the IC. SoftStart
An internal linear regulator regulates supply voltage into a A built-in Soft Start is used to prevent surge current from
4.0V voltage 4VDD for internal control logic circuit. No power supply input during turn on (referring to the Functional
external bypass capacitor is required for filtering the 4.0VDD Block Diagram). The error amplifier is a three-input device.
voltage. Reference voltage VREF or the internal soft start voltage SS
whichever is smaller dominates the behavior of the non-
The uP6109 integrates MOSFET gate drives that are
inverting input of the error amplifier. SS internally ramps up
powered from the VCC pin and support 12V+12V driving
to 4VDD in 50ms after the softstart cycle is initiated. The
capability. A bootstrap diode is embedded to facilitates PCB
ramp is created digitally, so there will be 100 small discrete
design and reduce the total BOM cost. No external
steps. Accordingly, the output voltage will follow the SS
Schottky diode is required. Converters that consist of
signal and ramp up smoothly to its target level.
uP6109 feature high efficiency without special consideration
on the selection of MOSFETs. The SS signal keeps ramping up after it exceeds the internal
reference VREF. However, the reference voltage VREF takes
Note: The embedded bootstrap diode is not a Schottky
over the behavior of error amplifier after SS > VREF. When
diode having a 0.7V forward voltage. External
the SS signal climb to its ceiling voltage (5V), the uP6109
Schottky diode is highly recommended if the VCC
claims the end of softstart cycle and enable the under
voltage is expected to be lower than 5.0V. Otherwise
voltage protection of the output voltage.
the bootstrap diode may be too low for the device to
work normally. For internal reference voltage, the effective ramp-up time of
the output voltage is about 3.6ms.
Power On Reset and Chip Enable
For the uP6109 (300kHz operation frequency), the soft start
A power on reset (POR) circuitry continuously monitors
is about 2.4ms.
the supply voltage at VCC pin. Once the rising POR
threshold is exceeded, the uP6109 sets itself to active Figure 2 shows a typical start up interval where the EN pin
state and is ready to accept chip enable command. The has been released from a grounded (system shutdown)
rising POR threshold is typically 4.2V at VCC rising. state.
The EN pin is internally pulled high to VCC by a 30kΩ
resistor as shown in Figure 1. A signal level NPN or
NMOSFET transistor is adequate to pull this lower than
0.3V to shut down the device. When EN pin is released, it
is pulled high and clamped to about 1.0V by internal zener
diode.

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 uP6109
Functional Description
OCP level can be calculated according the on-resistance
of the lower MOSFET used.

V IN
VOCP
5V/Div
V OUT IOCP = − (A)
0.5V/Div
RDS(ON)

Connecting a resistance from LGATE to GND selects the

appropriate VOCP as shown in Table 1. Also shown in Table
LGATE
1 is OCP level if a lower MOSFET with 10mΩ RDS(ON) is
5V/Div used.
Table 1. OCP Level Selection
IX
2.5/Div
ROCP (Ω) open 42k 26k 10k
2ms/Div VOCP (mV) -375 -300 -225 -150

Figure 2. Softstart Behavior. IOCP (A) 37.5 30 22.5 15

Power Input Detection When programming the OCP level, take into consideration
The uP6109 detects PHASE voltage for the present of power the conditions that affect RDS(ON) of the lower MOSFET,
input when the UGATE turns on the first time. If the PHASE including operation junction temperature, gate driving voltage
voltage does not exceed 3.0V when the UGATE turns on, and distribution. Consider the RDS(ON) at maximum operation
the uP6109 asserts that power input in not ready and stops temperature and lowest gate driving voltage.
the softstart cycle. However, the internal SS continues Another factor should taken into consideration is the ripple
ramping up to 4VDD. Another softstart is initiated after SS of the inductor current. The current near the valley of the
ramps up to 4VDD. The hiccup period is about 12ms. Figure ripple current is used for OCP, resulting the averaged OCP
3 shows the start up interval where VIN does not present level a little higher than the calculated value.
initially.
Undervoltage Protection (UVP)
The FB voltage is monitored for undervoltage protection.
The UVP threshold level is typical 0.6V for both stand-
alone and tracking mode. The uP6109 shuts down upon
the detection of UVP and can be reset only by POR or
V IN toggling EN pin.
5V/Div

V OUT
5V/Div

LGATE
5V/Div

1ms/Div

Figure 3. Softstart where VIN does not Present Initially.

Overcurrent Protection (OCP)

The uP6109 detects voltage drop across the lower MOSFET

(VPHASE) for overcurrent protection when it is turn on. If VPHASE
is lower than the user-programmable voltage VOCP, the
uP6109 asserts OCP and shuts down the converter. The

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 uP6109
Absolute Maximum Rating
Supply Input Voltage, VCC (Note 1) ------------------------------------------------------------------------------------------------ -0.3V to +15V
PHASE to GND
DC ------------------------------------------------------------------------------------------------------------------------------------- -5V to 15V
< 200ns ---------------------------------------------------------------------------------------------------------------------------- -5V to 30V
BOOT to PHASE -------------------------------------------------------------------------------------------------------------------------------------- 15V
BOOT to GND
DC ------------------------------------------------------------------------------------------------------------------------- -0.3V to PHASE +15V
< 200ns -------------------------------------------------------------------------------------------------------------------------- -0.3V to 42V
Input, Output or I/O Voltage ---------------------------------------------------------------------------------------------------------- -0.3V to +6V
Storage Temperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V

Thermal Information
Package Thermal Resistance (Note 3)
SOP-8 θJA----------------------------------------------------------------------------------------------------------------------------------- 160°C/W
PSOP-8 θJA---------------------------------------------------------------------------------------------------------------------------------- 50°C/W
PSOP-8 θJC---------------------------------------------------------------------------------------------------------------------------------- 15°C/W
Power Dissipation, PD @ TA = 25°C
SOP-8 ------------------------------------------------------------------------------------------------------------------------------------------- 0.625W
PSOP-8 ------------------------------------------------------------------------------------------------------------------------------------------------- 2.0W

Recommended Operation Conditions

Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C
Operating Ambient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C
Supply Input Voltage, VCC ---------------------------------------------------------------------------------------------------------------- +4.5V to 13.2V

Electrical Characteristics
O
(VCC = 12V, TA = 25 C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Units

Supply Input
Supply Voltage VCC 4.5 -- 13.2 V
Supply Current ICC UGATE, LGATE Open; VCC = 12V, Switching -- 4 -- mA
Quiescent Supply Current ICC_Q VFB = 0.9V, No Switching -- 3 -- mA
Power Input Voltage VIN 3.0 -- 13.2 V
Pow er On Reset
POR Threshold VCCRTH VCC rising 4.0 4.2 4.4 V
POR Hysteresis VCCHYS -- 0.2 -- V
Oscillator
Free Running Frequency fOSC V C C = 12V 255 300 345 kHz
Ramp Amplitude ΔVOSC V C C = 12V -- 1.5 -- VP-P

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 uP6109
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Units
Error Amplifier
Open Loop DC Gain AO Guaranteed by Design 55 70 -- dB
Gain-Bandwidth Product GBW Guaranteed by Design -- 10 -- MHz
Slew Rate SR Guaranteed by Design 3 6 -- V/us
Transconductance Guaranteed by Design -- -- 0.7 mS
PWM Controller Gate Drivers

Upper Gate Sourcing Current IUG_SRC VBOOT - VPHASE = 12V, VBOOT - VUGATE = 6V -- -1 -- A

Upper Gate RDS(ON) Sinking RUG_SNK VUGATE - VPHASE = 0.1V -- 2 4 Ω

Lower Gate Sourcing Current ILG_SRC VCC - VLGATE = 6V -- -1 -- A

Lower Gate RDS(ON) Sinking RLG_SNK VLGATE = 0.1V -- 2 4 Ω

PHASE Falling to LGATE Rising
VCC = 12V; VPHASE < 1.2V to VLGATE > 1.2V -- 30 -- ns
Delay
LGATE Falling to UGATE Rising VCC = 12V; VLGATE < 1.2V to (VUGATE - VPHASE
-- 30 -- ns
Delay ) > 1.2V
Reference Voltage

Nominal Feedback Voltage V FB Stand Alone Mode 0.788 0.8 0.812 V

Enable Threshold

Enable Threshold VENRTH VEN rising. 0.6 -- -- V

Disable Threshold VENFTH VEN falling. -- -- 0.3 V

Protection

Under Voltage Protection VFB_UVP 0.55 0.6 0.65 V

Over Current Threshold VPHASE RLGATE Open -- -375 -- mV

Soft-Start Interval TSS 2.4 3.6 4.8 ms

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.

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 uP6109
Typical Operation Characteristics
Power On Waveforms Turn On Waveforms

VIN EN
5V/Div 0.5V/Div VOUT
V OUT
0.5V/Div 0.5V/Div

LGATE LGATE
5V/Div 5V/Div

IX
2.5/Div IX
2.5A/Div

2ms/Div 2ms/Div
VIN =12V, VOUT = 1.2V, COUT = 1500uF, No Load VIN =12V, VOUT = 1.2V, COUT = 1500uF, No Load

Turn Off Waveforms Switching Waveforms: UGATE Turn On

UGATE
5V/Div
VOUT
0.5V/Div
LGATE
10V/Div LGATE PHASE
5V/Div 5V/Div

IX
10A/Div UGATE - PHASE
5V/Div

EN
1V/Div

10us/Div 25ns/Div
VIN = 12V, VOUT = 1.2V, COUT = 1500uF, IOUT = 6A VIN = 12V, IOUT = 10A

Switching Waveforms: UGATE Trun Off Power Sequencing Operation

UGATE
5V/Div VIN
5V/Div
UGATE - PHASE
LGATE
5V/Div
5V/Div
VOUT
PHASE 5V/Div
5V/Div

LGATE
5V/Div

25ns/Div 1ms/Div
VIN = 12V, IOUT = 10A VCC =12V Ready, VOUT = 1.2V, COUT = 1500uF, No Load

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 uP6109
Typical Operation Characteristics
Load Transient Response Over Current Protection

IOUT
10A/Div

VOUT
0.5V/Div
VOUT
5V/Div

PHASE
5V/Div
PHASE
10V/Div

IX
20A/Div

10us/Div 5ms/Div, VIN = 12V, VOUT = 1.2V, COUT = 1500uF,

VIN =12V, VOUT = 1.2V, COUT = 1500uF Turn On to Short Circuit

Over Current Protection Line Regulation

0.5
0.4
Output Voltage Deviation (%)

0.3
VOUT
0.2
0.5V/Div
0.1
0
PHASE
-0.1
5V/Div
-0.2
-0.3
IX -0.4
20A/Div
-0.5
4 6 8 10 12 14

5ms/Div, VIN = 12V, VOUT = 1.2V, COUT = 1500uF, Input Voltage (V)
Output Short to Ground

Load Regulation Output Voltage vs. Junction Temperature

0.3 3
0.2 2.5
Output Voltage Deviation (%)

2
Output Voltage Varition (%)

0.1
1.5
0
1
-0.1 0.5
-0.2 0
-0.3 -0.5
-1
-0.4
-1.5
-0.5
-2
-0.6 -2.5
-0.7 -3
0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125

Output Current (A) Junction Temperature (OC)

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 uP6109
Typical Operation Characteristics
Switching Frequency vs. Input Voltage Switching Frequency vs. Junction Temperature
225 225
220 220
Switching Frequency (kHz)

Switching Frequency (kHz)

215 215
210 210
205 205
200 200
195 195
190 190
185 185
180 180
175 175
4 6 8 10 12 14 -50 -25 0 25 50 75 100 125

Input Voltage (V) Junction Temperature (OC)

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 uP6109
Application Information
Power MOSFET Selection Both MOSFETs have I2R losses and the top MOSFET
External component selection is primarily determined by includes an additional term for switching losses, which are
the maximum load current and begins with the selection of largest at high input voltages. The bottom MOSFET losses
power MOSFET switches. The uP6109 requires two are greatest when the bottom duty cycle is near 100%,
external N-channel power MOSFETs for upper (controlled) during a short-circuit or at high input voltage. These
and lower (synchronous) switches. Important parameters equations assume linear voltage current transitions and do
for the power MOSFETs are the breakdown voltage V(BR)DSS, not adequately model power loss due the reverse-recovery
on-resistance RDS(ON), reverse transfer capacitance CRSS, of the lower MOSFET’s body diode. Ensure that both
maximum current IDS(MAX), gate supply requirements, and MOSFETs are within their maximum junction temperature
thermal management requirements. at high ambient temperature by calculating the temperature
rise according to package thermal-resistance
The gate drive voltage is powered by VCC pin that receives specifications. A separate heatsink may be necessary
4.5V~13.2V supply voltage. When operating with a 12V depending upon MOSFET power, package type, ambient
power supply for VCC (or down to a minimum supply temperature and air flow.
voltage of 8V), a wide variety of NMOSFETs can be used.
Logic-level threshold MOSFET should be used if the input The gate-charge losses are dissipated by the uP6109 and
voltage is expected to drop below 8V. Since the lower don’t heat the MOSFETs. However, large gate charge
MOSFET is used as the current sensing element, particular increases the switching interval, TSW that increases the
attention must be paid to its on-resistance. Look for RDS(ON) MOSFET switching losses. The gate-charge losses are
ratings at lowest gate driving voltage. calculated as:

Special cautions should be exercised on the lower switch PG = VCC × ( VCC × (CISS _ UP + CISS _ LO ) + VIN × CRSS ) × fOSC
exhibiting very low threshold voltage VGS(TH). The shoot-
through protection present aboard the uP6109 may be where CISS_UP is the input capacitance of the upper
circumvented by these MOSFETs if they have large MOSFET, CISS_LO is the input capacitance of the lower
parasitic impedances and/or capacitances that would inhibit MOSFET, and CRSS_UP is the reverse transfer capacitance
the gate of the MOSFET from being discharged below its of the upper MOSFET. Make sure that the gate-charge loss
threshold level before the complementary MOSFET is will not cause over temperature at uP6109, especially with
turned on. Also avoid MOSFETs with excessive switching large gate capacitance and high supply voltage.
times; the circuitry is expecting transitions to occur in under Output Inductor Selection
50 nsec or so.
Output inductor selection usually is based the
In high-current applications, the MOSFET power considerations of inductance, rated current, size
dissipation, package selection and heatsink are the requirement, and DC resistance (DC)
dominant design factors. The power dissipation includes
Given the desired input and output voltages, the inductor
two loss components; conduction loss and switching loss.
value and operating frequency determine the ripple current:
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs. 1 V
ΔIL = × VOUT × (1 − OUT )
These losses are distributed between the two MOSFETs fOSC × L OUT VIN
according to duty cycle. Since the uP6109 is operating in
Lower ripple current reduces core losses in the inductor,
continuous conduction mode, the duty cycles for the
ESR losses in the output capacitors and output voltage
MOSFETs is:
ripple. Highest efficiency operation is obtained at low
VOUT VIN − VOUT frequency with small ripple current. However, achieving this
DUP = DLO = requires a large inductor. There is a tradeoff between
VIN VIN
; component size, efficiency and operating frequency. A
The resulting power dissipation in the MOSFETs at reasonable starting point is to choose a ripple current that
maximum output current are: is about 40% of IOUT(MAX).
2
PUP = IOUT × RDS(ON) × DUP + 0.5 × IOUT × VIN × TSW × fOSC There is another tradeoff between output ripple current/
voltage and response time to a transient load. Increasing
2
PLO = IOUT × RDS(ON) × DLO the value of inductance reduces the output ripple current
and voltage. However, the large inductance values reduce
where TSW is the combined switch ON and OFF time. the converter’s response time to a load transient.

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 uP6109
Application Information
Maximum current ratings of the inductor are generally manufacturer’s ripple current ratings are often based on
specified in two methods: permissible DC current and 2000 hours of life. This makes it advisable to further derate
saturation current. Permissible DC current is the allowable the capacitor, or choose a capacitor rated at a higher
DC current that causes 40OC temperature raise. The temperature than required. Always consult the manufacturer
saturation current is the allowable current that causes 10% if there is any question.
inductance loss. Make sure that the inductor will not For a through-hole design, several electrolytic capacitors
saturate over the operation conditions including temperature may be needed. For surface mount designs, solid tantalum
range, input voltage range, and maximum output current. capacitors can also be used, but caution must be exercised
The size requirements refer to the area and height with regard to the capacitor surge current rating. These
requirement for a particular design. For better efficiency, capacitors must be capable of handling the surge-current
choose a low DC resistance inductor. DCR is usually at power-up. Some capacitor series available from reputable
inversely proportional to size. manufacturers are surge current tested.
Different core materials and shapes will change the size/ Output Capacitor Selection
current and price/current relationship of an inductor. Toroid An output capacitor is required to filter the output and supply
or shielded pot cores in ferrite or permalloy materials are the load transient current. The selection of COUT is primarily
small and don’t radiate much energy, but generally cost determined by the ESR required to minimize voltage ripple
more than powdered iron core inductors with similar electrical and load step transients. The output ripple ΔVOUT is
characteristics. The choice of which style inductor to use approximately bounded by:
often depends more on the price vs. size requirements
and any radiated field/EMI requirements. 1
ΔVOUT ≤ ΔIL (ESR + )
Input Capacitor Selection 8 × fOSC × C OUT

The synchronous-rectified buck converter draws pulsed Since ΔIL increases with input voltage, the output ripple is
current with sharp edges from the input capacitor resulting highest at maximum input voltage. Typically, once the ESR
in ripples and spikes at the input supply voltage. Use a requirement is satisfied, the capacitance is adequate for
mix of input bypass capacitors to control the voltage filtering and has the necessary RMS current rating. Multiple
overshoot across the MOSFETs. Use small ceramic capacitors placed in parallel may be needed to meet the
capacitors for high frequency decoupling and bulk capacitors ESR and RMS current handling requirements. Dry tantalum,
to supply the current needed each time upper MOSFET special polymer, aluminum electrolytic and ceramic
turns on. Place the small ceramic capacitors physically capacitors are all available in surface mount packages.
close to the MOSFETs and between the drain of upper Special polymer capacitors offer very low ESR but have
MOSET and the source of lower MOSFET to avoid the lower capacitance density than other types.
stray inductance along the connection trace. The load transient requirements are a function of the slew
The important parameters for the bulk input capacitor are rate (di/dt) and the magnitude of the transient load current.
the voltage rating and the RMS current rating. For reliable These requirements are generally met with a mix of
operation, select the bulk capacitor with voltage and current capacitors and careful layout. Modern components and
ratings above the maximum input voltage and largest RMS loads are capable of producing transient load rates above
1A/ns. High frequency capacitors initially supply the
current required by the circuit. The capacitor voltage rating
transient and slow the current load rate seen by the bulk
should be at least 1.25 times greater than the maximum
capacitors. The bulk filter capacitor values are generally
input voltage and a voltage rating of 1.5 times is a
determined by the ESR (Effective Series Resistance) and
conservative guideline. The RMS current rating requirement
voltage rating requirements rather than actual capacitance
for the input capacitor of a buck converter is calculated as:
requirements.
VOUT ( VIN − VOUT ) High frequency decoupling capacitors should be placed as
IIN(RMS) = IOUT(MAX ) close to the power pins of the load as physically possible.
VIN
Be careful not to add inductance in the circuit board wiring
This formula has a maximum at VIN = 2VOUT, where IIN(RMS) that could cancel the usefulness of these low inductance
= I OUT(RMS) /2. This simple worst-case condition is components. Consult with the manufacturer of the load on
commonly used for design because even significant
deviations do not offer much relief. Note that the capacitor

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 uP6109
Application Information
specific decoupling requirements. 2 Place the power components as physically close as
Use only specialized low-ESR capacitors intended for possible.
switching-regulator applications for the bulk capacitors. The 2.1 Place the input capacitors, especially the high-
bulk capacitor’s ESR will determine the output ripple frequency ceramic decoupling capacitors, directly
voltage and the initial voltage drop after a high slew-rate to the drain of upper MOSFET ad the source of the
transient. An aluminum electrolytic capacitor’s ESR value lower MOSFET. To reduce the ESR replace the
is related to the case size with lower ESR available in single input capacitor with two parallel units
larger case sizes. 2.2 Place the output capacitor between the converter
However, the Equivalent Series Inductance (ESL) of these and load.
capacitors increases with case size and can reduce the 3 Place the uP6109 near the upper and lower MOSFETs
usefulness of the capacitor to high slew-rate transient with pins 1 to 4 facing the power components. Keep
loading. the components connected to pins 4 to 8 close to the
Unfortunately, ESL is not a specified parameter. Work with uP6109 and away from the inductor and other noise
your capacitor supplier and measure the capacitor’s sources (noise sensitive components).
impedance with frequency to select a suitable component. 4 Use a dedicated grounding plane and use vias to ground
In most cases, multiple electrolytic capacitors of small case all critical components to this layer. The ground plane
size perform better than a single large case capacitor. layer should not have any traces and it should be as
Bootstrap Capacitor Selection close as possible to the layer with power MOSFETs.
An external bootstrap capacitor CBOOT connected to the Use an immediate via to connect the components to
BOOT pin supplies the gate drive voltage for the upper ground plane including GND of uP6109 Use several
MOSFET. This capacitor is charged through the internal bigger vias for power components.
diode when the PHASE node is low. When the upper 5 Apply another solid layer as a power plane and cut this
MOSFET turns on, the PHASE node rises to VIN and the plane into smaller islands of common voltage levels.
BOOT pin rises to approximately VIN + VCC. The boot The power plane should support the input power and
capacitor needs to store about 100 times the gate charge output power nodes to maintain good voltage filtering
required by the upper MOSFET. In most applications 0.1uF and to keep power losses low. Also, for higher currents,
to 0.47uF, X5R or X7R dielectric capacitor is adequate. it is recommended to use a multilayer board to help
PCB Layout Considerations with heat sinking power components.

High speed switching and relatively large peak currents in 6 The PHASE node is subject to very high dV/dt voltages.
a synchronous-rectified buck converter make the PCB layout Stray capacitance between this island and the
a very important part of design. Fast current switching from surrounding circuitry tend to induce current spike and
one device to another in a synchronous-rectified buck capacitive noise coupling. Keep the sensitive circuit
converter causes voltage spikes across the interconnecting away from the PHASE node and keep the PCB area
impedances and parasitic circuit elements. The voltage small to limit the capacitive coupling. However, the PCB
spikes can degrade efficiency and radiate noise that result area should be kept moderate since it also acts as
in overvoltage stress on devices. Careful component main heat convection path of the lower MOSFET.
placement layout and printed circuit design minimizes the 7 uP6109 sources/sinks impulse current with 2A peak to
voltage spikes induced in the converter. turn on/off the upper and lower MOSFETs. The
Follow the layout guidelines for optimal performance of connecting trance between the controller and gate/
uP6109 source of the MOSFET should be wide and short to
minimize the parasitic inductance along the traces.
1 The upper and lower MOSFETs turn on/off and conduct
pulsed current alternatively with high slew rate transition. 8 Flood all unused areas on all layers with copper.
Any inductance in the switched current path generates Flooding with copper will reduce the temperature rise
a large voltage spike during the switching. The of power component.
interconnecting wires indicated by red heavy lines 9 Provide local VCC decoupling between VCC and GND
conduct pulsed current with sharp transient and should pins. Locate the capacitor, CBOOT as close as practical
be part of a ground or power plane in a printed circuit to the BOOT and PHASE pins.
board to minimize the voltage spike. Make all the
connection the top layer with wide, copper filled areas.
uPI Semiconductor Corp., http://www.upi-semi.com 13
Rev. F00, File Name: uP6109-DS-F0000

Free Datasheet http://www.Datasheet4U.com

 uP6109
Package Information
SOP - 8 Packagke

0.76 REF 1.27 REF

1.85 REF
4.80 - 5.00

5.80 - 6.20
3.80 - 4.00
6.15 REF
8.00 MIN

4.00 MIN

1.27 BSC 0.32 - 0.52

Recommended Solder Pad Layout

1.45 - 1.60

0.20 BSC 0.18 - 0.25 1.75 MAX

0.10 - 0.25

0.41 - 0.89 3.81 BSC

Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.

uPI Semiconductor Corp., http://www.upi-semi.com 14

Rev. F00, File Name: uP6109-DS-F0000

Free Datasheet http://www.Datasheet4U.com

 uP6109
Package Information
PSOP - 8 Packagke

4.80 - 5.00
0.70 REF 1.27 REF
3.00 BSC

1.50 REF
3.00 REF

5.80 - 6.20
3.80 - 4.00
7.00 REF

2.20 REF
5.50 REF

2.20 BSC
4.00 REF

1.27 BSC 0.32 - 0.52

Recommended Solder Pad Layout

1.45 - 1.60

0.20 BSC 0.18 - 0.25 1.75 MAX

0.05 - 0.25

0.40 - 0.90 3.81 BSC

Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.

uPI Semiconductor Corp., http://www.upi-semi.com 15

Rev. F00, File Name: uP6109-DS-F0000

Free Datasheet http://www.Datasheet4U.com