LM76005-Q1

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LM76005-Q1 3.5-V to 60-V, 5-A Automotive Synchronous Step-Down Converter

1 Features 2 Applications
• AEC-Q100 qualified for automotive applications • Automotive ADAS with support for 24-V battery
– Temperature grade 1: –40°C to +125°C, TA • Infotainment and cluster
• Functional Safety-Capable • HEV/EV
– Documentation available to aid functional safety
3 Description
system design
• Designed for automotive applications The LM76005-Q1 regulator is an easy-to-use
– Input transient protection up to 65 V synchronous step-down DC-DC converter capable of
driving up to 5 A (LM76005-Q1) of load current from
– Optimized for low EMI requirements
an input up to 60 V. Tolerance goes up to 65 V, easing
– Pin-selectable FPWM operation input surge protection.
– Adjustable frequency range: 200 kHz to 500
kHz The LM76005-Q1 use peak-current-mode control to
– Start up with pre-biased output voltage provide exceptional efficiency and output accuracy in
a small solution size. Seamless transition between
– Protection features: thermal shutdown, input
PWM and PFM modes, along with very low MOSFET
undervoltage lockout, cycle-by-cycle current
ON resistances and an external bias input, ensures
limit, hiccup short-circuit protection
exceptional efficiency across the entire load range.
• Suited for scalable power supplies
– Pin compatible with: This device requires few external components and
• LM76002/3-Q1 (60 V, 2.5 A or 3.5 A) has a pinout designed for simple PCB layout with
best-in-class EMI (CISPR25) and thermal
– Output voltage: 1 V to 95% of VIN
performance. The small solution size and feature set
– Synchronization to external clock of the LM76005-Q1 are designed to simplify the
– Adjustable soft-start (6.3 ms default) implementation for a wide range of end equipment.
• Low power dissipation across load spectrum
The LM76005-Q1 device is available in the WQFN 30-
– 15-µA quiescent current in regulation
pin leadless package with wettable flanks.
– 95% efficiency at 400 kHz (12VIN, 5VOUT, 2A)
– 92% PFM efficiency at 10-mA (12VIN, 5VOUT) Device Information
– External bias option for improved efficiency PART NUMBER (1) PACKAGE BODY SIZE (NOM)

• Create a custom design using the LM76005-Q1 LM76005-Q1 WQFN (30) 6.00 mm × 4.00 mm
with the WEBENCH® Power Designer (1) For all available packages, see the orderable addendum at
the end of the data sheet.
100

VIN PVIN BOOT 98

CBOOT 96
CIN EN SW VOUT 94
Efficiency (%)

L 92
COUT
PGND 90

LM76005-Q1 88
86
VCC BIAS 84
82 VIN = 12 V
RFBT VIN = 24 V
C2
80
FB 0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 45
Load Current (A)
RFBB LM76
AGND
Efficiency: VOUT = 5 V, fSW = 400 kHz, Auto Mode

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Table of Contents
1 Features............................................................................1 7.3 Feature Description...................................................12
2 Applications..................................................................... 1 7.4 Device Functional Modes..........................................19
3 Description.......................................................................1 8 Application and Implementation.................................. 21
4 Revision History.............................................................. 2 8.1 Application Information............................................. 21
5 Pin Configuration and Functions...................................3 8.2 Typical Applications.................................................. 21
Pin Functions.................................................................... 4 9 Power Supply Recommendations................................34
6 Specifications.................................................................. 5 10 Layout...........................................................................35
6.1 Absolute Maximum Ratings........................................ 5 10.1 Layout Guidelines................................................... 35
6.2 ESD Ratings............................................................... 5 10.2 Layout Example...................................................... 38
6.3 Recommended Operating Conditions.........................5 11 Device and Documentation Support..........................39
6.4 Thermal Information....................................................6 11.1 Device Support........................................................39
6.5 Electrical Characteristics.............................................6 11.2 Receiving Notification of Documentation Updates.. 39
6.6 Timing Characteristics.................................................8 11.3 Support Resources................................................. 39
6.7 Switching Characteristics............................................8 11.4 Trademarks............................................................. 39
6.8 System Characteristics............................................... 9 11.5 Electrostatic Discharge Caution.............................. 39
6.9 Typical Characteristics.............................................. 10 11.6 Support Resources................................................. 39
7 Detailed Description...................................................... 11 12 Mechanical, Packaging, and Orderable
7.1 Overview................................................................... 11 Information.................................................................... 39
7.2 Functional Block Diagram......................................... 11

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (February 2020) to Revision A (July 2020) Page

• Changed device status from Advance Information to Production Data.............................................................. 1
• Updated the numbering format for tables, figures and cross-references throughout the document...................1

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5 Pin Configuration and Functions

NC NC NC NC

30 29 28 27

SW 1 26 PGND

SW 2 25 PGND

SW 3 24 PGND

SW 4 23 NC

SW 5 22 PVIN

BOOT 6 DAP 21 PVIN

NC 7 20 PVIN

VCC 8 19 NC

BIAS 9 18 EN

RT 10 17 SYNC/MODE

SS/TRK 11
16 PGOOD

12 13 14 15

FB AGND AGND AGND

Figure 5-1. RNP Package 30-Pin WQFN Top View

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Pin Functions
PIN
I/O(1) DESCRIPTION
NO. NAME
Switching output of the regulator. Internally connected to the source of the HS FET and
1, 2, 3, 4, 5 SW P
drain of the LS FET. Connect to power inductor and bootstrap capacitor.
Bootstrap capacitor connection for high-side driver. Connect a high-quality 470-nF capacitor
6 BOOT P
from this pin to the SW pin.
Not internally connected. Connect pins 19, 27, 28, 29, and 30 to ground copper on PCB to
7, 19, 23, 27,
NC — improve heat-sinking of the device and board level reliability. Leave pins 7 and 23 floating in
28, 29, 30
order to maximize distance from the high voltage input to ground.
Output of internal bias supply. Used as supply to internal control circuits. Connect a high-
8 VCC P quality 2.2-µF capacitor from this pin to GND. TI does not recommended loading this pin by
external circuitry.
Optional BIAS LDO supply input. TI recommends tying this to VOUT when 3.3 V ≤ VOUT ≤ 18
9 BIAS P V, or tying to an external 3.3-V or 5-V rail if available, to improve efficiency. When used,
place a 1-µF capacitor from this terminal to ground. Tie to ground when not in use.
Switching frequency setting pin. Place a resistor from this pin to ground to set the switching
10 RT A
frequency. If floating, the default switching frequency is 400 kHz. Do not short to ground.
Soft-start control pin. Leave this pin floating to use the 6.3-ms internal soft-start ramp. An
external capacitor can be connected from this pin to ground to extend the soft-start time. A
11 SS/TRK A
2-µA current sourced from this pin can charge the capacitor to provide the ramp. Connect to
external ramp for tracking. Do not short to ground.
Feedback input for output voltage regulation. Connect a resistor divider to set the output
12 FB A
voltage. Never short this terminal to ground during operation.
Open-drain power-good flag output. Connect to suitable voltage supply through a current
16 PGOOD A limiting resistor. High = VOUT regulation OK, Low = VOUT regulation fault. PGOOD = Low
when EN = Low
Synchronization input and mode setting pin. Do not float, tie to ground if not used.
Tie to ground: DCM/PFM operation under light loads, improved efficiency
Tie to logic high: forced PWM under light loads, constant switching frequency over load
17 SYNC/MODE A
Tie to external clock source: synchronize switching action to the clock, forced PWM under
light loads.
Triggers on the rising edge of external clock.
Precision-enable input to regulator. Do not float. High = on, Low = off. Can be tied to VIN.
18 EN A
Precision-enable input allows adjustable UVLO by external resistor divider.
Analog ground. Ground reference for internal references and logic. All electrical parameters
13, 14, 15 AGND G
are measured with respect to this pin. Connect to system ground on PCB.
Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass
20, 21, 22 PVIN P capacitors CIN. CIN must be placed right next to this pin and PGND and connected with
short traces.
Power ground, connected to the source of LS FET internally. Connect to system ground,
24, 25, 26 PGND G DAP/EP, AGND, and ground side of CIN and COUT. Path to CIN must be as short as
possible.
Low impedance connection to AGND. Connect to system ground on PCB. Major heat
EP DAP — dissipation path for the die. Must be used for heat sinking by soldering to ground copper on
PCB. Thermal vias are preferred.

(1) A = Analog, O = Output, I = Input, G = Ground, P = Power

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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range of –40°C to +125°C (unless otherwise noted)(1)
PARAMETER MIN MAX UNIT
PVIN to PGND –0.3 65
EN to AGND –0.3 VIN + 0.3
FB, RT, SS/TRK to AGND –0.3 5
Input voltages PGOOD to AGND –0.1 20 V
SYNC to AGND –0.3 5.5
BIAS to AGND –0.3 Lower of (VIN + 0.3) or 30
AGND to PGND –0.3 0.3
SW to PGND –0.3 VIN + 0.3
SW to PGND less than 10-ns transients –3.5 65
Output voltages V
BOOT to SW –0.3 5.5
VCC to AGND –0.3 5.5
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±2000 V
V(ESD) Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011 ±500 V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of -40°C to 125°C (unless otherwise noted)(1)
MIN MAX UNIT
PVIN to PGND 3.5 60
EN 0 VIN
FB 0 4.5
PGOOD 0 18
Input voltages V
BIAS input not used 0 0.3
Lower of (VIN + 0.3)
BIAS input used 0
or 24
AGND to PGND –0.1 0.1
Switching
FSW 200 500 kHz
Frequency
Output voltage VOUT 1 95% of VIN V
Output current IOUT 0 5 A
Temperature Operating junction temperature, TJ –40 125 °C

(1) Recommended operating rating indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics Table.

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6.4 Thermal Information

LM76005-Q1
THERMAL METRIC(1) RNP (WQFN) UNIT
30 PINS
RθJA Junction-to-ambient thermal resistance 29.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.6 °C/W
RθJB Junction-to-board thermal resistance 9.1 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 9.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.0 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless
otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only. Unless otherwise stated, the following conditions apply: VIN = 24 V, VOUT = 3.3 V, fSW = 400 kHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (PVIN PINS)
Operating input voltage
VIN 3.5 60 V
range
Shutdown quiescent current;
ISD VEN = 0 V 1.2 10 µA
measured at PVIN pin(1)
Operating quiescent current VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V
IQ_NONSW 2 12 µA
from VIN (non-switching) external
ENABLE (EN PIN)
Enable input high level for
VEN_VCC_H VEN rising 1.2 V
VCC output
Enable input low level for
VEN_VCC_L VEN falling 0.3 V
VCC output
Enable input high level for
VEN_VOUT_H VEN rising 1.14 1.204 1.25 V
VOUT
Enable input hysteresis for
VEN_VOUT_HYS VEN falling hysteresis –150 mV
VOUT
ILKG_EN Enable input leakage current VEN = 2 V 1.4 200 nA
INTERNAL LDO (VCC PIN, BIAS PIN)
PWM operation 3.29 V
VCC Internal VCC voltage
PFM operation 3.1 V

Internal VCC undervoltage VCC rising 2.96 3.14 3.27 V

VCC_UVLO
lockout VCC falling hysteresis –565 mV
VBIAS rising 3.11 3.25 V
VBIAS_ON Input change over
VBIAS falling hysteresis –63 mV
Operating quiescent current
VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 V
IBIAS_NONSW from external VBIAS (non- 21 50 µA
external
switching)
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage PWM mode 0.987 1.006 1.017 V
Input leakage current at FB
ILKG_FB VFB = 1 V 0.2 60 nA
pin

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Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless
otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only. Unless otherwise stated, the following conditions apply: VIN = 24 V, VOUT = 3.3 V, fSW = 400 kHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HIGH SIDE DRIVER (BOOT PIN)
BOOT - SW undervoltage
VBOOT_UVLO 1.6 2.2 2.7 V
lockout
CURRENT LIMITS AND HICCUP
Short-circuit, high-side
IHS_LIMIT(2) 6.0 6.8 7.8 A
current limit
ILS_LIMIT (2) Low-side current limit 4.5 5.1 5.8 A
INEG_LIMIT Negative current limit –4.1 A
VHICCUP Hiccup threshold on FB pin 0.38 0.42 0.46 V
IL_ZC Zero cross-current limit 0.05 A
SOFT START (SS/TRK PIN)
ISSC Soft-start charge current 1.8 2 2.2 µA
Soft-start discharge
RSSD UVLO, TSD, OCP; or EN = 0 V 2 kΩ
resistance
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION
Power-good overvoltage
VPGOOD_OV % of FB voltage 106% 110% 113%
threshold
Power-good undervoltage
VPGOOD_UV % of FB voltage 86% 90% 93%
threshold
VPGOOD_HYS Power-good hysteresis % of FB voltage 2.5%
Minimum input voltage for
VPGOOD_VALID 50-µA pullup to PGOOD pin, VEN = 0 V 1.3 2 V
proper PGOOD function
VEN = 2.5 V 40 100
RPGOOD Power-good on-resistance Ω
VEN = 0 V 30 90
MOSFETS
High-side MOSFET on-
RDS_ON_HS (3) IOUT = 1 A, VBIAS = VOUT = 3.3 V 95 150 mΩ
resistance
Low-side MOSFET on-
RDS_ON_LS (3) IOUT = 1 A, VBIAS = VOUT = 3.3 V 45 85 mΩ
resistance
THERMAL SHUTDOWN
Thermal shutdown threshold Shutdown threshold 150 °C
TSD (4)
Recovery threshold 135 °C

(1) Shutdown current includes leakage current of the switching transistors.

(2) This current limit was measured as the internal comparator trip point. Due to inherent delays in the current limit comparator and
drivers, the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower.
(3) Measured at pins.
(4) Ensured by design.

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6.6 Timing Characteristics

MIN NOM MAX UNIT
CURRENT LIMITS AND HICCUP
Number of switching cycles
NOC (1) 128 Cycles
before hiccup is tripped
Overcurrent hiccup retry delay
tOC 46 ms
time
SOFT START (SS/TRK PIN)
CSS = OPEN, from EN rising
tSS Internal soft-start time 3.5 6.3 ms
edge to PGOOD rising edge
POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION
PGOOD rising edge deglitch
tPGOOD_RISE 80 140 200 µs
delay
PGOOD falling edge deglitch
tPGOOD_FALL 80 140 200 µs
delay

(1) Ensured by design

6.7 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PWM LIMITS (SW PINS)
tON-MIN Minimum switch on-time 65 95 ns
tOFF-MIN Minimum switch off-time 95 130 ns
tON-MAX Maximum switch on-time HS timeout in dropout 3.8 8 11.4 µs
OSCILLATOR (RT and SYNC PINS)
fADJ Adjustable frequency by RT or SYNC RT =133 kΩ, 0.1% 270 300 330 kHz
fOSC Internal oscillator frequency RT = Open 350 400 450 kHz
VSYNC_HIGH Sync input high level threshold 2 V
VSYNC_LOW Sync input low level threshold 0.4 V
Mode input high level threshold for
VMODE_HIGH 0.42 V
FPWM
Mode input low level threshold for
VMODE_LOW 0.4 V
AUTO mode
tSYNC_MIN Sync input minimum on- and off-time 80 ns

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6.8 System Characteristics

The following specifications apply to the circuit found in the typical application schematic with appropriate
modifications. These parameters are not tested in production and represent typical performance only. Unless
otherwise stated the following conditions apply: TA = 25°C, VIN = 24 V, VOUT = 3.3 V, fSW = 400 kHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output voltage offset at no load VIN = 3.8 V to 36 V, VSYNC = 0 V, auto mode
VFB_PFM 2%
in auto mode IOUT = 0 A
Minimum input to output
Vdrop voltage differential to maintain VOUT = 5 V, IOUT = 1.5 A, fSW = 400 kHz 0.65 V
specified accuracy
Operating quiescent current VEN = 3.3 V, IOUT = 0 A, RT = open, VBIAS =
IQ_SW 15 µA
(switching) VOUT = 3.3 V, RFBT = 1 Meg
IPEAK_MIN Minimum inductor peak current VSYNC = 0 V, IOUT = 10 mA 1 A
Operating quiescent current
IBIAS_SW f = 400 kHz, IOUT = 1 A 7 mA
from external VBIAS (switching) SW
DMAX Maximum switch duty cycle While in frequency foldback 97.5%
Dead time between high-side
tDEAD 4 ns
and low-side MOSFETs

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6.9 Typical Characteristics

Unless otherwise specified, VIN = 24 V. Curves represent most likely parametric norm at specified condition.

140 1800
130 1700 VIN = 24 V
1600 VIN = 3.5 V
120 1500 VIN = 60 V
110 1400

Shutdown Current (nA)

1300
100
RDS-ON (m:)

1200
90 1100
80 1000
900
70
800
60 700
50 600
500
40
HS Switch 400
30 LS Switch 300
20 200
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (qC) Temperature (qC) D002
D001

Figure 6-1. High-Side and Low-Side Switch RDS-ON Figure 6-2. Shutdown Quiescent Current
1.008 1.4
Temp = 40qC
1.007 Temp = 25qC
Temp = 125qC 1.2
1.006
Feedback Voltage (V)

Enable Thresholds (V)

1
1.005

1.004 0.8

1.003
0.6
1.002
VEN_VOUT Rising
1.001 0.4 VEN_VOUT Falling
VEN_VCC Rising
VEN_VCC Falling
1
0 6 12 18 24 30 36 42 48 54 60 0.2
Input Voltage (V) -40 -20 0 20 40 60 80 100 120 140
D003 Temperature (qC) D008
Figure 6-3. Feedback Voltage Figure 6-4. Enable Threshold
115

110
PGOOD Threshold (%)

105
OV Tripping
OV Recovery
100
UV Recovery
UV Tripping
95

90

85
-40 -20 0 20 40 60 80 100 120 140
Temperature (qC) D009

Figure 6-5. PGOOD Threshold

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7 Detailed Description
7.1 Overview
The LM76005-Q1 regulator is an easy-to-use synchronous step-down DC-DC converter that operates from 3.5-V
to 60-V supply voltage. The device is capable of delivering up to 5-A DC load current with exceptional efficiency
and thermal performance in a very small solution size.
The LM76005-Q1 employs fixed-frequency peak-current-mode control with configurable discontinuous
conduction mode (DCM) and pulse frequency modulation (PFM) mode at light loads to achieve high efficiency
across the load range. The device can also be configured as forced-PWM (FPWM) operation to keep constant
switching frequency over the load range. The device is internally compensated, which reduces design time and
requires fewer external components. The switching frequency is programmable from 200 kHz to 500 kHz by an
external resistor. The LM76005-Q1 is also capable of synchronization to an external clock operating within the
200-kHz to 500-kHz frequency range. The wide switching frequency range allows the device to meet a wide
range of design requirements. It can be optimized for a very small solution size with higher frequency or for very
high efficiency with lower switching frequency. It has very small minimum HS MOSFET on-time (tON-MIN) and
minimum off-time (tOFF-MIN) to provide wide range of voltage conversion. Automated frequency foldback is
employed under tON-MIN or tOFF-MIN condition to further extend the operation range.
The LM76005-Q1 also features the following:
• A power-good (PGOOD) flag
• Precision enable
• Internal or adjustable soft-start rate
• Start-up with pre-bias voltage
• Output voltage tracking
It provides a flexible and easy-to-use solution for wide range of applications. Protection features include thermal
shutdown, VCC undervoltage lockout, cycle-by-cycle current limiting, and short-circuit hiccup protection.
The family requires very few external components and has a pinout designed for simple, optimum PCB layout for
EMI and thermal performance. The LM76005-Q1 device is available in a 30-pin WQFN lead-less package.
7.2 Functional Block Diagram
EN VCC BIAS

ISSC Internal LDO PVIN

SS Precision VBOOT
BOOT
Enable VCC
SS/TRK HS I Sense
ICMD +
EA + VBOOT
REF ±
RC ± +
UVLO
FB UVLO
FB CC

OV/UV SW
Detector PFM CONTROL LOGIC
Detector
PGood
PGOOD

HICCUP TSD
± +
Slope Comp Detector
Oscillator CLK

AGND ICMD LS I Sense

FPWM

RT SYNC/ PGND
MODE

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7.3 Feature Description

7.3.1 Fixed-Frequency, Peak-Current-Mode Control
The following operation description of the LM76005-Q1 refers to Section 7.2 and to the waveforms in Figure 7-1.
The LM76005-Q1 supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS)
NMOS switches with varying duty cycle (D). During high-side switch on-time, tON, the SW pin voltage VSW
swings up to approximately VIN, and the inductor current, iL, increases with linear slope. The HS switch is turned
off by the control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current
discharges through the LS switch, which forces the VSW to swing below ground by the voltage drop across the
LS switch. The regulator loop adjusts the duty cycle to maintain a constant output voltage. The control parameter
of a buck converter is defined as duty cycle D = tON / TSW. In an ideal buck converter, where losses are ignored,
D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN.
VSW
D = tON/ TSW
VIN
SW Voltage

tON tOFF
t
0
-VD
TSW
iL

ILPK
Inductor Current

IOUT
ûiL

t
0

Figure 7-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode

The LM76005-Q1 synchronous buck converter employs peak current-mode control topology. A voltage-feedback
loop is used to get accurate DC-voltage regulation by adjusting the peak current command based on voltage
offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the
on-time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency in continuous conduction mode (CCM) and
discontinuous conduction mode (DCM). At very light load, the LM76005-Q1 operates in PFM to maintain high
efficiency, and the switching frequency decreases with reduced load current.
7.3.2 Light Load Operation Modes — PFM and FPWM
DCM operation is employed in the LM76005-Q1 when the inductor current valley reaches zero. The LM76005-
Q1 is in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the
LS switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS
FET at zero current, and the conduction loss is lowered by not allowing negative current conduction. Power
conversion efficiency is higher in DCM than CCM under the same conditions.
In DCM, the HS switch on-time reduces with lower load current. When either the minimum HS switch on-time
(tON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency decreases to
maintain regulation. At this point, the LM76005-Q1 operates in PFM. In PFM, switching frequency is decreased
by the control loop when load current reduces to maintain output voltage regulation. Reference the Section 8.2.3
for typical steady state switching behavior in PFM. Switching loss is further reduced in PFM operation due to less
frequent switching actions.
In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The
lower the frequency is in PFM, the more DC offset is needed at VOUT. See Section 6.9 for typical DC offset at
very light load. If the DC offset on VOUT is not acceptable for a given application, TI recommends a static load at

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output to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and RFBB can also serve
as a static load. In conditions with low VIN and high frequency, the LM76005-Q1 may not enter PFM mode if the
output voltage cannot be charged up to provide the trigger to activate the PFM detector. Once the LM76005-Q1
is operating in PFM mode at higher VIN, it remains in PFM operation when VIN is reduced.
Alternatively, the device can run in a forced pulse-width-modulation (FPWM) mode where the switching
frequency does not lower with load, and no offset is added to affect the VOUT accuracy unless the minimum on-
time of the converter is reached.
7.3.3 Adjustable Output Voltage
The voltage regulation loop in the LM76005-Q1 regulates the FB voltage to be the same as the internal
reference voltage. The output voltage of the LM76005-Q1 is set by a resistor divider to program the ratio from
VOUT to VFB. The resistor divider is connected from the output node to ground with the mid-point connecting to
the FB pin.
VOUT

RFBT

FB

RFBB

Figure 7-2. Output Voltage Setting

The voltage reference system produces a precise ±1% voltage reference over temperature. TI recommends
using divider resistors with 1% tolerance or better with temperature coefficient of 100 ppm or lower. Selection of
RFBT equal or lower than 100 kΩ is also recommended. RFBB can be calculated by Equation 1:

VFB
RFBB RFBT
VOUT VFB (1)

Larger RFBT and RFBB values reduce the current that goes through the divider, helping to increase light load
efficiency. However, larger values also make the feedback path more susceptible to noise. If efficiency at very
light load is not critical in a certain application, TI recommends RFBT = 10 kΩ to 100 kΩ. If the resistor divider is
not connected properly, output voltage cannot be regulated because the feedback loop is broken. If the FB pin is
shorted to ground or disconnected, the output voltage is driven close to VIN because the regulator detects very
low voltage on the FB node. The load connected to VOUT can be damaged in this case. It is important to route
the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Section 10.
The minimum output voltage achievable equals VFB, with RFBB open. The maximum VOUT is limited by the
maximum duty cycle at a given frequency:

DMAX = 1 – (tOFF_MIN / TSW) (2)

where
• tOFF_MIN is the minimum off-time of the HS switch
• TSW = 1 / fSW is the switching period
Ideally, without frequency foldback, VOUT_MAX = VIN_MIN × DMAX
Maximum output voltage with frequency foldback can be estimated using Equation 3:

tON _ MAX
VOUT _ MAX VIN_MIN u IOUT u RDS _ ON _ HS DCR
tON _ MAX tOFF _ MIN (3)

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7.3.4 Enable (EN Pin) and UVLO

System UVLO by EN and VCC_UVLO voltage on the EN pin (VEN) controls the ON/OFF functionality of the
LM76005-Q1. Applying a voltage less than 0.3 V to the EN input shuts down the operation of the LM76005-Q1.
In shutdown mode, the quiescent current drops to typically 1.2 µA at VIN = 24 V.
The internal LDO output voltage VCC is turned on when VEN is higher than 1.2 V. The LM76005-Q1 switching
action and output regulation are enabled when VEN is greater than 1.204 V (typical). The LM76005-Q1 supplies
regulated output voltage when enabled and output current up to 5 A. The EN pin is an input and cannot be open
circuit or floating. The simplest way to enable the operation of the LM76005-Q1 is to connect the EN pin to PVIN
pins directly. This allows self-start-up of the LM76005-Q1 when VIN is within the operation range.
Many applications can benefit from the employment of an enable divider RENT and RENB (see Figure 7-3) to
establish a precision system UVLO level for the stage. System UVLO can be used for supplies operating from
utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply
protection, such as a battery. An external logic signal can also be used to drive EN input for system sequencing
and protection.

VIN
RENT
ENABLE
RENB

Figure 7-3. VIN UVLO

With a selected RENT, the RENB can be calculated by:

VEN _ VOUT _ H u RENT

RENB
VIN _ ON _ H VEN_VOUT_H (4)

where
• VIN_ON_H is the desired supply voltage threshold to turn on this device
• VEN_VOUT_H can be taken from device data sheet
Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add
more quiescent current loss. However, large divider values make the node more sensitive to noise. RENT in the
hundreds of kΩ range is a good starting point.
7.3.5 Internal LDO, VCC UVLO, and Bias Input
The LM76005-Q1 has an internal LDO generating VCC voltage for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 3.29 V. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as close as
possible to the pin and properly grounded. Do not load or short the VCC pin to ground during operation. Shorting
the VCC pin to ground during operation can damage the device.
A UVLO prevents the LM76005-Q1 from operating until the VCC voltage exceeds VCC_UVLO. The VCC_UVLO
threshold is 3.14 V and has approximately 565 mV of hysteresis, so the device operates until VCC drops below
2.575 V (typical). Hysteresis prevents the device from turning off during power up if VIN droops due to input
current demands.
The LDO can generate VCC from two inputs: the supply voltage VIN and the BIAS input. The LDO power loss is
calculated by ILDO × (VINLDO – VOUTLDO). The higher the difference between the input and output voltages of the
LDO, the more losses occur to supply the same LDO output current. The BIAS input is designed to reduce the
difference of the input and output voltages of the LDO to improve efficiency, especially at light load. TI
recommends tying the BIAS pin to VOUT when the output voltage is equal to or greater than 3.3 V and less than
18 V. Tie the BIAS pin to ground for applications less than 3.3 V or greater than 18 V. BIAS can also tie to
external voltage source if available to improve efficiency. When used, TI recommends a 1-µF to 10-µF high-

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quality ceramic capacitor be used to bypass the BIAS pin to ground. If there is high-frequency noise or voltage
spikes present on VOUT (during transient events or fault conditions), TI recommends connecting a resistor (1 to
10 Ω) between VOUT and BIAS.
The VCC voltage is typically 3.29 V. When the LM76005-Q1 is operating in PFM mode with frequency foldback,
VCC voltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve efficiency at very
light loads.
7.3.6 Soft Start and Voltage Tracking (SS/TRK)
The LM76005-Q1 has a flexible and easy-to-use start-up rate control pin: SS/TRK. The soft-start feature
prevents inrush current from impacting the LM76005-Q1 and its supply when power is first applied. Soft start is
achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up. The
simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM76005-Q1 employs the
internal soft-start control ramp and starts up to the regulated output voltage in 6.3 ms typically. In applications
with a large amount of output capacitors, higher VOUT, or other special requirements, the soft-start time can be
extended by connecting an external capacitor, CSS, from SS/TRK pin to AGND. Extended soft-start time further
reduces the supply current required to charge up output capacitors and supply any output loading. An internal
current source (ISSC = 2.2 μA) charges CSS and generates a ramp from 0 V to VFB to control the ramp-up rate of
the output voltage. For a desired soft-start time tSS, the capacitance for CSS can be found by Equation 5:

CSS = ISSC × tSS (5)

where
• CSS = soft-start capacitor value (µF)
• ISSC = soft-start charging current (µA)
• tSS = desired soft-start time (s)
The soft-start capacitor CSS is discharged by an internal FET when VOUT is shut down by hiccup protection or
ENABLE = logic low. When a large CSS is applied, and EN is toggled low only for a short period of time, CSS may
not be fully discharged. The next soft-start ramp follows internal soft-start ramp before reaching the leftover
voltage on CSS and then follows the ramp programmed by CSS. If this is not acceptable for a certain application,
an R-C low-pass filter can be added to EN to slow down the shutting down of VCC, allowing more time to
discharge CSS.
The LM76005-Q1 is capable of start-up into pre-biased output conditions. When the inductor current reaches
zero, the LS switch is turned off to avoid negative current conduction. This operation mode is also called diode
emulation mode. It is built-in by the DCM operation in light loads. With a pre-biased output voltage, the
LM76005-Q1 waits until the soft-start ramp allows regulation above the pre-biased voltage and then follows the
soft-start ramp to the regulation level. When an external voltage ramp is applied to the SS/TRK pin, the
LM76005-Q1 FB voltage follows the ramp if the ramp magnitude is lower than the internal soft-start ramp. A
resistor divider pair can be used on the external control ramp to the SS/TRK pin to program the tracking rate of
the output voltage. The final voltage detected by the SS/TRK pin must not fall below 1.2 V to avoid abnormal
operation.
VOUT tracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltage
ramp. VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin.
Figure 7-4 shows resistive divider connection if external ramp tracking is desired.
EXT RAMP
RTRT
SS/TRK
RTRB

Figure 7-4. Soft-Start Tracking External Ramp

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Figure 7-5 shows the case when VOUT ramps more slowly than the internal ramp, while Figure 7-6 shows when
VOUT ramps faster than the internal ramp. Faster start-up time can result in inductor current tripping current
protection during start-up. Use with special care.
Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

VOUT

Figure 7-5. Tracking with Longer Start-up Time than the Internal Ramp
Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

VOUT

Figure 7-6. Tracking with Shorter Start-up Time than the Internal Ramp

The LM76005-Q1 is capable of start-up into pre-biased output conditions. During start-up, the device sets the
minimum inductor current to zero to avoid discharging a pre-biased load.
7.3.7 Adjustable Switching Frequency (RT) and Frequency Synchronization
The switching frequency of the LM76005-Q1 can be programmed by the impedance RT from the RT pin to
ground. The frequency is inversely proportional to the RT resistance. The RT pin can be left floating, and the
LM76005-Q1 operates at 400-kHz default switching frequency. The RT pin is not designed to be shorted to
ground.
For an desired frequency, RT can be found by:

38400
RT (k:) =
Frequency(kHz) 14.33 (6)
Table 7-1. Switching Frequency vs RT
SWITCHING FREQUENCY (kHz) RT RESISTANCE (kΩ)
200 206.82
300 134.42
400 99.57
500 79.07

The LM76005-Q1 switching action can also be synchronized to an external clock from 200 kHz to 500 kHz. TI
recommends connecting an external clock to the SYNC pin with an appropriate termination resistor. Ground the
SYNC pin if not used.

SYNC
EXT CLOCK
RTERM

Figure 7-7. Frequency Synchronization

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The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V,
duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the
external clock fails at logic high or low, the LM76005-Q1 switches at the frequency programmed by the RT
resistor after a time-out period. TI recommends connecting a resistor RT to the RT pin so that the internal
oscillator frequency is the same as the target clock frequency when the LM76005-Q1 is synchronized to an
external clock. This allows the regulator to continue operating at approximately the same switching frequency if
the external clock fails.
The choice of switching frequency is usually a compromise between conversion efficiency and the size of the
circuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switch
transition losses, and so forth) and usually results in higher overall efficiency. However, higher switching
frequency allows use of smaller LC output filters and hence a more compact design. Lower inductance also
helps transient response (higher large signal slew rate of inductor current), and reduces the DCR loss. The
optimal switching frequency is usually a trade-off in a given application and thus needs to be determined on a
case-by-case basis. It is related to the following:
• Input voltage
• Output voltage
• Most frequent load current level or levels
• External component choices
• Circuit size requirement
The choice of switching frequency can also be limited if an operating condition triggers tON-MIN or tOFF-MIN.
7.3.8 Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout Conditions
Minimum on-time, tON-MIN, is the smallest duration of time that the HS switch can be on. tON-MIN is typically 65 ns
in the LM76005-Q1. Minimum off-time, tOFF-MIN, is the smallest duration that the HS switch can be off. tOFF-MIN is
typically 95 ns in the LM76005-Q1. In CCM operation, tON-MIN and tOFF-MIN limits the voltage conversion range
given a selected switching frequency. The minimum duty cycle allowed is:

DMIN = tON-MIN × fSW (7)

And the maximum duty cycle allowed is:

DMAX = 1 – tOFF-MIN × fSW (8)

Given fixed tON-MIN and tOFF-MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle. In the LM76005-Q1, frequency foldback scheme is employed to extend the maximum duty cycle when
tOFF-MIN is reached. The switching frequency decreases once longer duty cycle is needed under low VIN
conditions. Such a wide range of frequency foldback allows the LM76005-Q1 output voltage to stay in regulation
with a much lower supply voltage VIN. This leads to a lower effective dropout voltage.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size, and efficiency. The maximum operational supply voltage can be found by:

VIN_MAX = VOUT / (fSW × tON-MIN) (9)

At lower supply voltage, the switching frequency decreases once tOFF-MIN is tripped. The minimum VIN without
frequency foldback can be approximated by:

VIN_MIN = VOUT / (fSW × tOFF-MIN) (10)

Considering power losses in the system with heavy load operation, VIN-MIN is higher than the result calculated in
Equation 10. With frequency foldback, VIN-MIN is lowered by decreased fSW. When the device is operating in auto
mode at voltages near maximum rated input voltage and light load conditions, an increased output voltage ripple
during load transient can be observed. For this reason, TI recommends that the device operating point be
calculated with sufficient operational margin so that minimum on-time condition is not triggered.

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7.3.9 Bootstrap Voltage and VBOOT UVLO (BOOT Pin)

The driver of the power switch (HS switch) requires bias higher than VIN when the HS switch is ON. The
capacitor connected between CBOOT and SW works as a charge pump to boost voltage on the BOOT pin to (VSW
+ VCC). The boot diode is integrated on the LM76005-Q1 die to minimize physical size. TI recommends a 0.47-
µF, 6.3-V or higher capacitor for CBOOT. The VBOOT_UVLO threshold is typically 2.2 V. If the CBOOT capacitor is not
charged above this voltage with respect to SW, the device initiates a charging sequence using the low-side FET.
7.3.10 Power Good and Overvoltage Protection (PGOOD)
The LM76005-Q1 has a built-in power-good flag shown on the PGOOD pin to indicate whether the output
voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails.
The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any
voltage below 12 V). The pin can sink 5 mA of current and maintain its specified logic low level. A typical range
of pullup resistor value is 10 kΩ to 100 kΩ. When the FB voltage is outside the power-good band, +10% above
and –10% below the internal reference VREF typically, the PGOOD switch is turned on, and the PGOOD pin
voltage is pulled to ground. When the FB is 2.5% (typical) closer to FB than the PGOOD threshold, the PGOOD
switch is turned off, and the pin is pulled up to the voltage connected to the pullup resistor. Both rising and falling
edges of the power-good flag have a built-in 140-µs (typical) deglitch delay. To pull up the PGOOD pin to a
voltage higher than 15 V, a resistor divider can be used to divide the voltage down.
VPU

RPGT

PGOOD

RPGB

Figure 7-8. PGOOD Resistor Divider

For given pullup voltage, VPU, the desired voltage on PGOOD pin, VPG, and RPGT chosen, use Equation 11 to
calculate RPGB:

VPG
RPGB = RPGT
VPU VPG (11)

7.3.11 Overcurrent and Short-Circuit Protection

The LM76005-Q1 is protected from overcurrent conditions by cycle-by-cycle current limiting on both peak and
valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent overheating.
High-side MOSFET overcurrent protection is implemented by the nature of the peak current-mode control. The
HS switch current is sensed when the HS is turned on after a blanking time. The HS switch current is compared
to either the minimum of a fixed current set point (IHS_Limit) or the output of the voltage regulation loop minus
slope compensation every switching cycle.
When the LS switch is turned on, the current going through it is also sensed and monitored. Before turning off
the LS switch at the end of every clock cycle, the LS current is compared to the LS current limit. If the LS current
limit is exceeded, the LS MOSFET stays on, and the HS switch is not turned on. The LS switch is kept ON so
that inductor current keeps ramping down, until the inductor current ramps below ILS_LIMIT. The LS switch is
turned off once the LS current falls below the limit, and the HS switch is turned on again after a dead time.
If the current of the LS switch is higher than the LS current limit for 128 consecutive cycles, and the feedback
voltage falls 60% below regulation, hiccup current-protection mode is activated. In hiccup mode, the regulator is
shut down and kept off for 46 ms typically before the LM76005-Q1 tries to start again. If overcurrent or a short-
circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup mode reduces power
dissipation under severe overcurrent conditions, and prevents overheating and potential damage to the device.
Under non-severe overcurrent conditions when the feedback voltage has not fallen 60% below regulation, the

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LM76005-Q1 reduces the switching frequency and keeps the inductor current valley clamped at the LS current
limit level. This operation mode allows slight overcurrent operation during load transients without tripping hiccup.
If tracking was used for initial sequencing, the device attempts to restart using the internal soft-start circuit until
the tracking voltage is reached.
7.3.12 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction
temperature exceeds 150°C (typical). After thermal shutdown occurs, hysteresis prevents the device from
switching until the junction temperature drops to approximately 135°C. When the junction temperature falls
below 135°C, the LM76005-Q1 attempts to soft start.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical on/off control for the LM76005-Q1. When the EN pin voltage is below 0.3 V
(typical), both the regulator and the internal LDO have no output voltages, and the device is in shutdown mode.
In shutdown mode the quiescent current drops to typically 1.2 µA. The LM76005-Q1 also employs UVLO
protection. If VCC voltage is below the UVLO level, the output of the regulator is turned off.
7.4.2 Standby Mode
The internal LDO has a lower EN threshold than the regulator. When the EN pin voltage is above 1.2 V
(maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the VCC
voltage at 3.29 V typically. The precision enable circuitry is ON once VCC is above the UVLO. The internal
MOSFETs remain in tri-state unless the voltage on EN pin goes above the precision enable threshold. The
LM76005-Q1 also employs UVLO protection. If VCC voltage is below the UVLO level, the output of the regulator
is turned off.
7.4.3 Active Mode
The LM76005-Q1 is in active mode when the EN pin and UVLO high threshold levels are satisfied. The simplest
way to enable the operation of the LM76005-Q1 is to connect the EN pin to VIN, which allows self start-up of the
LM76005-Q1 when the input voltage is in the operation range: 3.5 V to 60 V. See Section 7.3.4 for details on
setting these operating levels.
In active mode, depending on the load current, the LM76005-Q1 will be in one of five sub modes:
1. CCM with fixed switching frequency with load between half of IMINPK to full load
2. DCM when the load current is lower than half of the inductor current ripple
3. Light load mode where the device uses pulse frequency modulation (PFM) and lowers the switching
frequency at load under half of IPEAK_MIN to improve efficiency
4. Foldback mode when switching frequency is reduced to maintain output regulation with supply voltages that
cause the minimum tON or tOFF to be exceeded
5. Forced-pulse-width modulation (FPWM) is similar to CCM with fixed switching frequency, but extends the
fixed frequency range of operation from full to no load.
7.4.4 CCM Mode
CCM operation is employed in the LM76005-Q1 when the load current is higher than ½ of the peak-to-peak
inductor current. If the load current is decreased, the device enters DCM mode. In CCM operation, the frequency
of operation is constant and fixed unless the minimum tON or tOFF are exceeded which causes the part to enter
foldback mode (refer to Section 7.3.5 for details). In these cases, PWM is still maintained, but the frequency of
operation is folded back (reduced) to maintain proper regulation.
7.4.5 DCM Mode
DCM operation is employed in the LM76005-Q1 when the load current is lower than ½ of the peak-to-peak
inductor current. In DCM operation (also known as diode emulation mode), the LS FET is turned off when the
inductor current drops below 0 A to keep operation as efficient as possible by reducing switching losses and
preventing negative current conduction. In PWM operation, the frequency of operation is constant and fixed

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unless the load current is reduced below IPEAK_MIN, which causes the part to enter light load mode, or if the
minimum tON or tOFF are exceeded, which cause the device to enter foldback mode.
7.4.6 Light Load Mode
At light output current loads, PFM is activated for the highest efficiency possible. When the inductor current does
not reach IPEAK_MIN during a switching cycle, the on-time is increased, and the switching frequency reduces as
needed to maintain proper regulation. The on-time has a maximum value of 8 µs to avoid large output voltage
ripple in dropout conditions. Efficiency is greatly improved by reducing switching and gate-drive losses. During
light-load mode of operation, the LM76005-Q1 operates with a minimum quiescent current of 10 to 15 µA
(typical).
7.4.7 Foldback Mode
Foldback protection modes are entered when the duty cycle exceeds the minimum on- and off-times of the
device. At very high duty cycles, where the minimum off-time is not satisfied, the frequency folds back to allow
more time for the peak current command to be reached. The maximum on-time is 8 µs, which limits the
maximum duty cycle in dropout to 98%. At very low duty cycles when the minimum on-time is reached, the
device maintains regulation by dropping the frequency to allow more time for the inductor current to discharge
the output capacitor. Foldback mode is exited once the minimum on-time and off-times are satisfied.
7.4.8 Forced Pulse-Width-Modulation Mode
FPWM is employed when the FPWM pin is pulled high, or the device is synchronized to an external clock. In this
mode, diode emulation is turned off, and the device remains in CCM over the full load range. In FPWM
operation, the frequency of operation is constant and fixed unless the minimum tON or tOFF are exceeded, which
cause the device to enter foldback mode. In these cases, PWM operation is still maintained, but the frequency of
operation is folded back (reduced) to maintain proper regulation. DC accuracy is highest in FPWM mode.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information

The LM76005-Q1 is a step-down DC-DC converter. It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 5 A. The following design procedure can be used to select
component values for the LM76005-Q1. Alternately, the WEBENCH® software may be used to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design.
8.2 Typical Applications
The LM76005-Q1 only requires a few external components to convert from a wide range of supply voltages to
output voltage, as shown in Figure 8-1 :
L
VIN PVIN SW VOUT
CIN CBOOT COUT
PGND RFBT CFF
BOOT
FB
EN VCC RFBB
CVCC
SS/TRK

BIAS
RT
LM76005-Q1 CBIAS

SYNC PGOOD

Tie BIAS to PGND

AGND
when VOUT < 3.3 V

Figure 8-1. LM76005-Q1 Basic Schematic

The LM76005-Q1 also integrates a full list of features to aid system design requirements, such as the following:
• VCC UVLO
• Programmable soft start
• Start-up tracking
• Programmable switching frequency
• Clock synchronization
• Power-good indication
Each system can select the features needed in a specific application. A comprehensive schematic with all
features utilized is shown in Figure 8-2 :

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VIN L VOUT
PVIN SW
RENT CIN COUT
PGND CBOOT RFBT CFF
BOOT
RENB EN
FB
VCC RFBB
CVCC
SS/TRK
CSS
RT BIAS
RT LM76005-Q1 CBIAS

SYNC PGOOD
RPG
RSYNC
Tie BIAS to PGND when
AGND PGND VOUT < 3.3 V

Figure 8-2. LM76005-Q1 Comprehensive Schematic

The external components must fulfill the requirements of the application, but also the stability criteria of the
device control loop. The LM76005-Q1 is optimized to work within a range of external components. Inductance
and capacitance of the LC output filter each create poles that have to be considered in the control of the
converter. For VOUT = 1 V, 3.3 V, 5V, the recommended output capacitors have been generated assuming typical
derating for 16-V, X7R, automotive grade capacitors. For VOUT = 12 V, the recommended output capacitors have
been generated assuming typical derating for 25-V, X7R, automotive grade capacitors, and for VOUT = 24 V, the
recommended output capacitors have been generated assuming typical derating for 50-V, X7R, automotive
grade capacitors. If lower voltage, nonautomotive grade, or lower temperature rated capacitors are used, more
capacitors than listed are likely to be needed. Table 8-1 can be used to simplify the output filter component
selection.
Table 8-1. Typical Component Selection
fSW (kHz) VOUT (V) L (µH) COUT (µF) RFBT (kΩ) RFBB (kΩ)
200 1 2.5 720 100 OPEN
400 1 1.2 600 100 OPEN
500 1 1 470 100 OPEN
200 3.3 10 300 100 43.5
400 3.3 4.7 220 100 43.5
500 3.3 4.7 200 100 43.5
200 5 15 250 100 25
400 5 6.8 180 100 25
500 5 5.2 150 100 25
200 12 22 200 100 9.09
400 12 10 150 100 9.09
500 12 7.2 120 100 9.09
200 24 44 150 100 4.37
400 24 22 100 100 4.37
500 24 15 88 100 4.37

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8.2.1 Design Requirements

Section 8.2.2 is based on a design example. For this design example, use the parameters listed in Table 8-2 as
the input parameters.
Table 8-2. Design Example Parameters
DESIGN PARAMETER VALUE
Input voltage range 3.5 V to 60 V
Output voltage 5V
Input ripple voltage 400 mV
Output ripple voltage 30 mV
Output current rating 5A
Operating frequency 400 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM76005-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the LM76005-Q1 device is externally adjustable using a resistor divider network. In the
application circuit of Figure 8-2 , this divider network is comprised of top feedback resistor, RFBT, and bottom
feedback resistor, RFBB. Equation 12 is used to determine the output voltage of the converter:

VFB
RFBB RFBT
VOUT VFB (12)

Choose the value of the RFBT to be around 1 MΩ to minimize quiescent current during light load operation or 100
kΩ to improve noise immunity. With the desired output voltage set to be 5 V and with a VFB = 1 V, the RFBB value
can then be calculated using Equation 12. The formula yields a value of 24.9 kΩ when RFBT = 100 kΩ.
8.2.2.3 Switching Frequency
The default switching frequency of the LM76005-Q1 device is set at 400 kHz. If the RT is left open, the
LM76005-Q1 switches at 400 kHz in CCM mode. Use Equation 13 to calculate the required value for RT to
operate the LM76005-Q1 at different frequencies.

38400
RT (k:) =
Frequency(kHz) 14.33 (13)

The result for 400 kHz is 99.57 kΩ.

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The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows for the use of smaller inductors and output capacitors, hence, a
more compact design. When choosing operating frequency, the most important consideration is thermal
limitations. This constraint typically dominates frequency selection. For the LM76005, the safe operating area is
controlled by the thermal performance (RθJA=18.8 °C/W); see Figure 8-3.
6

Output Current (A) 4

0
25 50 75 100 125 150
Ambient Temperature (°C) lm76

Figure 8-3. LM76005-Q1 Safe Operating Area (5 VOUT, 400 kHz, RθJA=18.8 °C/W)

8.2.2.4 Input Capacitors

The LM76005-Q1 device requires an input decoupling and, depending on the application, a bulk input capacitor.
The typical recommended value for the high frequency decoupling capacitor is 10 μF to 22 μF. TI recommends a
high-quality ceramic type X5R or X7R with sufficiency voltage rating. The voltage rating must be greater than the
maximum input voltage. To compensate the derating of ceramic capacitors, a voltage rating of twice the
maximum input voltage is recommended.
Many times, it is desirable and necessary to use an electrolytic capacitor on the input in parallel with the
ceramics. This is especially true if the LM76005-Q1 circuit is not located within approximately 5 cm from the
input voltage source. This capacitor can help damp any ringing on the input supply caused by the long power
leads and the associated inductance. The use of this additional capacitor also helps with momentary voltage
dips caused by input supplies with unusually high impedance. The optimum value for this capacitor is four times
the ceramic input capacitance with ESR close to the characteristic impedance of the LC filter formed by the
application input inductance and ceramic input capacitors.
For this design, two 4.7-μF, X7R dielectric capacitors rated for 100 V are used for the input decoupling
capacitance. A single capacitor can aslo be used that has an equivalent series resistance (ESR) of
approximately 3 mΩ, and an RMS current rating of 5 A. Include a capacitor with a value of 47 nF for high-
frequency filtering and place it as close as possible to the device pins.

Note
DC-Bias Effect: High capacitance ceramic capacitors have a DC-bias derating effect, which has a
strong influence on the final effective capacitance. Therefore, choose the right capacitor value
carefully. Package size and voltage rating in combination with dielectric material are responsible for
differences between the rated capacitor value and the effective capacitance.

8.2.2.5 Inductor Selection

The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is
based on the desired peak-to-peak ripple current, ΔiL that flows in the inductor along with the load current. As
with switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductance
means lower ripple current and hence lower output voltage ripple. Lower inductance results in smaller, less
expensive devices. An inductance that gives a ripple current of 20% to 40% of the maximum output current is a

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good starting point. (ΔiL = (1/5 to 2/5) × IOUT). The peak-to-peak inductor current ripple can be found by Equation
15 and the range of inductance can be found by Equation 14 with the typical input voltage used as VIN.

(VIN VOUT ) u D
'iL
L u fSW (14)

(VIN (VVINOUTV)OUT
u D) u D (VIN (VV V) u D) u D
d L dd L d INOUT OUT
0.4 u0.4
fSWu ufSW
IL-MAX
u I
LOAD-MAX
L-MAX 0.2 u0.2
f u f
u
SW SW I u IL-MAX
L-MAX LOAD-MAX (15)

D is the duty cycle of the converter which in a buck converter it can be approximated as D = VOUT / VIN,
assuming no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductance
value comes out in micro henries. The inductor ripple current ratio is defined by:

'iL
r
IOUT (16)

The second criterion is the inductor saturation-current rating. The inductor must be rated to handle the maximum
load current plus the ripple current:

IL-PEAK = ILOAD-MAX + Δ iL / 2 (17)

The LM76005-Q1 has both valley current limit and peak current limit. During an instantaneous short, the peak
inductor current can be high due to a momentary increase in duty cycle. The inductor current rating must be
higher than the HS current limit. TI recommends selection of an inductor with a larger core saturation margin and
preferably a softer roll off of the inductance value over load current.
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. However,
too low of an inductance can generate too large of an inductor current ripple such that overcurrent protection at
the full load can be falsely triggered. It also generates more conduction loss because the RMS current is slightly
higher relative that with lower current ripple at the same DC current. Larger inductor current ripple also implies
larger output voltage ripple with the same output capacitors. With peak-current-mode control, it is not
recommended to have an inductor current ripple that is too small. Enough inductor current ripple improves
signal-to-noise ratio on the current comparator and makes the control loop more immune to noise.
Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low core
losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and
preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly
when the peak design current is exceeded. The hard saturation results in an abrupt increase in inductor ripple
current and consequent output voltage ripple. Do not allow the core to saturate.
For the design example, a standard 6.8-μH inductor from Wurth, Coiltronics, or Vishay can be used for the 5-V.
8.2.2.6 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. TI generally recommends using as little
output capacitance as possible to keep cost and size down. Choose the output capacitor or capacitors, COUT,
with care as it directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/
undershoot during load current transients.
The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple
going through the equivalent series resistance (ESR) of the output capacitors:

ΔVOUT-ESR = ΔiL × ESR (18)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

ΔVOUT-C = ΔiL / (8 × fSW × COUT) (19)

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The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,
output capacitors provide the required charge before the inductor current can slew to the appropriate level. The
initial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop until
the control loop response increases or decreases the inductor current to supply the load. To maintain a small
overshoot or undershoot during a transient, small ESR, and large capacitance are desired. But these also come
with higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the output
voltage deviation.
For a given input and output requirement, Equation 20 gives an approximation for an absolute minimum output
cap required:

1 ª§ r 2 · º
COUT ! u «¨ u (1 Dc) ¸ Dc u (1 r) »
(fSW ¨
u r u 'VOUT / IOUT ) ¬«© 12 ¸
¹ ¼» (20)

Along with this for the same requirement, calculate the maximum ESR as per Equation 21:

D' §1 ·
ESR < u ¨ + 0.5 ¸
fSW u COUT ©r ¹ (21)

where
• r = ripple ratio of the inductor ripple current (ΔiL / IOUT)
• ΔVO = target output voltage undershoot
• D’ = 1 – duty cycle
• fSW = switching frequency
• IOUT = load current
A general guideline for COUT range is that COUT must be larger than the minimum required output capacitance
calculated by Equation 20. Limit the maximum value of total output capacitance to between 800 μF and 1200 μF.
Large values of output capacitance can prevent the regulator from starting up correctly and adversely effect the
loop stability. If values greater than the given range are to be used, then a careful study of start-up at full load
and loop stability must be performed.
In applications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This limits
potential output voltage overshoots as the input voltage falls below the device normal operating range. To
optimize the transient behavior a feedforward capacitor can be added in parallel with the upper feedback
resistor. For this design example, three 47-µF, 10-V, X7R ceramic capacitors are used in parallel.
8.2.2.7 Feedforward Capacitor
The LM76005-Q1 is internally compensated. Depending on the VOUT and frequency FS, if the output capacitor
COUT is dominated by low ESR (ceramic types) capacitors, it can result in low phase margin. To improve the
phase boost an external feedforward capacitor, CFF can be added in parallel with RFBT. CFF is chosen such that
phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover
frequency without CFF (fx) is shown in Equation 22, assuming COUT has very small ESR.

15.46
fX
VOUT u COUT (22)

Equation 23 for CFF was tested:

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1 1
CFF u
2Sfx RFBT u (RFBT / /RFBB )
(23)

If capacitors with high ESR are used, CFF is not required. The CFF capacitor creates a time constant with RFBT
that couples the attenuated output voltage ripple to the FB node. Using a value that is too large for CFF can
couple too much ripple to FB node and affect output voltage regulation. For capacitors with medium ESR (20 –
200 mΩ), Equation 1 can be used as a quick starting point. For the application in this design example, a 47-pF
C0G capacitor is used.
8.2.2.8 Bootstrap Capacitors
Every LM76005-Q1 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.47
μF and rated at 6.3 V or greater. The bootstrap capacitor is located between the SW pin and the BOOT pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
For improved EMI performance, a boot resistor can be added in series with the bootstrap capacitor. The boot
resistor will slow down the rising edge of the switch node.
8.2.2.9 VCC Capacitors
The VCC pin is the output of an internal LDO for LM76005-Q1. The input for this LDO comes from either VIN or
BIAS (please refer to functional block diagram for LM76005-Q1). To ensure stability of the part, place a 1-µF to
2.2-µF, 10-V capacitor for this pin. Never short VCC pin to ground during operation.
8.2.2.10 BIAS Capacitors
For an output voltage of 3.3 V and greater, connect the BIAS pin to the output to increase light load efficiency.
The BIAS pin is one of the two inputs for the VCC LDO. When BIAS voltage is below VBIAS-ON threshold, the
input for the VCC LDO is internally connected to VIN. Because this is an LDO, the voltage differences between
the input and output affects the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be
added close to the BIAS pin as an input capacitor for the LDO.
8.2.2.11 Soft-Start Capacitors
The SS pin can be left floating, and the LM76005-Q1 implements a soft-start time of 6.3 ms. To use an external
soft-start capacitor, the capacitor must be sized so that the soft-start time is greater than 6.3 ms. Use Equation
24 to calculate the soft-start capacitor value:

CSS = ISSC × tSS (24)

With a desired soft-start time of 11 ms, a soft-start charging current of 2 µA, and an internal VREF of 1 V,
Equation 24 yields a soft-start capacitor value of 22 nF.
8.2.2.12 Undervoltage Lockout Setpoint
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. RENT
is connected between the PVIN pin and the EN pin of the LM76005-Q1. RENB is connected between the EN pin
and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brownouts when the input voltage is falling. Equation 25 can be used to determine the VIN UVLO
level.

VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB (25)

The EN rising threshold (VENH) for LM76005-Q1 is set to be 1.204 V (typical). Choose the value of RENB to be
100 kΩ to minimize input current from the supply. If the desired VIN UVLO level is at 5 V, then the value of RENT
can be calculated using Equation 26:

RENT = (VIN-UVLO-RISING / VENH – 1) × RENB (26)

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Equation 26 yields a value of 315 kΩ. The resulting falling UVLO threshold, can be calculated by Equation 27,
where EN falling threshold (VENL) is 1.05 V (typical).

VIN-UVLO-FALLING = VENL × (RENB + RENT) / RENB (27)

8.2.2.13 PGOOD
A typical pullup resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 18 V. If it is
desired to pull up the PGOOD pin to a voltage higher than 18 V, a resistor can be added from the PGOOD pin to
ground to divide the voltage detected by the PGOOD pin to a value no higher than 18 V.
8.2.2.14 Synchronization
The LM76005-Q1 switching action can synchronize to an external clock from 200 kHz to 500 kHz. TI
recommends connecting an external clock to the SYNC pin with a 50-Ω to 100-Ω termination resistor. Ground
the SYNC pin if not used.

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8.2.3 Application Curves

Unless otherwise specified the following conditions apply:

100 5.2

95 5.16
5.12
90
5.08

Output Voltage (V)

Efficiency (%)

85 5.04
80 5

75 4.96
4.92
70
4.88
65 VIN = 12 V 4.84 VIN = 12 V
VIN = 24 V VIN = 24 V
60 4.8
0.001 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 45 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Load Current (A) Quik
Load Current (A) Quik

VOUT = 5 V fSW = 400 kHz Auto Mode VOUT = 5 V fSW = 400 kHz Auto Mode

Figure 8-4. LM76005-Q1 Efficiency Figure 8-5. LM76005-Q1 Load and Line Regulation
5.6 5E+5

5.4 4.5E+5

5.2 4E+5
Switching Frequency (Hz)

3.5E+5
Output Voltage (V)

5
3E+5
4.8
2.5E+5
4.6
2E+5
4.4
1.5E+5
4.2 1E+5
4 ILOAD = 2.5 A 5E+4 ILOAD = 2.5 A
ILOAD = 5 A ILOAD = 5 A
3.8 0
4.5 5 5.5 6 6.5 5 5.5 6 6.5 7
Input Voltage (V) drop
Input Voltage (V) drop

VOUT = 5 V fSW = 400 kHz FPWM Mode VOUT = 5 V fSW = 400 kHz FPWM Mode

Figure 8-6. LM76005-Q1 Voltage Dropout Figure 8-7. LM76005-Q1 Frequency Dropout

VSW VSW
(5 V/DIV) (10 V/DIV)

IINDUCTOR IINDUCTOR
(500 mA/ (500 mA/
DIV) DIV)

VOUT VOUT
(20 mV/DIV) (20 mV/DIV)

Time (4 ms/DIV) Time (4 ms/DIV)

VIN = 12 V VOUT = 5 V fSW = 400 kHz VIN = 24 V VOUT = 5 V fSW = 400 kHz
No Load Auto Mode No Load Auto Mode

Figure 8-8. LM76005-Q1 Switching Waveform and Figure 8-9. LM76005-Q1 Switching Waveform and
Output Ripple Output Ripple

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VSW VSW
(5 V/DIV) (10 V/DIV)

IINDUCTOR IINDUCTOR
(500 mA/ (500 mA/
DIV) DIV)

VOUT VOUT
(20 mV/DIV) (20 mV/DIV)

Time (2 µs/DIV) Time (2 µs/DIV)

VIN = 12 V VOUT = 5 V fSW = 400 kHz VIN = 24 V VOUT = 5 V fSW = 400 kHz
No Load FPWM Mode No Load FPWM Mode

Figure 8-10. LM76005-Q1 Switching Waveform and Figure 8-11. LM76005-Q1 Switching Waveform and
Output Ripple Output Ripple

VSW VSW
(5 V/DIV) (10 V/DIV)

IINDUCTOR IINDUCTOR
(500 mA/ (500 mA/
DIV) DIV)

VOUT VOUT
(20 mV/DIV) (20 mV/DIV)

Time (4 µs/DIV) Time (4 µs/DIV)

VIN = 12 V VOUT = 5 V fSW = 400 kHz VIN = 24 V VOUT = 5 V fSW = 400 kHz
100-mA Load Auto Mode 100-mA Load Auto Mode

Figure 8-12. LM76005-Q1 Switching Waveform and Figure 8-13. LM76005-Q1 Switching Waveform and
Output Ripple Output Ripple

VSW VSW
(5 V/DIV) (10 V/DIV)

IINDUCTOR IINDUCTOR
(500 mA/ (500 mA/
DIV) DIV)

VOUT VOUT
(20 mV/DIV) (20 mV/DIV)

Time (2 µs/DIV) Time (2 µs/DIV)

VIN = 12 V VOUT = 5 V fSW = 400 kHz VIN = 24 V VOUT = 5 V fSW = 400 kHz
100-mA Load FPWM Mode 100-mA Load FPWM Mode

Figure 8-14. LM76005-Q1 Switching Waveform and Figure 8-15. LM76005-Q1 Switching Waveform and
Output Ripple Output Ripple

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Enable Enable
(2 V/DIV) (2 V/DIV)

VOUT VOUT
(2 V/DIV) (2 V/DIV)

PGOOD PGOOD
(2 V/DIV) (2 V/DIV)

IINDUCTOR IINDUCTOR
(2 A/DIV) (2 A/DIV)
Time (4 ms/DIV) Time (4 ms/DIV)

VIN = 12 V VOUT = 5 V fSW = 400 kHz VIN = 24 V VOUT = 5 V fSW = 400 kHz
No Load Auto Mode No Load Auto Mode

Figure 8-16. LM76005-Q1 Start-up Waveform Figure 8-17. LM76005-Q1 Start-up Waveform

Enable Enable
(2 V/DIV) (2 V/DIV)

VOUT VOUT
(2 V/DIV) (2 V/DIV)

PGOOD PGOOD
(2 V/DIV) (2 V/DIV)

IINDUCTOR IINDUCTOR
(2 A/DIV) (2 A/DIV)
Time (4 ms/DIV) Time (4 ms/DIV)

VIN = 12 V VOUT = 5 V fSW = 400 kHz VIN = 24 V VOUT = 5 V fSW = 400 kHz
No Load FPWM Mode No Load FPWM Mode

Figure 8-18. LM76005-Q1 Start-up Waveform Figure 8-19. LM76005-Q1 Start-up Waveform

Enable Enable
(2 V/DIV) (2 V/DIV)

VOUT VOUT
(2 V/DIV) (2 V/DIV)

PGOOD PGOOD
(2 V/DIV) (2 V/DIV)

IINDUCTOR IINDUCTOR
(5 A/DIV) (5 A/DIV)
Time (4 ms/DIV) Time (4 ms/DIV)

VIN = 12 V VOUT = 5 V fSW = 400 kHz VIN = 24V VOUT = 5 V fSW = 400 kHz
5-A Load 5-A Load

Figure 8-20. LM76005-Q1 Start-up Waveform Figure 8-21. LM76005-Q1 Start-up Waveform

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Enable Enable
(2 V/DIV) (2 V/DIV)

VOUT VOUT
(2 V/DIV) (2 V/DIV)

PGOOD PGOOD
(2 V/DIV) (2 V/DIV)

IINDUCTOR IINDUCTOR
(2 A/DIV) (2 A/DIV)
Time (4 ms/DIV) Time (4 ms/DIV)

VIN = 12 V VOUT = 5 V fSW = 400 kHz VIN = 24V VOUT = 5 V fSW = 400 kHz
No Load Auto Mode No Load Auto Mode

Figure 8-22. LM76005-Q1 Start-up With Pre-Biased Figure 8-23. LM76005-Q1 Start-up With Pre-Biased
Output Output

VOUT VOUT
(1 V/DIV) (1 V/DIV)

IINDUCTOR IINDUCTOR
(2 A/DIV) (2 A/DIV)

VSW VSW
(5 V/DIV) (10 V/DIV)

Time (40 ms/DIV) Time (40 ms/DIV)

VIN = 12 V VOUT = 5 V fSW = 400 kHz VIN = 24 V VOUT = 5 V fSW = 400 kHz
Auto Mode Auto Mode

Figure 8-24. LM76005-Q1 Short-Circuit Behavior Figure 8-25. LM76005-Q1 Short-Circuit Behavior
With Hiccup With Hiccup

LW_PK5 VHF1-PK5
MW_PK5 VHF2-PK5 FM-PK5
LW_AV5 SW PK5
TVI-PK5
CB_PK5
MW_AV5 VHF1-AV5 TVI-AV5
SW AV5
CB_AV5 VHF2-AV5 FM-AV5

Peak Limit Peak Limit

Average Limit Average Limit
Peak Value Peak Value
Average Value Average Value

VIN = 13.5 V VOUT = 5 V fSW = 400 kHz VIN = 13.5 V VOUT = 5 V fSW = 400 kHz
CFLT = 4 × 2.2 µF, LFLT = 1 µH IOUT = 3.5 A CFLT = 4 × 2.2 µF, LFLT = 1 µH IOUT = 3.5 A

Figure 8-26. LM76005-Q1 Conducted EMI Result Figure 8-27. LM76005-Q1 Conducted EMI Result
vs. CISPR25 Limits - Low Frequency vs. CISPR25 Limits - High Frequency

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50 50
Peak_Limit
Peak_Limit
45 Peak detector _Horizontal_Log
Peak detector _Horizontal_Bicon 45
Peak detector _Vertical_Bicon Peak detector _Vertical_Log
40
40
35

Level in dBµV/m
35
Level in dBµV/m

30

25 30

20
25

15
20
10

15
5

0 10
30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 200 300 400 500 600 700 800 900 1000

Frequency (MHz) Frequency (MHz)

VIN = 13.5 V VOUT = 5 V fSW = 400 kHz VIN = 13.5 V VOUT = 5 V fSW = 400 kHz

CFLT = 4 × 2.2 µF, IOUT = 3.5 A CFLT = 4 × 2.2 µF, IOUT = 3.5 A
LFLT = 1 µH LFLT = 1 µH

Figure 8-28. LM76005-Q1 Radiated EMI Result vs. Figure 8-29. LM76005-Q1 Radiated EMI Result vs.
CISPR25 Limits - Low Frequency CISPR25 Limits - High Frequency

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9 Power Supply Recommendations

The LM76005-Q1 is designed to operate from an input voltage supply range between 3.5 V and 60 V. This input
supply must be able to withstand the maximum input current and maintain a voltage above 3.5 V. The resistance
of the input supply rail must be low enough that an input current transient does not cause a high enough drop at
the LM76005-Q1 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the LM76005-Q1, additional bulk capacitance can be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-µF
or 100-µF electrolytic capacitor is a typical choice.

34 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: LM76005-Q1

 LM76005-Q1
www.ti.com SNVSBK6A – FEBRUARY 2020 – REVISED JULY 2020

10 Layout
10.1 Layout Guidelines
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and
minimum generation of unwanted EMI.
1. Place ceramic high frequency bypass CIN as close as possible to the LM76005-Q1 PVIN and PGND pins.
Grounding for both the input and output capacitors must consist of localized top-side planes that connect to
the PGND pins and PAD.
2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to device
ground.
3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB, must be located close to the FB
pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT sense
is made at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on the
other side of a shielding layer.
4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path. Have a single
point ground connection to the plane. Route the ground connections for the feedback, soft start, and enable
components to the ground plane. This prevents any switched or load currents from flowing in the analog
ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output
voltage ripple behavior.
5. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
6. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking
to keep the junction temperature below 125°C.
10.1.1 Layout Highlights
1. Minimize the area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize
the high di/dt paths during PC board layout as shown in the figure above. The high current loops that do not
overlap have high di/dt content that causes observable high frequency noise on the output pin if the input
capacitor CIN is placed at a distance away from the LM76005-Q1. Therefore, place CIN as close as possible
to the LM76005-Q1 PVIN and PGND pins. This minimizes the high di/dt area and reduce radiated EMI.
Additionally, grounding for both the input and output capacitor must consist of a localized top-side plane that
connects to the PGND pin.
2. Have a single point ground. The ground connections for the feedback, soft-start, and enable components
must be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in the
analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic
output voltage ripple behavior.
3. Minimize trace length to the FB pin net. Place both feedback resistors, RFBT and RFBB, close to the FB pin.
Because the FB node is high impedance, maintain the copper area as small as possible. Route the traces
from RFBT, RFBB away from the body of the LM76005-Q1 to minimize possible noise pickup. Place Cff directly
in parallel with RFBT.
4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a
separate feedback voltage sense trace is made to the load. Doing so corrects for voltage drops and provide
optimum output accuracy.
5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. For best results use a 10 × 10 via array (or greater)
with a minimum via diameter of 12 mil thermal vias spaced 46.8 mil apart. Ensure enough copper area is
used for heat-sinking to keep the junction temperature below 125°C.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 35

Product Folder Links: LM76005-Q1
LM76005-Q1
SNVSBK6A – FEBRUARY 2020 – REVISED JULY 2020 www.ti.com

10.1.2 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
the area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In buck
converters, the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch,
and then return to the ground of the input capacitors, as shown in Figure 10-1.
BUCK
CONVERTER
VIN PVIN SW L VOUT

CIN COUT

PGND PGND
High di/dt current

Figure 10-1. Buck Converter High di / dt Path

High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of
the pulsing current. Placing ceramic bypass capacitor or capacitors as close as possible to the PVIN and PGND
pins is the key to EMI reduction. The SW pin connecting to the inductor must be as short as possible, and just
wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes)
must be used for high current conduction path to minimize parasitic resistance. The output capacitors must be
placed close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. Place the
bypass capacitors on VCC and BIAS pins as close as possible to the pins respectively and closely grounded to
PGND and the exposed PAD.
10.1.3 Ground Plane and Thermal Considerations
TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the
AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins are
connected to the source of the internal LS switch; connect the PGND pins directly to the grounds of the input
and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to load
variations. The PGND trace, as well as PVIN and SW traces, must be constrained to one side of the ground
plane. The other side of the ground plane contains much less noise — use for sensitive routes.
Provide adequate device heat sinking by utilizing the PAD of the device as the primary thermal path. Use a
minimum 4 x 4 array of 10-mil thermal vias to connect the PAD to the system ground plane for heat sinking.
Distribute the vias evenly under the PAD. Use as much copper as possible for system ground plane on the top
and bottom layers for the best heat dissipation. TI recommends using a four-layer board with the copper
thickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough
copper thickness and proper layout provides low current conduction impedance, proper shielding and lower
thermal resistance.
The thermal characteristics of the LM76005-Q1 are specified using the parameter RθJA, which characterize the
junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is
dependant on many variables, it still can be used to approximate the operating junction temperature of the
device.
To obtain an estimate of the device junction temperature, you can use the following relationship:

TJ = PD × RθJA + TA (28)

where
• TJ = junction temperature in °C
• PD = VIN × IIN × (1 − efficiency) − (1.1 × (IOUT)2× DCR)
• DCR = inductor DC parasitic resistance in Ω

36 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: LM76005-Q1

 LM76005-Q1
www.ti.com SNVSBK6A – FEBRUARY 2020 – REVISED JULY 2020

• RθJA = junction-to-ambient thermal resistance of the device in °C/W

• TA = ambient temperature in °C.
The maximum operating junction temperature of the LM76005-Q1 is 125°C. RθJA is highly related to PCB size
and layout, as well as environmental factors such as heat sinking and air flow. Figure 10-2 shows measured
results of RθJA with different copper area on a 2-layer board and a 4-layer board.
30

28 1W @0 fpm - 2layer
1W @0 fpm - 4layer
26
2W @0 fpm - 2layer
24 2W @0 fpm - 4layer
R,JA (°C/W)

22

20

18

16

14

12

10
20 30mm 30
× 30mm 40mm 40
× 40mm 50mm 50
× 50mm 60 70mm 70
×70mm 80

Copper Area

Figure 10-2. Measured RθJA versus PCB Copper Area on a 2-Layer Board and a 4-Layer Board

10.1.4 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and
CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces
the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace
from VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for
voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider must be routed away from the SW node path, the inductor, and VIN path to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. TI recommends routing the voltage sense
trace on a different layer than the inductor, SW node, and VIN path, such that there is a ground plane in between
the feedback trace and inductor / SW node / VIN polygon. This provides further shielding for the voltage
feedback path from switching noises.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 37

Product Folder Links: LM76005-Q1
LM76005-Q1
SNVSBK6A – FEBRUARY 2020 – REVISED JULY 2020 www.ti.com

10.2 Layout Example

LM76005-Q1

Figure 10-3. LM76005-Q1 Layout

38 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: LM76005-Q1

 LM76005-Q1
www.ti.com SNVSBK6A – FEBRUARY 2020 – REVISED JULY 2020

11 Device and Documentation Support

11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM76005-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.6 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 39

Product Folder Links: LM76005-Q1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Dec-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LM76005QRNPRQ1 ACTIVE WQFN RNP 30 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 LM76005R Samples
NPQ1

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Dec-2022

OTHER QUALIFIED VERSIONS OF LM76005-Q1 :

• Catalog : LM76005

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM76005QRNPRQ1 WQFN RNP 30 3000 330.0 12.4 4.3 6.3 1.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM76005QRNPRQ1 WQFN RNP 30 3000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RNP 30 WQFN - 0.8 mm max height
4 x 6, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225831/A

www.ti.com
 PACKAGE OUTLINE
RNP0030B SCALE 2.700
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4.1 B
A
3.9

PIN 1 INDEX AREA

6.1
5.9

0.1 MIN

(0.05)

SECTION A-A
SECTION A-A
SCALE 25.000

TYPICAL
0.8 MAX
C

SEATING PLANE
0.05
0.00 0.08 C

1.8 0.1
2X 1.5 (0.2) TYP
EXPOSED
12 15 THERMAL PAD
26X 0.5
11
16

SYMM 31 A A
2X 4.5 0.1
5

1 26
0.3
PIN 1 ID 30 27 30X
0.5 SYMM 0.2
(OPTIONAL) 8X
0.3 0.1 C A B
0.65 0.05 C
22X
0.45
4222784/B 09/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RNP0030B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(1.8)
SYMM
30 8X (0.6)
27
22X (0.75)

1
26

30X (0.25)

(0.5) TYP (1.14)

TYP
SYMM 31 (5.8)
(4.5)
(0.57)

(R0.05) TYP

( 0.2) TYP
VIA

11 16

12 15
(0.65) TYP
(3.65)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

METAL SOLDER MASK

OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4222784/B 09/2017
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RNP0030B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

8X (0.8)
8X (0.6)
30 27
22X (0.75)

1
26
31
30X (0.25)

8X
(0.94)

26X (0.5)

SYMM (5.8)

(0.57)
TYP

(1.14)
TYP

METAL
TYP

11 16

(R0.05) TYP

12 15
SYMM

(0.5) TYP
(3.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 31:

74.3% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4222784/B 09/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
RNP0030E SCALE 2.700
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4.1 B
A
3.9

PIN 1 INDEX AREA

6.1
5.9

0.1 MIN

(0.13)

SECTION A-A
SECTION A-A
SCALE 25.000

0.8 TYPICAL
0.7
C

SEATING PLANE
0.05
0.00 0.08 C
1.8 0.1
2X 1.5
EXPOSED (0.2) TYP
12 15 THERMAL PAD
26X 0.5
11
16
(0.16)

SYMM 31 A A
2X 4.5 0.1
5

1 26
30 27 0.3
PIN 1 ID 30X
SYMM 0.2
(OPTIONAL)
0.5 0.1 C A B
8X
0.3 0.05 C
0.65
22X
0.45
4227136/A 10/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RNP0030E WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(1.8)
SYMM
30 8X (0.6)
27
22X (0.75)

1
26

30X (0.25)

(0.5) TYP (1.14)

TYP
SYMM 31 (5.8)
(4.5)
(0.57)

(R0.05) TYP

( 0.2) TYP
VIA

11 16

12 15
(0.65) TYP
(3.65)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

METAL SOLDER MASK

OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4227136/A 10/2021
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RNP0030E WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

8X (0.8)
8X (0.6)
30 27
22X (0.75)

1
26
31
30X (0.25)

8X
(0.94)

26X (0.5)

SYMM (5.8)

(0.57)
TYP

(1.14)
TYP

METAL
TYP

11 16

(R0.05) TYP

12 15
SYMM

(0.5) TYP
(3.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 31:

74.3% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4227136/A 10/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
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