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LM26001, LM26001-Q1
SNVS430I – MAY 2006 – REVISED MARCH 2015

LM26001/-Q1 1.5-A Switching Regulator With High-Efficiency Sleep Mode

1 Features 3 Description
1• LM26001-Q1 is an Automotive-Grade Product that The LM26001 is a switching regulator designed for
is AEC-Q100 Grade 1 Qualified (–40°C to +125°C the high-efficiency requirements of applications with
standby modes. The device features a low-current
Operating Junction Temperature)
sleep mode to maintain efficiency under light-load
• High-Efficiency Sleep Mode conditions and current-mode control for accurate
• 40-µA Typical Iq in Sleep Mode regulation over a wide input voltage range. Quiescent
• 10-µA Typical Iq in Shutdown Mode current is reduced to 10 µA typically in shutdown
mode and less than 40 µA in sleep mode. Forced
• 3.0-V Minimum Input Voltage PWM mode is also available to disable sleep mode.
• 4.0-V to 38-V Continuous Input Range
The LM26001 can deliver up to 1.5 A of continuous
• 1.5% Reference Accuracy load current with a fixed current limit, through the
• Cycle-by-Cycle Current Limit internal N-channel switch. The part has a wide input
• Adjustable Frequency (150 kHz to 500 kHz) voltage range of 4.0 V to 38 V and can operate with
input voltages as low as 3 V during line transients.
• Synchronizable to an External Clock
• Power Good Flag Operating frequency is adjustable from 150 kHz to
500 kHz with a single resistor and can be
• Forced PWM Function synchronized to an external clock.
• Adjustable Soft-Start
Other features include Power Good, adjustable soft-
• HTSSOP-16 Exposed Pad Package start, enable pin, input undervoltage protection, and
• Thermal Shut Down an internal bootstrap diode for reduced component
count.
2 Applications
Device Information(1)
• Automotive Telematics
PART NUMBER PACKAGE BODY SIZE (NOM)
• Navigation Systems
LM26001
• In-Dash Instrumentation HTSSOP (16) 5.00 mm x 4.40 mm
LM26001-Q1
• Battery-Powered Applications
(1) For all available packages, see the orderable addendum at
• Standby Power for Home Gateways/Set-top the end of the datasheet.
Boxes
Typical Application Circuit
VIN
1 12
VIN VBIAS
VOUT
2 16
C1 VIN SW
15 L
3
PGOOD SW +
C4 C6
4 14 D1 R1
R4 EN BOOT
EN LM26001
11 7
VDD SYNC FB
5 6
SS COMP
SYNC 9 13
FREQ VDD C8
C5 R2
10 8
R6 FPWM GND
R3 EP C3
R5
17

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM26001, LM26001-Q1
SNVS430I – MAY 2006 – REVISED MARCH 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 16
2 Applications ........................................................... 1 8 Applications and Implementation ...................... 17
3 Description ............................................................. 1 8.1 Application Information............................................ 17
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 17
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 23
6 Specifications......................................................... 4 10 Layout................................................................... 23
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 23
6.2 ESD Ratings - LM26001 ........................................... 4 10.2 Layout Example .................................................... 24
6.3 ESD Ratings - LM26001-Q1 ..................................... 4 10.3 Thermal Considerations and TSD......................... 24
6.4 Recommended Operating Conditions....................... 5 11 Device and Documentation Support ................. 25
6.5 Thermal Information .................................................. 5 11.1 Documentation Support ........................................ 25
6.6 Electrical Characteristics........................................... 5 11.2 Related Links ........................................................ 25
6.7 Typical Characteristics .............................................. 8 11.3 Trademarks ........................................................... 25
7 Detailed Description ............................................ 11 11.4 Electrostatic Discharge Caution ............................ 25
7.1 Overview ................................................................. 11 11.5 Glossary ................................................................ 25
7.2 Functional Block Diagram ....................................... 11 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 12 Information ........................................................... 25

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (November 2014) to Revision I Page

• Update made to the Power Dissipation description in Section 6.1 ....................................................................................... 4

• Changed ESD Ratings to ± and moved storage temp to Absolute Maximum Ratings .......................................................... 4

Changes from Revision G (April 2013) to Revision H Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1

Changes from Revision F (April 2013) to Revision G Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 24

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5 Pin Configuration and Functions

16-Pin
HTSSOP Package
Top View

VIN 1 16 SW
VIN 2 15 SW
PGOOD 3 14 BOOT
EN 4 13 VDD
SS 5 12 VBIAS
COMP 6 11 SYNC
FB 7 10 FPWM
GND 8 9 FREQ

Exposed Pad
Connect to GND

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 VIN A Power supply input
2 VIN A Power supply input
3 PGOOD O Power Good pin. An open-drain output which goes high when the output voltage is greater than
92% of nominal.
4 EN I Enable is an analog level input pin. When pulled below 0.8 V, the device enters shutdown mode.
5 SS A Soft-start pin. Connect a capacitor from this pin to GND to set the soft-start time.
6 COMP A Compensation pin. Connect to a resistor capacitor pair to compensate the control loop.
7 FB A Feedback pin. Connect to a resistor divider between Vout and GND to set output voltage.
8 GND G Ground
9 FREQ A Frequency adjust pin. Connect a resistor from this pin to GND to set the operating frequency.
10 FPWM I FPWM is a logic level input pin. For normal operation, connect to GND. When pulled high, sleep
mode operation is disabled.
11 SYNC I Frequency synchronization pin. Connect to an external clock signal for synchronized operation.
SYNC must be pulled low for non-synchronized operation.
12 VBIAS A Connect to an external 3-V or greater supply to bypass the internal regulator for improved efficiency.
If not used, VBIAS should be tied to GND.
13 VDD A The output of the internal regulator. Bypass with a minimum 1.0-µF capacitor.
14 BOOT A Bootstrap capacitor pin. Connect a 0.1-µF minimum ceramic capacitor from this pin to SW to
generate the gate drive bootstrap voltage.
15 SW A Switch pin. The source of the internal N-channel switch.
16 SW A Switch pin. The source of the internal N-channel switch.
EP EP G Exposed Pad thermal connection. Connect to GND.

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6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
MIN MAX UNIT
VIN –0.3 40 V
SW (3) –0.5 40 V
VDD –0.3 7 V
VBIAS –0.3 10 V
FB –0.3 6 V
Voltages
BOOT SW-0.3 SW+7 V
from the
indicated PGOOD –0.3 7 V
pins to
FREQ –0.3 7 V
GND
SYNC –0.3 7 V
EN –0.3 40 V
FPWM –0.3 y7 V
SS –0.3 7 V
Power Dissipation (4) (5) 2.6 W
Recomme Vapor Phase (70s) 215 °C
nded Lead
Infrared (15s) 220 °C
Temperatu
re
Storage Tstg –65 150 °C
temperatur
e

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications
and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The absolute maximum specification applies to DC voltage. An extended negative voltage limit of -2V applies for a pulse of up to 1 µs,
and –1 V for a pulse of up to 20 µs.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PD_MAX = (TJ_MAX - TA) /θJA. The maximum power dissipation of 2.6W is determined using TA = 25°C, θJA = 38°C/W, and
TJ_MAX = 125°C. The number stated here reflects the maximum power dissipation for the package and not the device.
(5) For Device Power Dissipation, please refer to section 10.3.

6.2 ESD Ratings - LM26001

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins ±2
Charged device model (CDM), per JEDEC specification JESD22-C101, ±1 kV
V(ESD) Electrostatic discharge
all pins (2)
Machine model ± 200 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings - LM26001-Q1

VALUE UNIT
Human body model (HBM), per AEC Q100-002 (1) ±2
Corner pins (1, 8, 9, and ±1
Charged device model (CDM), per AEC kV
V(ESD) Electrostatic discharge 16)
Q100-011
Other pins ±1
Machine model ± 200 V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating Junction Temp. –40 125 °C
Supply Voltage (1) 3.0 38 V

(1) Below 4.0-V input, power dissipation may increase due to increased RDS(ON). Therefore, a minimum input voltage of 4.0 V is required to
operate continuously within specification. A minimum of 3.9 V (typical) is also required for startup.

6.5 Thermal Information

LM26001
(1)
THERMAL METRIC PWP UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 38.8
RθJC(top) Junction-to-case (top) thermal resistance 23.0
RθJB Junction-to-board thermal resistance 16.7
°C/W
ψJT Junction-to-top characterization parameter 0.6
ψJB Junction-to-board characterization parameter 16.4
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

Unless otherwise stated, Vin=12 V. Minimum and Maximum limits are ensured through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM
ISD (2) Shutdown Current EN = 0 V 10.8 µA
EN = 0 V, –40°C ≤ TJ ≤ 125°C 20
Iq_Sleep_VB (2) Quiescent Current Sleep mode, VBIAS = 5 V 38 µA
Sleep mode, VBIAS = 5 V, –40°C 70
≤ TJ ≤ 125°C
Iq_Sleep_VDD Quiescent Current Sleep mode, VBIAS = GND 75 µA
Sleep mode, VBIAS = GND, 125
–40°C ≤ TJ ≤ 125°C
Iq_PWM_VB Quiescent Current PWM mode, VBIAS = 5 V 150 230 µA
Iq_PWM_VDD Quiescent Current PWM mode, VBIAS = GND 0.65 0.85 mA
IBIAS_Sleep (2) Bias Current Sleep mode, VBIAS = 5 V 33 µA
Sleep mode, VBIAS = 5 V, –40°C 85
≤ TJ ≤ 125°C
IBIAS_PWM Bias Current PWM mode, VBIAS = 5 V 0.5 0.70 mA
VFB Feedback Voltage 5 V < Vin < 38 V 1.234 V
5 V < Vin < 38 V, –40°C ≤ TJ ≤ 1.2155 1.2525
125°C
IFB FB Bias Current ±200 nA
ΔVOUT/ΔVIN Vout line regulation 5 V < Vin < 38 V 0.001 %/V
ΔVOUT/ΔIOUT Vout load regulation 0.8 V < VCOMP < 1.15 V 0.07%
VDD VDD output voltage 7 V < Vin < 35 V, IVDD= 0 mA to 5 5.95 V
mA
7 V < Vin < 35 V, IVDD= 0 mA to 5 5.50 6.50
mA, –40°C ≤ TJ ≤ 125°C

(1) All room temperature limits are 100% production tested. All limits at temperature extremes are ensured through correlation using
standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Iq and ISD specify the current into the VIN pin. IBIAS is the current into the VBIAS pin when the VBIAS voltage is greater than 3 V. All
quiescent current specifications apply to non-switching operation.
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Electrical Characteristics (continued)

Unless otherwise stated, Vin=12 V. Minimum and Maximum limits are ensured through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISS_Source Soft-start source current 2.2 µA
–40°C ≤ TJ ≤ 125°C 1.5 4.6
Vbias_th VBIAS On Voltage Specified at IBIAS = 92.5% of full 2.64 2.9 3.07 V
value
SWITCHING
RDS(ON) Switch on Resistance Isw = 1A 0.2 Ω
Isw = 1A, –40°C ≤ TJ ≤ 125°C 0.12 0.42
Isw_off Switch off state leakage current Vin = 38 V, VSW = 0 V 0.002 µA
Vin = 38 V, VSW = 0 V, –40°C ≤ 5.0
TJ ≤ 125°C
fsw Switching Frequency RFREQ = 62k, 124k, 240k ±10%
VFREQ FREQ voltage 1.0 V
fSW range Switching Frequency range –40°C ≤ TJ ≤ 125°C 150 500 kHz
VSYNC Sync pin threshold SYNC rising 1.2 V
SYNC rising, –40°C ≤ TJ ≤ 125°C 1.6
SYNC falling 1.1
SYNC falling, –40°C ≤ TJ ≤ 125°C 0.8
Sync pin hysteresis 114 mV
ISYNC SYNC leakage current 6 nA
FSYNC_UP Upper frequency synchronization range As compared to nominal fSW, 30%
–40°C ≤ TJ ≤ 125°C
FSYNC_DN Lower frequency synchronization range As compared to nominal fSW, –20%
–40°C ≤ TJ ≤ 125°C
TOFFMIN Minimum Off-time 365 ns
TONMIN Minimum On-time 155 ns
THSLEEP_HYS Sleep mode threshold hysteresis VFB rising, % of THWAKE 101.2%
THWAKE Wake up threshold Measured at falling FB, COMP = 1.234 V
0.6 V
IBOOT BOOT pin leakage current BOOT = 16 V, SW = 10 V 0.0006 µA
BOOT = 16 V, SW = 10 V, –40°C 5.0
≤ TJ ≤ 125°C
PROTECTION
ILIMPK Peak Current Limit 2.5 A
–40°C ≤ TJ ≤ 125°C 1.85 3.2
VFB_SC Short circuit frequency foldback Measured at FB falling 0.87 V
threshold
F_min_sc Min Frequency in foldback VFB < 0.3 V 71 kHz
VTH_PGOOD Power Good Threshold Measured at FB, PGOOD rising 92%
Measured at FB, PGOOD rising, 89% 95%
–40°C ≤ TJ ≤ 125°C
PGOOD hysteresis 2% 7% 8%
IPGOOD_HI PGOOD leakage current PGOOD = 5 V 0.2 nA
RDS_PGOOD PGOOD on resistance PGOOD sink current = 500 µA 64 Ω

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Electrical Characteristics (continued)

Unless otherwise stated, Vin=12 V. Minimum and Maximum limits are ensured through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO Under-voltage Lock-Out Threshold Vin falling , shutdown, VDD = VIN 2.9 V
Vin falling , shutdown, VDD = VIN, 2.60 3.20
–40°C ≤ TJ ≤ 125°C
Vin rising, soft-start, VDD = VIN 3.9
Vin rising, soft-start, VDD = VIN, 3.60 4.20
–40°C ≤ TJ ≤ 125°C
TSD Thermal Shutdown Threshold 160 °C
θJA Thermal resistance Power dissipation = 1W, 0 lfpm air 38 °C/W
flow
LOGIC
VthEN Enable Threshold voltage 1.2 V
–40°C ≤ TJ ≤ 125°C 0.8 1.4
Enable hysteresis 120 mV
IEN_Source EN source current EN = 0 V 4.5 µA
VTH_FPWM FPWM threshold 1.2 V
–40°C ≤ TJ ≤ 125°C 0.8 1.6
IFPWM FPWM leakage current FPWM = 5 V 35 nA
EA
gm Error amp trans-conductance 670 µmho
–40°C ≤ TJ ≤ 125°C 400 1000
ICOMP COMP source current VCOMP = 0.9 V 56 µA
COMP sink current VCOMP = 0.9 V 56 µA
VCOMP COMP pin voltage range 0.64 1.27 V

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6.7 Typical Characteristics

Unless otherwise specified the following conditions apply: VIN = 12 V, TJ = 25°C.

1.236 1.236

1.234 1.235

VFB (V)
VFB (V)

1.232 1.234

1.230 1.233

1.228 1.232
-40 -20 0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 40

TEMPERATURE (ºC) VIN (V)

Figure 1. VFB vs Temperature Figure 2. VFB vs Vin (IDC = 300 mA)
90 700 IQ
IQ (VBIAS=0V)
80 (VBIAS=0V)
600

70
500
CURRENT (PA)

CURRENT (PA)

60 IVBIAS
(VBIAS=5V)
400
50 IVBIAS
(VBIAS=5V)
300
40

IQ 200 IQ
30 (VBIAS=5V)
(VBIAS=5V)

20 100
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140

TEMPERATURE (ºC) TEMPERATURE (ºC)

Figure 3. IQ and IVBIAS vs Temperature (Sleep Mode) Figure 4. IQ and IVBIAS vs Temperature (PWM Mode)
102 4.1

3.9
SWITCHING FREQUENCY (%)

On Threshold
101 3.7

3.5
VIN (V)

100 3.3

3.1
Off Threshold
99 2.9

2.7

98 2.5
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (ºC) TEMPERATURE (ºC)
Figure 5. Normalized Switching Frequency vs Temperature Figure 6. UVLO Threshold vs Temperature (VDD = VIN)
(300 kHz)

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Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: VIN = 12 V, TJ = 25°C.
3.0 350

300

SWITCHING FREQUENCY (kHz)

2.8
250
ILIM PEAK (A)

2.6 200

150
2.4

100
2.2
50

2.0 0
-40 -20 0 20 40 60 80 100 120 140 0.2 0.4 0.6 0.8 1.0 1.2

TEMPERATURE (ºC) VFB (V)

Figure 7. Peak Current Limit vs Temperature Figure 8. Short Circuit Foldback Frequency vs VFB (325 kHz
Nominal)
100 100

5Vout 5Vout
90 EFFICIENCY (%) 90
EFFICIENCY (%)

3.3Vout 3.3Vout
80 80

70 70
FPWM FPWM
mode mode
60 60

50 50
1 10 100 1000 10000 1 10 100 1000 10000

IDC (mA) IDC (mA)

Figure 9. Efficiency vs Load Current (330 kHz) Figure 10. Efficiency vs Load Current (500 kHz)

Vout
Vout
1V/Div
40 mV/Div

PGOOD
5V/Div
Iout
500 mA/Div

SS
1V/Div

EN
10V/Div

1 Ps/DIV 200 Ps/DIV

Figure 11. Startup Waveforms Figure 12. Load Transient Response

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Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: VIN = 12 V, TJ = 25°C.
500
1A 125°C
450

VIN-VOUT DROPOUT (mV)

400
1A 25°C
350
300
250 1A -40°C

200
150
40mA -40°C
100
40mA
50
25 to 125°C
0
3 3.5 4 4.5 5 5.5
VIN (V)
Figure 13. Low Input Voltage Dropout Nominal VOUT = 5 V

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7 Detailed Description

7.1 Overview
The LM26001 is a current mode PWM buck regulator. At the beginning of each clock cycle, the internal high-side
switch turns on, allowing current to ramp up in the inductor. The inductor current is internally monitored during
each switching cycle. A control signal derived from the inductor current is compared to the voltage control signal
at the COMP pin, derived from the feedback voltage. When the inductor current reaches the threshold, the high-
side switch is turned off and inductor current ramps down. While the switch is off, inductor current is supplied
through the catch diode. This cycle repeats at the next clock cycle. In this way, duty cycle and output voltage are
controlled by regulating inductor current. Current mode control provides superior line and load regulation. Other
benefits include cycle by cycle current limiting and a simplified compensation scheme. Typical PWM waveforms
are shown in Figure 14.
Vout
10 mV/Div

IL
500 mA/Div

ID
1A/Div

VSW
5V/Div

1 Ps/DIV

Figure 14. PWM Waveforms 1-A Load, Vin = 12 V

7.2 Functional Block Diagram

VIN

5 PA BG on LDO
IREF UVLO
SD qn VDD
TSD VDD_low
EN

Switchover
fpwm
control
VBIAS
FPWM LG
BG + wake
- VREG Sync and
Sleep bootstrap
Sleep
0.6V Set sleep fpwm control
Reset +
- FPWM / Sleep BOOT
EA Peak Current
- Control
+
FB +
V clamp -
BG +
VIN
blanking I Sense
COMP frequency
foldback Corrective
-
+ ff Ramp
0.9V qn
+
-
- PWM Control
+ PWM Logic
0.92BG SW
Comp
PG
sleep
PGOOD
Clock / Sync SW
LG
- ss end
2 PA +
ff -
+
SS FREQ
VDD_low
SS TSD +
logic on -
soft start SD SYNC

GND EP

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7.3 Feature Description

7.3.1 Sleep Mode
In light load conditions, the LM26001 automatically switches into sleep mode for improved efficiency. As loading
decreases, the voltage at FB increases and the COMP voltage decreases. When the COMP voltage reaches the
0.6-V (typical) clamp threshold, and the FB voltage rises 1% above nominal, sleep mode is enabled and
switching stops. The regulator remains in sleep mode until the FB voltage falls to the reset threshold, at which
point switching resumes. This 1% FB window limits the corresponding output ripple to approximately 1% of
nominal output voltage. The sleep cycle will repeat until load current is increased. Figure 15 shows typical
switching and output voltage waveforms in sleep mode.
Vout
50 mV/Div

IL
200 mA/Div

VSW
5V/Div

100 Ps/DIV

Figure 15. Sleep Mode Waveforms 25-mA Load, Vin = 12 V

In sleep mode, quiescent current is reduced to less than 40 µA when not switching. The DC sleep mode
threshold can be calculated according to the equation below:
2

ISleep = Imin + 0.13 P Vin - Vout x

fsw x L
L D x 2 x (Vin ± Vout) (1)
Where Imin = Ilim/16 (2.5A/16 typically) and D = duty cycle, defined as (Vout + Vdiode)/Vin.
When load current increases above this limit, the LM26001 is forced back into normal PWM operation. The sleep
mode threshold varies with frequency, inductance, and duty cycle as shown in Figure 16.
250

200 500 kHz

150
IDC (mA)

100 22 PH 330 kHz

15 PH
22 PH
50 15 PH

0
0 10 20 30 40

VIN (V)

Figure 16. Sleep Mode Threshold vs Vin Vout = 3.3 V

Below the sleep threshold, decreasing load current results in longer sleep cycles, which can be quantified as
shown below:
Dwake = Iload/Isleep (2)
Where Dwake is the percentage of time awake when the load current is below the sleep threshold.
Sleep mode combined with low IQ operation minimizes the input supply current. Input supply current in sleep
mode can be calculated based on the wake duty cycle, as shown below:

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Feature Description (continued)

Iin = Iq + (IQG x Dwake) + (Io x D) (3)
Where IQG is the gate drive current, calculated as:
IQG = (4.6 x 10-9) x fSW
And Io is the sum of Iload, Ibias, and current through the feedback resistors.
Because this calculation applies only to sleep mode, use the Iq_Sleep_VB and IBIAS_SLEEP values from the Electrical
Characteristics. If VBIAS is connected to ground, use the same equation with Ibias equal to zero and Iq_Sleep_VDD.

7.3.2 FPWM
Pulling the FPWM pin high disables sleep mode and forces the LM26001 to always operate in PWM mode. Light
load efficiency is reduced in PWM mode, but switching frequency remains stable. The FPWM pin can be
connected to the VDD pin to pull it high. In FPWM mode, under light load conditions, the regulator operates in
discontinuous conduction mode (DCM) . In discontinuous conduction mode, current through the inductor starts at
zero and ramps up to its peak, then ramps down to zero again. Until the next cycle, the inductor current remains
at zero. At nominal load currents, in FPWM mode, the device operates in continuous conduction mode, where
positive current always flows in the inductor. Typical discontinuous operation waveforms are shown in Figure 17.
Vout
10 mV/Div

IL
200 mA/Div

VSW
5V/Div

1 Ps/DIV

Figure 17. Discontinuous Mode Waveforms 75-mA Load, Vin = 12 V

At very light load, in FPWM mode, the LM26001 may enter sleep mode. This is to prevent an over-voltage
condition from occurring. However, the FPWM sleep threshold is much lower than in normal operation.

7.3.3 Enable
The LM26001 provides a shutdown function via the EN pin to disable the device when the output voltage does
not need to be maintained. EN is an analog level input with typically 120 mV of hysteresis. The device is active
when the EN pin is above 1.2 V (typical) and in shutdown mode when EN is below this threshold. When EN goes
high, the internal VDD regulator turns on and charges the VDD capacitor. When VDD reaches 3.9 V (typical), the
soft-start pin begins to source current. In shutdown mode, the VDD regulator shuts down and total quiescent
current is reduced to 10 µA (typical). Because the EN pin sources 4.5 µA (typical) of pull-up current, this pin can
be left open for always-on operation. When open, EN will be pulled up to VIN.
If EN is connected to VIN, it must be connected through a 10 kΩ resistor to limit noise spikes. EN can also be
driven externally with a maximum voltage of 38V or VIN + 15V, whichever is lower.

7.3.4 Soft-Start
The soft-start feature provides a controlled output voltage ramp up at startup. This reduces inrush current and
eliminates output overshoot at turn-on. The soft-start pin, SS, must be connected to GND through a capacitor. At
power-on, enable, or UVLO recovery, an internal 2.2 µA (typical) current charges the soft-start capacitor. During
soft-start, the error amplifier output voltage is controlled by both the soft-start voltage and the feedback loop. As
the SS pin voltage ramps up, the duty cycle increases proportional to the soft-start ramp, causing the output
voltage to ramp up. The rate at which the duty cycle increases depends on the capacitance of the soft-start
capacitor. The higher the capacitance, the slower the output voltage ramps up. The soft-start capacitor value can
be calculated with the following equation:
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Feature Description (continued)

Iss x tss
Css =
1.234V (4)
Where tss is the desired soft-start time and Iss is the soft-start source current. During soft-start, current limit and
synchronization remain in effect, while sleep mode and frequency foldback are disabled. Soft-start mode ends
when the SS pin voltage reaches 1.23 V typical. At this point, output voltage control is transferred to the FB pin
and the SS pin is discharged.

7.3.5 Current Limit

The peak current limit is set internally by directly measuring peak inductor current through the internal switch. To
ensure accurate current sensing, VIN should be bypassed with a minimum 1-µF ceramic capacitor placed directly
at the pin.
When the inductor current reaches the current limit threshold, the internal FET turns off immediately allowing
inductor current to ramp down until the next cycle. This reduction in duty cycle corresponds to a reduction in
output voltage.
The current limit comparator is disabled for less than 100 ns at the leading edge for increased immunity to
switching noise.
Because the current limit monitors peak inductor current, the DC load current limit threshold varies with
inductance and frequency. Assuming a minimum current limit of 1.85A, maximum load current can be calculated
as follows:
Iripple
Iloadmax = 1.85A -
2
(5)
Where Iripple is the peak-to-peak inductor ripple current, calculated as shown below:
(Vin ± Vout) x Vout
Iripple =
fsw x L x Vin (6)
To find the worst case (lowest) current limit threshold, use the maximum input voltage and minimum current limit
specification.
During high over-current conditions, such as output short circuit, the LM26001 employs frequency foldback as a
second level of protection. If the feedback voltage falls below the short circuit threshold of 0.9 V, operating
frequency is reduced, thereby reducing average switch current. This is especially helpful in short circuit
conditions, when inductor current can rise very high during the minimum on-time. Frequency reduction begins at
20% below the nominal frequency setting. The minimum operating frequency in foldback mode is 71 kHz typical.
If the FB voltage falls below the frequency foldback threshold during frequency synchronized operation, the
SYNC function is disabled. Operating frequency versus FB voltage in short circuit conditions is shown in the
Typical Characteristics section.
Under conditions where the on time is close to minimum (less than 200 nsec typically), such as high input
voltage and high switching frequency, the current limit may not function properly. This is because the current limit
circuit cannot reduce the on-time below minimum which prevents entry into frequency foldback mode. There are
two ways to ensure proper current limit and foldback operation under high input voltage conditions. First, the
operating frequency can be reduced to increase the nominal on time. Second, the inductor value can be
increased to slow the current ramp and reduce the peak over-current.

7.3.6 Frequency Adjustment and Synchronization

The switching frequency of the LM26001 can be adjusted between 150 kHz and 500 kHz using a single external
resistor. This resistor is connected from the FREQ pin to ground as shown in the typical application. The resistor
value can be calculated with the following empirically derived equation:
RFREQ = (6.25 x 1010) x fSW-1.042 (7)

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Feature Description (continued)

600

SWITCHING FREQUENCY (kHz)

500

400

300

200

100
0 50 100 150 200 250 300

RFREQ (k:)

Figure 18. Switching Frequency vs RFREQ

The switching frequency can also be synchronized to an external clock signal using the SYNC pin. The SYNC
pin allows the operating frequency to be varied above and below the nominal frequency setting. The adjustment
range is from 30% above nominal to 20% below nominal. External synchronization requires a 1.2V (typical) peak
signal level at the SYNC pin. The FREQ resistor must always be connected to initialize the nominal operating
frequency. The operating frequency is synchronized to the falling edge of the SYNC input. When SYNC goes
low, the high-side switch turns on. This allows any duty cycle to be used for the sync signal when synchronizing
to a frequency higher than nominal. When synchronizing to a lower frequency, however, there is a minimum duty
cycle requirement for the SYNC signal, given in the equation below:
fsync
Sync_Dmin t 1 -
fnom (8)
Where fnom is the nominal switching frequency set by the FREQ resistor, and fsync is a square wave. If the
SYNC pin is not used, it must be pulled low for normal operation. A 10 kΩ pull-down resistor is recommended to
protect against a missing sync signal. Although the LM26001 is designed to operate at up to 500 kHz, maximum
load current may be limited at higher frequencies due to increased temperature rise. See the Thermal
Considerations and TSD section.

7.3.7 VBIAS
The VBIAS pin is used to bypass the internal regulator which provides the bias voltage to the LM26001. When
the VBIAS pin is connected to a voltage greater than 3 V, the internal regulator automatically switches over to the
VBIAS input. This reduces the current into VIN (Iq) and increases system efficiency. Using the VBIAS pin has the
added benefit of reducing power dissipation within the device.
For most applications where 3 V < Vout < 10V, VBIAS can be connected to Vout. If not used, VBIAS should be
tied to GND.
If VBIAS drops below 2.9 V (typical), the device automatically switches over to supply the internal bias voltage
from Vin.

7.3.8 Low VIN Operation and UVLO

The LM26001 is designed to remain operational during short line transients when input voltage may drop as low
as 3.0 V. Minimum nominal operating input voltage is 4.0 V. Below this voltage, switch RDS(ON) increases, due to
the lower gate drive voltage from VDD. The minimum voltage required at VDD is approximately 3.5 V for normal
operation within specification.
VDD can also be used as a pull-up voltage for functions such as PGOOD and FPWM. Note that if VDD is used
externally, the pin is not recommended for loads greater than 1 mA.

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Feature Description (continued)

If the input voltage approaches the nominal output voltage, the duty cycle is maximized to hold up the output
voltage. In this mode of operation, once the duty cycle reaches its maximum, the LM26001 can skip a maximum
of seven off pulses, effectively increasing the duty cycle and thus minimizing the dropout from input to output.
Typical off-pulse skipping waveforms are shown in Figure 19.

Vout
20 mV/Div

IL
100 mA/Div

VSW
2V/Div

4 Ps/DIV

Figure 19. Off-pulse Skipping Waveforms Vin = 3.5 V, Vnom = 3.3 V, fnom = 305 kHz

UVLO is sensed at both VIN and VDD, and is activated when either voltage falls below 2.9 V (typical). Although
VDD is typically less than 200 mV below VIN, it will not discharge through VIN. Therefore when the VIN voltage
drops rapidly, VDD may remain high, especially in sleep mode. For fast line voltage transients, using a larger
capacitor at the VDD pin can help to hold off a UVLO shutdown by extending the VDD discharge time. By
holding up VDD, a larger cap can also reduce the RDS(ON) (and dropout voltage) in low VIN conditions.
Alternately, under heavy loading the VDD voltage can fall several hundred mV below VIN. In this case, UVLO
may be triggered by VDD even though the VIN voltage is above the UVLO threshold.
When UVLO is activated the LM26001 enters a standby state in which VDD remains charged. As input voltage
and VDD voltage rise above 3.9 V (typical) the device will restart from softstart mode.

7.3.9 PGOOD
A power good pin, PGOOD, is available to monitor the output voltage status. The pin is internally connected to
an open-drain MOSFET, which remains open while the output voltage is within operating range. PGOOD goes
low (low impedance to ground) when the output falls below 85% of nominal or EN is pulled low. When the output
voltage returns to within 92% of nominal, as measured at the FB pin, PGOOD returns to a high state. For
improved noise immunity, there is a 5 µs delay between the PGOOD threshold and the PGOOD pin going low.

7.4 Device Functional Modes

The LM26001 has three basic operation mode: Shutdown, Sleep or light load operation and full operation.
The part enters shutdown mode when the EN pin is pulled low. In this mode the converter is disabled and the
quiescent current minimized See Enable for more details.
The part enters sleep mode when the converter is active (EN high) and the output current is low. Sleep mode is
activated as the COMP voltage naturally falls below a typical 0.6V threshold in light load operation. When
operating in sleep mode, the switching events of the converter are reduced in order to lower the current
consumption of the system. Forcing the FPWM pin high will prevent sleep mode operation. For details of
operation in sleep mode as well as entering and exiting sleep mode. See Sleep Mode.
When the part in enabled and the output load is higher, the part will be in full PWM operation.
In addition to these normal functioning modes, the LM26001 has a frequency foldback operating mode which
reduces the operating frequency to protect from short circuits. See Current Limit.

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8 Applications and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM26001 offers efficient step-down function meeting the requirements of automotive applications. Current
mode control ensures smooth and safe operation thanks to its cycle by cycle current limiting function. Its low
minimum ON time allows it to operate over a wide range of output voltages. The following sections detail the
steps required for designing a successful application with the LM26001 from component selection to layout.

8.2 Typical Application

Figure 20 shows a complete typical application schematic. The components have been selected based on the
design criteria given in the following sections.
VIN : 4V - 38V

+ C2 C1
47 PF 3.3 PF L
1 12 22 PH
50V 50V VIN VBIAS
3.5A VOUT : 3.3V
2 16
VIN SW
3 15 C6
PGOOD SW D1 +
PGOOD C4 3A R1 100 PF
R4 4 14 0.1 PF 60V 56k 12 m:
200k EN BOOT
1%
EN LM26001
11 7
VDD SYNC FB
5 6
SS COMP Ref # Manufacturer Part Number
SYNC 9 13 C8 R2 C1 TDK 3225JB1H335K
C5 FREQ VDD 4.7 nF 33k
10 nF 1% C2 Panasonic EEVFK1H470P
R6 10 8 C9
R3 FPWM GND C6 Panasonic EEFVEOK101R
10k EP C3 R5 47 pF
120k 15k
17 10 PF D1 NIEC NSQ03A06
1%
L1 TDK SLF12565T-
220M3R5

Figure 20. Example Circuit 1.5A Max, 305 kHz

8.2.1 Design Requirements

The following parameters are needed to properly design the application and size the components:

PARAMETERS VALUES
Vout Output voltage
Vin min Maximum input voltage
Vin max Minimum input voltage
Iout max Maximum output current
Fsw Switching Frequency
Fbw Bandwidth of the converter

8.2.2 Detailed Design Procedure

8.2.2.1 Setting Output Voltage

The output voltage is set by the ratio of a voltage divider at the FB pin as shown in the typical application. The
resistor values can be determined by the following equation:

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R1
R2 =
§ Vout -1 ·
© Vfb ¹ (9)
Where Vfb = 1.234V typically.
A maximum value of 150kΩ is recommended for the sum of R1 and R2.
As input voltage decreases towards the nominal output voltage, the LM26001 can skip up to seven off-pulses as
described in the Low VIN Operation and UVLO section. In low output voltage applications, if the on-time reaches
TonMIN, the device will skip on-pulses to maintain regulation. There is no limit to the number of pulses that are
skipped. In this mode of operation, however, output ripple voltage may increase slightly.

8.2.2.2 Inductor
The output inductor should be selected based on inductor ripple current. The amount of inductor ripple current
compared to load current, or ripple content, is defined as Iripple/Iload. Ripple content should be less than 40%.
Inductor ripple current, Iripple, can be calculated as shown below:
(Vin ± Vout) x Vout
Iripple =
fsw x L x Vin (10)
Larger ripple content increases losses in the inductor and reduces the effective current limit.
Larger inductance values result in lower output ripple voltage and higher efficiency, but a slightly degraded
transient response. Lower inductance values allow for smaller case size, but the increased ripple lowers the
effective current limit threshold.
Remember that inductor value also affects the sleep mode threshold as shown in Figure 16.
When choosing the inductor, the saturation current rating must be higher than the maximum peak inductor
current and the RMS current rating should be higher than the maximum load current. Peak inductor current,
Ipeak, is calculated as:
Iripple
Ipeak = Iload +
2 (11)
For example, at a maximum load of 1.5A and a ripple content of 40%, peak inductor current is equal to 1.8A
which is safely below the minimum current limit of 1.85A. By increasing the inductor size, ripple content and peak
inductor current are lowered, which increases the current limit margin.
The size of the output inductor can also be determined using the desired output ripple voltage, Vrip. The
equation to determine the minimum inductance value based on Vrip is as follows:
(Vin ± Vout) x Vout x Re
LMIN =
Vin x fsw x Vrip (12)
Where Re is the ESR of the output capacitors, and Vrip is a peak-to-peak value. This equation assumes that the
output capacitors have some amount of ESR. It does not apply to ceramic output capacitors.
If this method is used, ripple content should still be verified to be less than 40%.

8.2.2.3 Output Capacitor

The primary criterion for selecting an output capacitor is equivalent series resistance, or ESR.
ESR (Re) can be selected based on the requirements for output ripple voltage and transient response. Once an
inductor value has been selected, ripple voltage can be calculated for a given Re using the equation above for
Lmin. Lower ESR values result in lower output ripple.
Re can also be calculated from the following equation:
'Vt
ReMAX =
'It (13)

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Where ΔVt is the allowed voltage excursion during a load transient, and ΔIt is the maximum expected load
transient. If the total ESR is too high, the load transient requirement cannot be met, no matter how large the
output capacitance. If the ESR criteria for ripple voltage and transient excursion cannot be met, more capacitors
should be used in parallel. For non-ceramic capacitors, the minimum output capacitance is of secondary
importance, and is determined only by the load transient requirement.
If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed value even if
the maximum ESR requirement is met. The minimum capacitance is calculated as follows:
L x §©'Vt - ('Vt) - ('It x Re)
©
2 2 §
CMIN = 2
Vout x Re (14)
It is assumed the total ESR, Re, is no greater than ReMAX. Also, it is assumed that L has already been selected.
Generally speaking, the output capacitance requirement decreases with Re, ΔIt, and L. A typical value greater
than 100 µF works well for most applications.

8.2.2.4 Input Capacitor

In a switching converter, very fast switching pulse currents are drawn from the input rail. Therefore, input
capacitors are required to reduce noise, EMI, and ripple at the input to the LM26001. Capacitors must be
selected that can handle both the maximum ripple RMS current at highest ambient temperature as well as the
maximum input voltage. The equation for calculating the RMS input ripple current is shown below:
Iload x Vout x (Vin ± Vout)
Irms =
Vin (15)
For noise suppression, a ceramic capacitor in the range of 1.0 µF to 10 µF should be placed as close as possible
to the VIN pin.
A larger, high ESR input capacitor should also be used. This capacitor is recommended for damping input
voltage spikes during power-on and for holding up the input voltage during transients. In low input voltage
applications, line transients may fall below the UVLO threshold if there is not enough input capacitance. Both
tantalum and electrolytic type capacitors are suitable for the bulk capacitor. However, large tantalums may not be
available for high input voltages and their working voltage must be derated by at least 2X.

8.2.2.5 Bootstrap
The drive voltage for the internal switch is supplied via the BOOT pin. This pin must be connected to a ceramic
capacitor, Cboot, from the switch node, shown as C4 in the typical application. The LM26001 provides the VDD
voltage internally, so no external diode is needed. A maximum value of 0.1 uF is recommended for Cboot.
Values smaller than 0.01 uF may result in insufficient hold up time for the drive voltage and increased power
dissipation.
During low Vin operation, when the on-time is extended, the bootstrap capacitor is at risk of discharging. If the
Cboot capacitor is discharged below approximately 2.5V, the LM26001 enters a high frequency re-charge mode.
The Cboot cap is re-charged via the LG synchronous FET shown in the block diagram. Switching returns to
normal when the Cboot cap has been recharged.

8.2.2.6 Catch Diode

When the internal switch is off, output current flows through the catch diode. Alternately, when the switch is on,
the diode sees a reverse voltage equal to Vin. Therefore, the important parameters for selecting the catch diode
are peak current and peak inverse voltage. The average current through the diode is given by:
IDAVE = Iload x (1-D) (16)
Where D is the duty cycle, defined as Vout/Vin. The catch diode conducts the largest currents during the lowest
duty cycle. Therefore IDAVE should be calculated assuming maximum input voltage. The diode should be rated to
handle this current continuously. For over-current or short circuit conditions, the catch diode should be rated to
handle peak currents equal to the peak current limit.
The peak inverse voltage rating of the diode must be greater than maximum input voltage.

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A Schottky diode must be used. It's low forward voltage maximizes efficiency and BOOT voltage, while also
protecting the SW pin against large negative voltage spikes.

8.2.2.7 Compensation
The purpose of loop compensation is to ensure stable operation while maximizing dynamic performance. Stability
can be analyzed with loop gain measurements, while dynamic performance is analyzed with both loop gain and
load transient response. Loop gain is equal to the product of control-output transfer function (power stage) and
the feedback transfer function (the compensation network).
For stability purposes, our target is to have a loop gain slope that is -20dB /decade from a very low frequency to
beyond the crossover frequency. Also, the crossover frequency should not exceed one-fifth of the switching
frequency, i.e. 60 kHz in the case of 300 kHz switching frequency.
For dynamic purposes, the higher the bandwidth, the faster the load transient response. A large DC gain means
high DC regulation accuracy (i.e. DC voltage changes little with load or line variations). To achieve this loop gain,
the compensation components should be set according to the shape of the control-output bode plot. A typical
plot is shown in Figure 21.
fp fz fn
20 0

0 -45

PHASE (º)
GAIN (dB)

-20 -90

-40 -135

-60 -180
0.01 0.1 1 10 100 1000

FREQUENCY (kHz)

Figure 21. Control-Output Transfer Function

The control-output transfer function consists of one pole (fp), one zero (fz), and a double pole at fn (half the
switching frequency).
Referring to Figure 21, the following should be done to create a -20dB /decade roll-off of the loop gain:
1. Place a pole at 0 Hz (fpc)
2. Place a zero at fp (fzc)
3. Place a second pole at fz (fpc1)
The resulting feedback (compensation) bode plot is shown in Figure 22. Adding the control-output response to
the feedback response will then result in a nearly continuous –20db/decade slope.

-2
0dB
/de
c
GAIN (dB)

0dB/dec
-2
0dB
/ dec
B

fpc fzc fpc1

(0Hz)
FREQUENCY

Figure 22. Feedback Transfer Function

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The control-output corner frequencies can be determined approximately by the following equations:
1
fz =
2S x Re x Co (17)
1 0.5
fp = +
10 x S x Ro x Co 2 x S x L x fsw x Co (18)
fsw
fn =
2 (19)
Where Co is the output capacitance, Ro is the load resistance, Re is the output capacitor ESR, and fsw is the
switching frequency. The effects of slope compensation and current sense gain are included in this equation.
However, the equation is an approximation intended to simplify loop compensation calculations. To derive the
exact transfer function, use 0.2V/V sense amp gain and 36mVp-p slope compensation.
Since fp is determined by the output network, it shifts with loading. Determine the range of frequencies
(fpmin/max) across the expected load range. Then determine the compensation values as described below and
shown in Figure 23.

5
SS
6
COMP

7 FB
C8
C9

R5 R2 R1 C10

To Vout

Figure 23. Compensation Network

1. The compensation network automatically introduces a low frequency pole (fpc), which is close to 0Hz.
2. Once the fp range is determined, R5 should be calculated using:
B § R1 + R2 ·
R5 = x
gm © R2 ¹ (20)
Where B is the desired feedback gain in v/v between fp and fz, and gm is the transconductance of the error
amplifier. A gain value around 10dB (3.3v/v) is generally a good starting point. Bandwidth increases with
increasing values of R5.
3. Next, place a zero (fzc) near fp using C8. C8 can be determined with the following equation:
1
C8 =
2 x S x fPMAX x R5 (21)
The selected value of C8 should place fzc within a decade above or below fpmax, and not less than fpmin. A
higher C8 value (closer to fpmin) generally provides a more stable loop, but too high a value will slow the
transient response time. Conversely, a smaller C8 value will result in a faster transient response, but lower phase
margin.
4. A second pole (fpc1) can also be placed at fz. This pole can be created with a single capacitor, C9. The
minimum value for this capacitor can be calculated by:
1
C9 =
2 x S x fz x R5 (22)
C9 may not be necessary in all applications. However if the operating frequency is being synchronized below the
nominal frequency, C9 is recommended. Although it is not required for stability, C9 is very helpful in suppressing
noise.

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A phase lead capacitor can also be added to increase the phase and gain margins. The phase lead capacitor is
most helpful for high input voltage applications or when synchronizing to a frequency greater than nominal. This
capacitor, shown as C10 in Figure 23, should be placed in parallel with the top feedback resistor, R1. C10
introduces an additional zero and pole to the compensation network. These frequencies can be calculated as
shown below:
1
fzff =
2 x S x R1 x C10 (23)
fzff x Vout
fpff =
Vfb (24)
A phase lead capacitor will boost loop phase around the region of the zero frequency, fzff. fzff should be placed
somewhat below the fpz1 frequency set by C9. However, if C10 is too large, it will have no effect.

8.2.3 Application Curves

Vout
Vout
1V/Div
40 mV/Div

PGOOD
5V/Div
Iout
500 mA/Div

SS
1V/Div

EN
10V/Div

1 Ps/DIV 200 Ps/DIV

Figure 24. Startup Waveforms Figure 25. Load Transient Response

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9 Power Supply Recommendations

The LM26001 is designed to operate from various DC power supply including a car battery. If so, VIN input
should be protected from reversal voltage and voltage dump over 48 Volts. The impedance of the input supply
rail should be low enough that the input current transient does not cause drop below VIN UVLO level. If the input
supply is connected by using long wires, additional bulk capacitance may be required in addition to normal input
capacitor.

10 Layout

10.1 Layout Guidelines

Good board layout is critical for switching regulators such as the LM26001. First, the ground plane area must be
sufficient for thermal dissipation purposes, and second, appropriate guidelines must be followed to reduce the
effects of switching noise.
Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current
combined with parasitic trace inductance generates unwanted Ldi/dt noise spikes at the SW node and also at the
VIN node. The magnitude of this noise tends to increase as the output current increases. This parasitic spike
noise may turn into electromagnetic interference (EMI), and can also cause problems in device performance.
Therefore, care must be taken in layout to minimize the effect of this switching noise.
The current sensing circuit in current mode devices can be easily affected by switching noise. This noise can
cause duty cycle jitter which leads to increased spectral noise. Although the LM26001 has 100ns blanking time at
the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. Following the
important guidelines below will help minimize switching noise and its effect on current sensing.
The switch node area should be as small as possible. The catch diode, input capacitors, and output capacitors
should be grounded to a large ground plane, with the bulk input capacitor grounded as close as possible to the
catch diode anode. Additionally, the ground area between the catch diode and bulk input capacitor is very noisy
and should be somewhat isolated from the rest of the ground plane.
A ceramic input capacitor must be connected as close as possible to the VIN pin and grounded close to the GND
pin. Often this capacitor is most easily located on the bottom side of the pcb. If placement close to the GND pin
is not practical, the ceramic input capacitor can also be grounded close to the catch diode ground. The above
layout recommendations are illustrated below in Figure 26.
It is a good practice to connect the EP, GND pin, and small signal components (COMP, FB, FREQ) to a separate
ground plane, shown in Figure 26 as EP GND, and in the schematics as a signal ground symbol. Both the
exposed pad and the GND pin must be connected to ground. This quieter plane should be connected to the high
current ground plane at a quiet location, preferably near the Vout ground as shown by the dashed line in
Figure 26.
The EP GND plane should be made as large as possible, since it is also used for thermal dissipation. Several
vias can be placed directly below the EP to increase heat flow to other layers when they are available. The
recommended via hole diameter is 0.3mm.
The trace from the FB pin to the resistor divider should be short and the entire feedback trace must be kept away
from the inductor and switch node. See AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines, SNVA054, for
more information regarding PCB layout for switching regulators.

Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: LM26001 LM26001-Q1
LM26001, LM26001-Q1
SNVS430I – MAY 2006 – REVISED MARCH 2015 www.ti.com

10.2 Layout Example

Vin GND Vout

+
SW

EP
GND

Figure 26. Example PCB Layout

10.3 Thermal Considerations and TSD

Although the LM26001 has a built in current limit, at ambient temperatures above 80°C, device temperature rise
may limit the actual maximum load current. Therefore, temperature rise must be taken into consideration to
determine the maximum allowable load current.
Temperature rise is a function of the power dissipation within the device. The following equations can be used to
calculate power dissipation (PD) and temperature rise, where total PD is the sum of FET switching losses, FET
DC losses, drive losses, Iq, and VBIAS losses:
PDTOTAL = PswAC + PswDC + PQG + PIq + PVBIAS (25)
§ Vin x 10 ·
-9
PswAC = Vin x Iload x fsw x
© 1.33 ¹ (26)
PswDC = D x Iload2 x (0.2 + 0.00065 x (Tj - 25)) (27)
PQG = Vin x 4.6 x 10-9 x fsw (28)
PIq = Vin x Iq (29)
PVBIAS = Vbias x IVBIAS (30)
Given this total power dissipation, junction temperature can be calculated as follows:
Tj = Ta + (PDTOTAL x θJA) (31)
Where θJA=38°C/W (typically) when using a multi-layer board with a large copper plane area. θJA varies with
board type and metallization area.
To calculate the maximum allowable power dissipation, assume Tj = 125°C. To ensure that junction temperature
does not exceed the maximum operating rating of 125°C, power dissipation should be verified at the maximum
expected operating frequency, maximum ambient temperature, and minimum and maximum input voltage. The
calculated maximum load current is based on continuous operation and may be exceeded during transient
conditions.
If the power dissipation remains above the maximum allowable level, device temperature will continue to rise.
When the junction temperature exceeds its maximum, the LM26001 engages Thermal Shut Down (TSD). In
TSD, the part remains in a shutdown state until the junction temperature falls to within normal operating limits. At
this point, the device restarts in soft-start mode.

24 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated

Product Folder Links: LM26001 LM26001-Q1

 LM26001, LM26001-Q1
www.ti.com SNVS430I – MAY 2006 – REVISED MARCH 2015

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines, SNVA054
IC Package Thermal Metrics application report, SPRA953

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
LM26001 Click here Click here Click here Click here Click here
LM26001-Q1 Click here Click here Click here Click here Click here

11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: LM26001 LM26001-Q1
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Feb-2015

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

LM26001MXA/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 L26001
& no Sb/Br) MXA
LM26001MXAX/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 L26001
& no Sb/Br) MXA
LM26001QMXA/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 L26001
& no Sb/Br) QMXA
LM26001QMXAX/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 L26001
& no Sb/Br) QMXA

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Feb-2015

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM26001, LM26001-Q1 :

• Catalog: LM26001
• Automotive: LM26001-Q1

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM26001MXAX/NOPB HTSSOP PWP 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
LM26001QMXAX/NOPB HTSSOP PWP 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM26001MXAX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0
LM26001QMXAX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA
PWP0016A

MXA16A (Rev A)

www.ti.com
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