LV14360

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LV14360 60-V, 3-A Step-Down Converter With High Light Load Efficiency

1 Features 3 Description
• 4.3-V to 60-V input range The LV14360 is a 60-V, 3-A step-down regulator with
• 3-A continuous output current an integrated high-side MOSFET. With a wide input
• 300-µA operating quiescent current range from 4.3 V to 60 V, the device is suitable
• 155-mΩ high-side MOSFET for various applications from industrial to automotive
• Current mode control for power conditioning from unregulated sources.
• Adjustable switching frequency from 200 kHz to 2 The quiescent current of the regulator is 300 µA in
MHz sleep mode, which is suitable for battery-powered
• Frequency synchronization to external clock systems. An ultra-low 1-μA current in shutdown mode
• Internal compensation for ease of use can further prolong battery life. A wide adjustable
• High duty cycle operation supported switching frequency range allows either efficiency or
• Precision enable input external component size to be optimized. Internal
• 1-µA shutdown current loop compensation means that the user is free
• Thermal, overvoltage, and short protection from the tedious task of loop compensation design.
• 8-pin HSOIC with PowerPAD™ package This also minimizes the external components of the
device. A precision enable input allows simplification
2 Applications of regulator control and system power sequencing.
• Industrial power supplies The device also has built-in protection features such
• Communications equipment and datacom modules as cycle-by-cycle current limit, thermal sensing and
• General purpose wide VIN regulation shutdown due to excessive power dissipation, and
output overvoltage protection.
The LV14360 is available in an 8-pin, 4.89-mm ×
3.9-mm HSOIC package with exposed pad for low
thermal resistance.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
LV14360 HSOIC 4.89-mm × 3.9-mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
VIN up to 60 V 100
90
CIN
VIN 80
EN BOOT
70
CBOOT
Efficiency (%)

L
VOUT 60
RT/SYNC SW
50
RT D RFBT
40
COUT
30
SS FB RFBB
CSS 20 VIN = 12 V
GND VIN = 24 V
10
VIN = 48 V
0
0.0001 0.001 0.01 0.05 0.2 0.5 1 2 3
Simplified Schematic For Soft-Start (SS) Option IOUT (A) D012

Efficiency vs Output Current VOUT = 5 V,

ƒsw = 500 kHz

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.3 Feature Description...................................................10
2 Applications..................................................................... 1 8.4 Device Functional Modes..........................................16
3 Description.......................................................................1 9 Application and Implementation.................................. 17
4 Revision History.............................................................. 2 9.1 Application Information............................................. 17
5 Device Comparison Table...............................................2 9.2 Typical Application.................................................... 17
6 Pin Configuration and Functions...................................3 10 Power Supply Recommendations..............................23
Pin Functions.................................................................... 3 11 Layout........................................................................... 23
7 Specifications.................................................................. 4 11.1 Layout Guidelines................................................... 23
7.1 Absolute Maximum Ratings........................................ 4 11.2 Layout Example...................................................... 24
7.2 ESD Ratings............................................................... 4 12 Device and Documentation Support..........................25
7.3 Recommended Operating Conditions.........................4 12.1 Receiving Notification of Documentation Updates..25
7.4 Thermal Information....................................................5 12.2 Support Resources................................................. 25
7.5 Electrical Characteristics.............................................5 12.3 Trademarks............................................................. 25
7.6 Switching Characteristics............................................6 12.4 Glossary..................................................................25
7.7 Typical Characteristics................................................ 7 12.5 Electrostatic Discharge Caution..............................25
8 Detailed Description........................................................9 13 Mechanical, Packaging, and Orderable
8.1 Overview..................................................................... 9 Information.................................................................... 25
8.2 Functional Block Diagram......................................... 10

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (August 2017) to Revision A (September 2020) Page
• First public release..............................................................................................................................................1
• Updated the numbering format for tables, figures and cross-references throughout the document...................1

5 Device Comparison Table

PART NUMBER FEATURE
LV14360P Power Good
LV14360S Soft start

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6 Pin Configuration and Functions

BOOT 1 8 SW

VIN 2 7 GND
Thermal Pad
(9)
EN 3 6 SS or PGOOD

RT/SYNC 4 5 FB

Figure 6-1. DDA Package 8-Pin HSOIC Top View

Pin Functions
PIN
TYPE (1) DESCRIPTION
NO. NAME
Bootstrap capacitor connection for high-side MOSFET driver. Connect a high quality 0.1-μF
1 BOOT P
capacitor from BOOT to SW.
Connect to power supply and bypass capacitors CIN. Path from VIN pin to high frequency
2 VIN P
bypass CIN and GND must be as short as possible.
Enable pin with internal pullup current source. Pull below 1.2 V to disable. Float or connect to
3 EN A
VIN to enable. Adjust the input undervoltage lockout with two resistors (see Section 8.3.6).
Resistor timing or external clock input. An internal amplifier holds this pin at a fixed voltage
when using an external resistor to ground to set the switching frequency. If the pin is
pulled above the PLL upper threshold, a mode change occurs and the pin becomes a
4 RT/SYNC A
synchronization input. The internal amplifier is disabled and the pin is a high impedance clock
input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled, and the
operating mode returns to frequency programming by resistor.
Feedback input pin, connect to the feedback divider to set VOUT. Do not short this pin to
5 FB A
ground during operation.
SS SS pin for soft-start version, connect to a capacitor to set soft-start time.
6 or A The PGOOD pin for power-good version, open-drain output for power-good flag, use a 10-kΩ
PGOOD to 100-kΩ pullup resistor to logic rail or other DC voltage no higher than 7 V.
7 GND G System ground pin
Switching output of the regulator. Internally connected to high-side power MOSFET. Connect
8 SW P
to power inductor.
9 Thermal Pad G Major heat dissipation path of the die. Must be connected to ground plane on PCB.

(1) A = Analog, P = Power, G = Ground

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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)(1)
MIN MAX UNIT
VIN, EN to GND –0.3 65
BOOT to GND –0.3 71
SS to GND –0.3 5
Input voltages V
FB to GND –0.3 7
RT/SYNC to GND –0.3 3.6
PGOOD to GND –0.3 7
BOOT to SW 6.5
Output voltages V
SW to GND –3 65
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM)(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM) (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)(1)
MIN MAX UNIT
VIN 4.3 60
VOUT 0.8 50
Buck regulator BOOT 66 V
SW –1 60
FB 0 5
EN 0 60
RT/SYNC 0 3.3
Control V
SS 0 3
PGOOD to GND 0 5
Switching frequency range at RT mode 200 2000
Frequency kHz
Switching frequency range at SYNC mode 250 2000
Temperature Operating junction temperature, TJ –40 125 °C

(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits.
For ensured specifications, see Section 7.5.

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7.4 Thermal Information

LV14360
THERMAL METRIC (1) (2) DDA (HSOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 42.5 °C/W
ψJT Junction-to-top characterization parameter 9.9 °C/W
ψJB Junction-to-board characterization parameter 25.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.8 °C/W
RθJB Junction-to-board thermal resistance 25.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Power rating at a specific ambient temperature TA should be determined with a maximum junction temperature (TJ) of 125°C (see
Section 7.3).

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following
conditions apply: VIN = 4.3 V to 60 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY (VIN PIN)
VIN Operation input voltage 4.3 60 V
Under voltage lockout thresholds Rising threshold 3.8 4 4.2 V
UVLO
Hysteresis 285 mV
ISHDN Shutdown supply current VEN = 0 V, TA = 25°C, 4.3 V ≤ VIN ≤ 60 V 1 3 μA
Operating quiescent current VFB = 1 V, TA = 25°C
IQ 300 μA
(non- switching)
ENABLE (EN PIN)
VEN_TH EN Threshold Voltage 1.05 1.20 1.38 V
EN PIN current Enable threshold 50 mV –4.6
IEN_PIN μA
Enable threshold –50 mV –1
IEN_HYS EN hysteresis current –3.6 μA
SOFT START
SS pin current For external soft-start version only, TA = μA
ISS –3
25°C
Internal soft-start time For power-good version only, 10% to 90% ms
tSS 4
of FB voltage
POWER GOOD (PGOOD PIN)
Power-good flag under voltage POWER GOOD (% of FB voltage) 94%
VPG_UV tripping threshold
POWER BAD (% of FB voltage) 92%
Power-good flag over voltage POWER BAD (% of FB voltage) 109%
VPG_OV tripping threshold
POWER GOOD (% of FB voltage) 107%
Power-good flag recovery % of FB voltage
VPG_HYS 2%
hysteresis
PGOOD leakage current at high VPULLUP = 5 V nA
IPG 10 200
level output
VPG_LOW PGOOD low level output voltage IPULLUP = 1 mA 0.1 V
Minimum VIN for valid PGOOD VPULLUP < 5 V at IPULLUP = 100 μA V
VIN_PG_MIN 1.6 1.95
output

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Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following
conditions apply: VIN = 4.3 V to 60 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE REFERENCE (FB PIN)
Feedback voltage TJ = 25°C 0.746 0.75 0.754 V
VFB
TJ = –40°C to 125°C 0.735 0.75 0.765 V
HIGH-SIDE MOSFET
RDS_ON On-resistance VIN = 12 V, BOOT to SW = 5.8 V 155 320 mΩ
HIGH-SIDE MOSFET CURRENT LIMIT
ILIMT Current limit VIN = 12 V, TA = 25°C, Open Loop 3.8 4.75 5.7 A
THERMAL PERFORMANCE
TSHDN Thermal shutdown threshold 170
°C
THYS Hysteresis 12

7.6 Switching Characteristics

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Switching frequency RT = 11.5 kΩ 1912
ƒSW Switching frequency range at kHz
250 2000
SYNC mode
VSYNC_HI SYNC clock high level threshold 1.7
V
VSYNC_LO SYNC clock low level threshold 0.5
Measured at 500 kHz, VSYNC_HI > 3 V,
TSYNC_MIN Minimum SYNC input pulse width 30 ns
VSYNC_LO < 0.3 V
TLOCK_IN PLL lock in time Measured at 500 kHz 100 µs
TON_MIN Minimum controllable on time VIN = 12 V, BOOT to SW = 5.8 V, ILoad = 1 A 100 ns
DMAX Maximum duty cycle fSW = 200 kHz 90%

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7.7 Typical Characteristics

Unless otherwise specified the following conditions apply: VIN = 24 V, fSW = 500 KHz, L = 8.2 µH, COUT = 2 × 47
µF, TA = 25°C.

100 100

90 90

80 80
Efficiency (%)

Efficiency (%)
70 70

60 60

50 50

VIN = 12 V VIN = 36 V
40 VIN = 18 V 40 VIN = 48 V
VIN = 24 V VIN = 60 V
30 30
0.001 0.01 0.1 1 3 0.001 0.01 0.1 1 3
IOUT (A) D001
IOUT (A) D002

VOUT = 3.3 V ƒSW = 500 KHz VOUT = 3.3 V ƒSW = 500 KHz

Figure 7-1. Efficiency vs Load Current Figure 7-2. Efficiency vs Load Current
100 100

90 90

80 80
Efficiency (%)

Efficiency (%)

70 70

60 60

50 50

VIN = 12 V VIN = 36 V
40 VIN = 18 V 40 VIN = 48 V
VIN = 24 V VIN = 60 V
30 30
0.001 0.01 0.1 1 3 0.001 0.01 0.1 1 3
IOUT (A) D003
IOUT (A) D004

VOUT = 5 V ƒSW = 500 KHz VOUT = 5 V ƒSW = 500 KHz

Figure 7-3. Efficiency vs Load Current Figure 7-4. Efficiency vs Load Current
0.2 125
VFB Falling
0.15 VFB Rising
Nominal Switching Frequency (%)

100
0.1
VOUT Deviation (%)

0.05 75
0
50
-0.05

-0.1 VIN = 12 V
VIN = 24 V 25
-0.15 VIN = 36 V
VIN = 48 V
-0.2 0
0.001 0.01 0.1 1 3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
IOUT (A) VFB (V) D005
D005

VOUT = 5 V ƒSW = 500 KHz

Figure 7-5. Load Regulation Figure 7-6. Frequency vs VFB

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5.5 0.754

5 0.752

4.5 0.75
VOUT (V)

VFB (V)
4 0.748
3A
2A
3.5 1A 0.746
0.5 A
0.1 A
3 0.744
4.5 5 5.5 6 6.5 -50 -25 0 25 50 75 100 125 150
VIN (V) D007
Junction Temperature (qC) D010

VOUT = 5 V ƒSW = 500 KHz VIN = 12 V

Figure 7-7. Dropout Curve Figure 7-8. Voltage Reference vs Junction

Temperature
6 4
VIN = 12 V
5.8 VIN = 60 V 3.95
5.6
3.9
5.4
3.85 UVLO_H
Current (A)

5.2
UVLO (V) UVLO_L
5 3.8
4.8 3.75
4.6
3.7
4.4
4.2 3.65

4 3.6
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) D011
Junction Temperature (qC) D009

IOUT = 0 A

Figure 7-9. High-Side Current Limit vs Junction Figure 7-10. UVLO Threshold
Temperature

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8 Detailed Description
8.1 Overview
The LV14360 regulator is an easy-to-use step-down DC-DC converter that operates from a 4.3-V to 60-V supply
voltage. The device integrates a 155-mΩ (typical) high-side MOSFET and is capable of delivering up to 3-A DC
load current with exceptional efficiency and thermal performance in a very small solution size. The operating
current is typically 300 μA under no load condition (not switching). When the device is disabled, the supply
current is typically 1 μA. An extended family is available in 1-A and 2-A load options in pin-to-pin compatible
packages.
The LV14360 implements constant frequency peak current mode control with sleep mode at light load to achieve
high efficiency. The device is internally compensated, which reduces design time, and requires fewer external
components. The switching frequency is programmable from 200 kHz to 2 MHz by an external resistor RT. The
LV14360 is also capable of synchronization to an external clock within the 250-kHz to 2 MHz frequency range,
which allows the device to be optimized to fit small board space at higher frequency, or high efficient power
conversion at lower frequency.
Other features are included for more comprehensive system requirements, including precision enable,
adjustable soft-start time, and approximate 90% duty cycle by BOOT capacitor recharge circuit. These features
provide a flexible and easy-to-use platform for a wide range of applications. Protection features include over
temperature shutdown, VOUT overvoltage protection (OVP), VIN undervoltage lockout (UVLO), cycle-by-cycle
current limit, and short-circuit protection with frequency foldback.

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8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Fixed Frequency Peak Current Mode Control
The following operating description of the LV14360 refers to Section 8.2 and to the waveforms in Figure 8-1.
The LV14360 output voltage is regulated by turning on the high-side N-MOSFET with controlled ON time. During
high-side switch ON time, the SW pin voltage swings up to approximately VIN, and the inductor current iL
increases with linear slope (V IN – VOUT) / L. When the high-side switch is off, inductor current discharges through
a freewheel diode with a slope of –VOUT / L. The control parameter of buck converter is defined as Duty Cycle
D = tON / TSW, where tON is the high-side switch ON-time and TSW is the switching period. The regulator control
loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal Buck converter, where losses
are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT /
VIN.

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VSW
D = tON/ TSW
VIN

SW Voltage
tON tOFF
t
0
-VD
TSW
iL

ILPK

Inductor Current
IOUT
ûiL

t
0

Figure 8-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The LV14360 employs fixed frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current to control the ON time
of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency at normal load condition. At very light load, the
LV14360 operates in sleep mode to maintain high efficiency and switching frequency will decrease with reduced
load current.
8.3.2 Slope Compensation
The LV14360 adds a compensating ramp to the MOSFET switch current sense signal. This slope compensation
prevents subharmonic oscillations at duty cycles greater than 50%. The peak current limit of the high-side switch
is not affected by the slope compensation and remains constant over the full duty cycle range.
8.3.3 Sleep Mode
The LV14360 operates in sleep mode at light load currents to improve efficiency by reducing switching and
gate-drive losses. If the output voltage is within regulation and the peak switch current at the end of any
switching cycle is below the current threshold of 300 mA, the device enters sleep mode. The sleep-mode current
threshold is the peak switch current level corresponding to a nominal internal COMP voltage of 400 mV.
When in sleep mode, the internal COMP voltage is clamped at 400 mV and the high-side MOSFET is inhibited,
and the device draws only 300 μA (typical) input quiescent current. Since the device is not switching, the output
voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the internal
COMP voltage. The high-side MOSFET is enabled and switching resumes when the error amplifier lifts internal
COMP voltage above 400 mV. The output voltage recovers to the regulated value, and internal COMP voltage
eventually falls below the sleep-mode threshold at which time the device again enters sleep mode.
8.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The LV14360 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when
the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating
of 16 V or greater for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the LV14360
operates at approximate 90% duty cycle. When the high-side MOSFET is continuously on for five or six
switching cycles (five or six switching cycles for frequency lower than 1 MHz, and 10 or 11 switching cycles
for frequency higher than 1 MHz) and the voltage from BOOT to SW drops below 3.2 V, the high-side MOSFET
is turned off and an integrated low-side MOSFET pulls SW low to recharge the BOOT capacitor.

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Since the gate drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 90%. The effective duty cycle of the converter during dropout
is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-side diode
voltage, and the printed circuit board resistance.
8.3.5 Adjustable Output Voltage
The internal voltage reference produces a precise 0.75 V (typical) voltage reference over the operating
temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. It is
recommended to use 1% tolerance or better and temperature coefficient of 100 ppm or less divider resistors.
Select the low side resistor RFBB for the desired divider current and use Equation 1 to calculate high-side RFBT.
Larger value divider resistors are good for efficiency at light load. However, if the values are too high, the
regulator will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
RFBB in the range from 10 kΩ to 100 kΩ is recommended for most applications.
VOUT

RFBT

FB

RFBB

Figure 8-2. Output Voltage Setting

VOUT 0.75
RFBT u RFBB
0.75 (1)

8.3.6 Enable and Adjustable Undervoltage Lockout

The LV14360 is enabled when the VIN pin voltage rises above 4 V (typical) and the EN pin voltage exceeds
the enable threshold of 1.2 V (typical). The LV14360 is disabled when the VIN pin voltage falls below 3.715 V
(typical) or when the EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source (typically
IEN = 1 μA) that enables operation of the LV14360 when the EN pin is floating.
Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 8-3 to establish
a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power
as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such
as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.
When EN terminal voltage exceeds 1.2 V, an additional hysteresis current (typically IHYS = 3.6 μA) is sourced
out of EN terminal. When the EN terminal is pulled below 1.2 V, IHYS current is removed. This additional current
facilitates adjustable input voltage UVLO hysteresis. Use Equation 2 and Equation 3 to calculate RENT and RENB
for desired UVLO hysteresis voltage.

IEN_HYS IEN
VIN
VIN

RENT

EN
VEN RENB

Figure 8-3. System UVLO By Enable Dividers

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VSTART VSTOP
RENT
IHYS (2)

VEN
RENB
VSTART VEN
IEN
RENT (3)

where
• VSTART is the desired voltage threshold to enable LV14360
• VSTOP is the desired voltage threshold to disable device
• IEN = 1 μA
• IHYS = 3.6 μA, typically
8.3.7 External Soft Start
The LV14360S has an external soft-start pin for programmable output ramp up time. The soft-start feature is
used to prevent inrush current impacting the LV14360 and its load when power is first applied. The soft-start
time can be programed by connecting an external capacitor CSS from SS pin to GND. An internal current source
(typically I SS = 3 μA) charges CSS and generates a ramp from 0 V to VREF. The soft-start time can be calculated
by Equation 4:

CSS (nF) u VREF (V)

tSS (ms)
ISS (PA) (4)

The internal soft start resets while device is disabled or in thermal shutdown.
8.3.8 Switching Frequency and Synchronization (RT/SYNC)
The switching frequency of the LV14360 can be programmed by the resistor RT from the RT/SYNC pin and GND
pin. The RT/SYNC pin cannot be left floating or shorted to ground. To determine the timing resistance for a given
switching frequency, use Equation 5 or the curve in Figure 8-4. Table 8-1 gives typical RT values for a given ƒSW.

1.088
RT (k:) 42904 u ¦SW N+] (5)
140

120

100

80
RT (k:)

60

40

20

0
0 500 1000 1500 2000
Frequency (kHz) D008

Figure 8-4. RT vs Frequency Curve

Table 8-1. Typical Frequency Setting RT Resistance

ƒSW (kHz) RT (kΩ)
200 133
350 73.2
500 49.9

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Table 8-1. Typical Frequency Setting RT Resistance (continued)

ƒSW (kHz) RT (kΩ)
750 32.4
1000 23.2
1500 15.0
1912 11.5
2000 11

The LV14360 switching action can also be synchronized to an external clock from 250 kHz to 2 MHz. Connect
a square wave to the RT/SYNC pin through either circuit network shown in Figure 8-5. Internal oscillator is
synchronized by the falling edge of external clock. The recommendations for the external clock include: high
level no lower than 1.7 V, low level no higher than 0.5 V, and have a pulse width greater than 30 ns. When using
a low impedance signal source, the frequency setting resistor RT is connected in parallel with an AC coupling
capacitor CCOUP to a termination resistor RTERM (for example, 50 Ω). The two resistors in series provide the
default frequency setting resistance when the signal source is turned off. A 10-pF ceramic capacitor can be used
for CCOUP. Figure 8-6, Figure 8-7, and Figure 8-8 show the device synchronized to an external system clock.
CCOUP

PLL PLL
RT
Lo-Z RT/SYNC Hi-Z RT/SYNC
Clock Clock
Source RTERM Source RT

Figure 8-5. Synchronizing to an External Clock

Figure 8-6. Synchronizing in CCM Figure 8-7. Synchronizing in DCM

Figure 8-8. Synchronizing in Sleep Mode

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Equation 6 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.

1 § IOUT u RIND VOUT VD ·

¦SW(max) u¨ ¸
tON ¨© VIN_MAX IOUT u RDS_ON VD ¸¹
(6)

where
• IOUT = Output current
• RIND = Inductor series resistance
• VIN_MAX = Maximum input voltage
• VOUT = Output voltage
• VD = Diode voltage drop
• RDS_ON = High-side MOSFET switch on resistance
• tON = Minimum on-time
8.3.9 Power Good (PGOOD)
The LV14360P has a built-in power-good flag shown on the PGOOD pin to indicate whether the output voltage
is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault
protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage.
Voltage seen by the PGOOD pin must never exceed 7 V. A resistor divider pair can be used to divide the voltage
down from a higher potential. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.
Refer to Figure 8-9. When the FB voltage is within the power-good band, +7% above and –6% below the internal
reference VREF typically, the PGOOD switch is turned off, and the PGOOD voltage is pulled up to the voltage
level defined by the pullup resistor or divider. When the FB voltage is outside of the tolerance band, +9% above
or –8% below VREF typically, the PGOOD switch is turned on, and the PGOOD pin voltage is pulled low to
indicate power bad.

VREF
109%
107%

94%
92%

PGOOD

High

Low

Figure 8-9. Power-Good Flag

8.3.10 Overcurrent and Short-Circuit Protection

The LV14360 is protected from overcurrent condition by cycle-by-cycle current limiting on the peak current of the
high-side MOSFET. High-side MOSFET overcurrent protection is implemented by the nature of the peak current
mode control. The high-side switch current is compared to the output of the error amplifier (EA) minus slope
compensation every switching cycle. See Section 8.2 for more details. The peak current of the high-side switch
is limited by a clamped maximum peak current threshold which is constant. Thus, the peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
The LV14360 also implements a frequency foldback to protect the converter in severe overcurrent or short
conditions. The oscillator frequency is divided by two, four, and eight as the FB pin voltage decrease to 75%,
50%, 25% of VREF. The frequency foldback increases the off-time by increasing the period of the switching cycle,
so that it provides more time for the inductor current to ramp down and leads to a lower average inductor current.

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Lower frequency also means lower switching loss. Frequency foldback reduces power dissipation and prevents
overheating and potential damage to the device.
8.3.11 Overvoltage Protection
The LV14360 employs an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance.
The OVP feature minimizes output overshoot by turning off the high-side switch immediately when FB voltage
reaches to the rising OVP threshold, which is nominally 109% of the internal voltage reference VREF. When the
FB voltage drops below the falling OVP threshold which is nominally 107% of VREF, the high-side MOSFET
resumes normal operation.
8.3.12 Thermal Shutdown
The LV14360 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170°C (typical). The high-side MOSFET stops switching when thermal shutdown activates. Once the
die temperature falls below 158°C (typical), the device reinitiates the power-up sequence controlled by the
internal soft-start circuitry.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LV14360. When VEN is below 1 V, the device is in
shutdown mode. The switching regulator is turned off and the quiescent current drops to 1 µA, typically. The
LV14360 also employs UVLO protection. If VIN voltage is below the UVLO level, the regulator is turned off.
8.4.2 Active Mode
The LV14360 is in active mode when VEN is above the precision enable threshold and VIN is above its UVLO
level. The simplest way to enable the LV14360 is to connect the EN pin to VIN pin. This allows self start-up when
the input voltage is in the operation range: 4.3 V to 60 V. See Section 8.3.6 for details on setting these operating
levels.
In active mode, depending on the load current, the LV14360 is in one of three modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation
3. Sleep-mode when internal COMP voltage drop to 400 mV at very light load
8.4.3 CCM Mode
CCM operation is employed in the LV14360 when the load current is higher than half of the peak-to-peak
inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple will be at a minimum
in this mode and the maximum output current of 3 A can be supplied by the LV14360.
8.4.4 Light Load Operation
When the load current is lower than half of the peak-to-peak inductor current in CCM, the LV14360 operates in
DCM. At even lighter current loads, sleep mode is activated to maintain high efficiency operation by reducing
switching and gate-drive losses.

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

The LV14360 is a step-down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 3 A. The following design procedure can be used to select
components for the LV14360. This section presents a simplified discussion of the design process.
9.2 Typical Application
The LV14360 only requires a few external components to convert from wide voltage range supply to a fixed
output voltage. A schematic of 5-V / 3-A application circuit is shown in Figure 9-1. The external components
have to fulfill the needs of the application, but also the stability criteria of the device control loop.
7 V to 60 V
CBOOT
CIN VIN BOOT

L 5V/3A
EN SW
COUT
D
RFBT

RT/SYNC FB

RFBB
RT SS GND

CSS

Figure 9-1. Application Circuit, 5-V Output

9.2.1 Design Requirements

This example details the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These parameters are typically determined at
the system level:
Table 9-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage, VIN 7 V to 60 V, typical 24 V
Output voltage, VOUT 5V
Maximum output current IO_MAX 3A
Transient response 0.3 A to 3 A 5%
Output voltage ripple 50 mV
Input voltage ripple 400 mV
Switching frequency ƒSW 500 KHz

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9.2.2 Detailed Design Procedure

9.2.2.1 Output Voltage Set-Point
The output voltage of LV14360 is externally adjustable using a resistor divider network. The divider network is
comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 7 is used to determine the
output voltage:

VOUT 0.75
RFBT u RFBB
0.75 (7)

Choose the value of RFBT to be 100 kΩ. With the desired output voltage set to 5 V and the VFB = 0.75 V, the
RFBB value can then be calculated using Equation 7. The formula yields to a value 17.65 kΩ. Choose the closest
available value of 17.8 kΩ for RFBB.
9.2.2.2 Switching Frequency
For desired frequency, use Equation 8 to calculate the required value for RT.

1.088
RT (k:) 42904 u ¦SW N+] (8)

For 500 KHz, the calculated RT is 49.66 kΩ, and standard value 49.9 kΩ can be used to set the switching
frequency at 500 KHz.
9.2.2.3 Output Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the RMS current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with
the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 9 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current. A reasonable value of KIND should be 20% to
40%. During an instantaneous short or overcurrent operation event, the RMS and peak inductor current can be
high. The inductor current rating should be higher than current limit.

VOUT u (VIN_MAX VOUT )

'iL
VIN _ MAX u L u ¦SW (9)

VIN_MAX VOUT VOUT

LMIN u
IOUT u KIND VIN_MAX u ¦SW (10)

In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too
low of an inductance can generate too large of an inductor current ripple such that overcurrent protection at the
full load can be falsely triggered. It also generates more conduction loss since the RMS current is slightly higher.
Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak
current mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current
ripple improves the comparator signal-to-noise ratio.
For this design example, choose KIND = 0.4. The minimum inductor value is calculated to be 7.64 µH, and a
nearest standard value is chosen: 8.2 µH. A standard 8.2-μH ferrite inductor with a capability of 3-A RMS current
and 6-A saturation current can be used.
9.2.2.4 Output Capacitor Selection
Choose the output capacitor or capacitors, COUT, with care since it directly affects the steady state output
voltage ripple, loop stability, and the voltage overshoot and undershoot during load current transients.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the equivalent series resistance (ESR) of the output capacitors:

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'VOUT_ESR 'iL u ESR KIND u IOUT u ESR (11)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

'iL KIND u IOUT

'VOUT_C
8 u ¦SW u COUT 8 u ¦SW u COUT (12)

The two components in the voltage ripple are not in-phase, so the actual peak-to-peak ripple is smaller than the
sum of two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,
output capacitors provide the required charge before the inductor current can slew up to the appropriate level.
The control loop of the regulator usually needs three or more clock cycles to respond to the output voltage
droop. The output capacitance must be large enough to supply the current difference for three clock cycles
to maintain the output voltage within the specified range. Equation 13 shows the minimum output capacitance
needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors
absorb energy stored in the inductor. The catch diode cannot sink current so the energy stored in the inductor
results in an output voltage overshoot. Equation 14 calculates the minimum capacitance required to keep the
voltage overshoot within a specified range.

3 u (IOH IOL )
COUT !
¦SW u 9US (13)

2 2
IOH IOL
COUT ! uL
(VOUT VOS )2 2
VOUT (14)

where
• KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT)
• IOL = Low level output current during load transient
• IOH = High level output current during load transient
• VUS = Target output voltage undershoot
• VOS = Target output voltage overshoot
For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and
choose KIND = 0.4. Equation 11 yields ESR no larger than 41.7 mΩ and Equation 12 yields COUT no smaller than
6 μF. For the target overshoot and undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. COUT
can be calculated to be no smaller than 64.8 μF and 6.4 μF by Equation 13 and Equation 14, respectively. In
summary, the most stringent criteria for the output capacitor is 100 μF. For this design example, two 47-μF, 16-V,
X7R ceramic capacitors with 5-mΩ ESR are used in parallel.
9.2.2.5 Schottky Diode Selection
The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage.
The current rating for the diode should be equal to the maximum output current for best reliability in most
applications. In cases where the input voltage is much greater than the output voltage, the average diode current
is lower. In this case, it is possible to use a diode with a lower average current rating, approximately (1 – D) ×
IOUT, however, the peak current rating should be higher than the maximum load current. A 3-A rated diode is a
good starting point.
9.2.2.6 Input Capacitor Selection
The LV14360 device requires high frequency input decoupling capacitor or capacitors and a bulk input capacitor,
depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7
μF to 10 μF. A high-quality ceramic capacitor type X5R or X7R with sufficient voltage rating is recommended.
To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is

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recommended. Additionally, some bulk capacitance can be required, especially if the LV14360 circuit is not
located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to
the voltage spike due to the lead inductance of the cable or the trace. For this design, two 2.2-μF, X7R ceramic
capacitors rated for 100 V are used. Use a 0.1-μF capacitor for high-frequency filtering and place it as close as
possible to the device pins.
9.2.2.7 Bootstrap Capacitor Selection
Every LV14360 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and rated
16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

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9.2.3 Application Curves

Unless otherwise specified the following conditions apply: VIN = 24 V, fSW = 500 KHz, L = 8.2 µH, COUT = 2 × 47 µF, TA =
25°C.

VOUT = 5 V IOUT = 2 A
VOUT = 5 V IOUT = 2 A
Figure 9-3. Start-up By VIN
Figure 9-2. Start-up by EN

VOUT = 5 V IOUT = 0 A VOUT = 5 V IOUT = 200 mA

Figure 9-4. Sleep Mode Figure 9-5. DCM Mode

VOUT = 5 V IOUT = 2 A IOUT: 20% → 80% of 3 A Slew rate = 100 mA/μs

Figure 9-6. CCM Mode Figure 9-7. Load Transient

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VOUT = 5 V VOUT = 5 V

Figure 9-8. Output Short Figure 9-9. Output Short Recovery

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10 Power Supply Recommendations

The LV14360 is designed to operate from an input voltage supply range between 4.3 V and 60 V. This input
supply should be able to withstand the maximum input current and maintain a stable voltage. The resistance of
the input supply rail must be low enough that an input current transient does not cause a high enough drop at
the LV14360 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply
is located more than a few inches from the LV14360, additional bulk capacitance may be required in addition to
the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic
capacitor is a typical choice.
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The feedback network, resistor RFBT and RFBB, should be kept close to the FB pin. VOUT sense path away
from noisy nodes and preferably through a layer on the other side of a shielding layer.
2. The input bypass capacitor CIN must be placed as close as possible to the VIN pin and ground. Grounding
for both the input and output capacitors should consist of localized top side planes that connect to the GND
pin and PAD.
3. The inductor L should be placed close to the SW pin to reduce magnetic and electrostatic noise.
4. Place the output capacitor, COUT close to the junction of L and the diode D. Keep the L, D, and COUT trace as
short as possible to reduce conducted and radiated noise and increase overall efficiency.
5. The ground connection for the diode, CIN, and COUT should be as small as possible and tied to the system
ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane.
6. For more detail on switching power supply layout considerations see AN-1149 Layout Guidelines for
Switching Power Supplies.

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11.2 Layout Example

Output Bypass
Capacitor

Output
Inductor

Rectifier Diode
BOOT
Capacitor
Input Bypass
Capacitor

BOOT SW
Soft-Start
Capacitor
VIN GND

EN SS

UVLO Adjust RT/SYNC FB

Resistor Output Voltage
Set Resistor

Frequency Thermal VIA

Set Resistor
Signal VIA

Figure 11-1. Layout

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
PowerPAD™ is a trademark of TI.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LV14360PDDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 150 14360P Samples

LV14360SDDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 150 14360S Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 18-May-2023

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jan-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LV14360PDDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jan-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LV14360PDDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/A 08/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/A 08/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

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