Department of Electronics &Communication Engineering, VNIT, Nagpur.
Mid sem Exam February 2023
Fourth Sem B.Tech (Electronics &Communication)
Analog circuit design (ECL308), Slot- G
Time: 1.5 Hrs Marks: 25
Q1)A
BIT differential amplifier uses a 300 juA bias current. What is the value of r, of cach device?
B= 150. (Co1, 02)
Q.2) Which two parameters of op-amp not including frequency response are frequency dependent. (CO1, 01)
Q.3) For the following circuit, determine collector currents and collector voltages. Also find input
Impedence and overall voltage gain for the circuit. Assume B=100. Q1-03 and Q2-Q4 form Darlington
pair of transistors.
(CO4, 10)
VCC
15V
R1 LR2
10kQ 10kQ R5
2k2
Vu Q2
Q5
SR4
12kQ 12k2
VEE
-15V
Q.4) Find gain for the following circuit. (CO1,02)
R2 R3 1OkO
10kQ
R4
S1kQ
R1
Vin 1kO
U1
Q5) Measurement of a circuit for an ideal op-amp shows voltage at op-amp olp to be -2 Vand that at
negative /p to be -3 V. For the op-amp to be ideal, what wWould be the voltage at positive terminal? (CO1, 01)
Q6) Anoninverting op-amp with again of 200 has Vp offset voltage of +2mv. Find the o/p when /p
is 0.01 sin wt. (CO3, 02)
0.7) How long does it take for the o/p of an op-amp to go from -10 Vto +10 Vif the slew rate is 0.5V/us. (CO1, 02)
a.8) Design a circuit using single op-amp to get Vo =V1+3V2-2(V3 +3 V4). (CO3, 02)
Q.9) In an instrumentation system, there is a need to take the difference between two signals,
VI=3 sin(2|T 60t) +(0.01 sin(2| 1000:), V2=3 sin(21| 60t) -(0.01 sin(21T 10000). Draw the circuit.
Gain of 10 is required to amplify 1000 Hz component. Choose R1= RÍ= 10 ko. (CO3, 03)
Department of Electronics &Communication Engineering, VNIT, Nagpur.
End Sem Exam April 2023
Fourth SemB.Tech (Electronics & Communication)
Analog circuit design (ECL308)
Slot- G
Time: 3Hrs
Marks: 55
Q.1a) For the cascaded differential amplifier shown in figure
determine: (i) The collector current and
collector to emitter voltage for each transistor. (ii) The overall
voltage gain. (ii)
resistance. (iv) The output resistance. Assume that for the transistors used B= The input
0.715V. In addition,draw the AC equivalent model for the 100 and Vag =
circuit. (CO1, 06)
9 Vcc =10 V
Rc12.2Ka Rca2.2KSa Res1.2KS1 ReA1.2Ks2
Noninverting Vo1 Vo
input
R'E R'E
$1000 M009
Vid
Inverting
input
Rei7Ka 15KK2REz
o-VeE =10 V
b) If in the output of the above circuit we need the DC
component to be zero what kind of
circuitry we should connect.Give one example along with the
derivation. (CO1, 03 )
c) In order to achieve the stabilization in the DC emitter
current of the circuit designed in (a)
which circuitry can be added to get stable operating point.
(CO1, 01)
R1
Q2 a) For the given circuit find V,(t). Consider
and +Vsat= 15V
R1=R2=R3R4 = R
V,(t)
If R= 1kohm, V= 10V, and C= 1 mF. Calculate the time at which
RA N the op-amp saturates.
(CO4,05)
2b) A non-inverting op-amp with again of 100is found to have a
3db
Particular application, bandwidth of 20 kHz is required. What is thefrequency
of 10 kHz. For a
these conditions?
highest gain available under
(CO1,03)
the expression for
10k Vc(t) K) In the given circuit derive
output voltage at t=
output voltage and find the
addition, draw an
Ims and 10s respectively. In (CO4 ,03)
output Vs time Curve for the same.
10V
Q.3a) A5-bit D/A converter produces Vour =0.2 Vfor a digital input of o001. Find the value of Vout
for an input of 11111: (CO1 ,02)
b) What is the advantage of R/2R ladder DACS Over those that use binary weighted resistors? (CO1 ,01)
U1 Q. 4a) For the circuit shown, what are the upper and lower threshold
voltages? Assume tVsat= 15 v. (C01,01)
R1
741 10k2
SR2
5kQ
~v23v
b) Draw and explain fullwave rectifier circuit. If the position of diodes is reversed, what will be the
effect on the output? (CO1, 02)
c)Design acircuit to implement following equation using op-amp. Use Log and Antilog ckt.
y=(x*+z/2 (CO3, 04)
R2 R3
d) What is the the circuit shown in figure? Find the overall
10kQ 10kQ
voltage gain of the circuit.What value of R6 must be used
741 to change the gain of the circuit to 1000?
(CO4,02)
100k2
SR6
1.0k2 R7
100k2
U2 741
R4
10k2 R5
10k2
741
100 2 e)The signal Viof peak voltage 8 Vis applied to the non
inverting terminal of an ideal opamp. The transistor has
+VCC VBE = 0.7 V, B=100; VuED = 1.5 V, VCC =t10 V. How many
LED times LED glows in this circuit? (CO3,02)
2 kS)
15 kí)
-VCC
Vi
4V
2V
2\
-4V
-5V
Qpa) Derive the transfer function of all pass phase lead ckt. Also design an all pass phase lead ckt
for aphase shift of +90° at a frequency of 1 kHz. C 0 -0|lr (CO5,04)
b)Design a lowpass filter to meet the following specifications. (COS, 06)
1) relative attenuation < 3 dB for f< 1 KHz
2) relative attenuation > 35 dB for f > 4 kHz
Assume Capacitor values as 1.414,0.707 or 3.546, 1.392,0.202 . Final value of C1= 0.047pF.
Qga) Design a circuit to produce o/p pulse of 120 us using IC555. (CO2, 03)
b) Draw and explain block diagram of PLL? (CO2,02)
c) For the given circuit derive the expression
0.1kQ for the Ton and Tof and clearly state the duty
R4 cycle. If the same circuit is to be used as a square wave
0.2kQ
generator, what should be the updated value of R3? (CO4 ,05)
R1
W
2kO
Department of Electronics & Communication Engineering, VNIT, Nagpur.
Mid Sem Exam March 2022
Fourth SemB.Tech(Electronics & Communication)
Analog circuit design (ECL308)
Slot- G (SET A) (Roll Nos- BT20ECE001 – BT20ECE060)
Time: 1Hr Marks: 25
1. Consider a differential amplifier with current mirror circuit in Figure 1. Determine the
differential voltage gain and current through diode in the following circuit if RB=8 kΩ,
R=10kΩ, RC=10 kΩ, VCC=15 V, VEE=−10 V. (4, CO1)
Figure1
2. For the dual input balanced output differential amplifier with RE= 4.7kΩ, RC= 2.2kΩ,
Rin1= Rin2=50Ω, β=100 and VBE = 0.7V, determine output voltage if V1 = 30mV peak to peak
at 2 KHz and V2 = 50mV peak to peak at 2KHz. What is the maximum peak to peak output
voltage without clipping? (2, CO1)
3. Using the circuit of Figure 2, determine the single-ended input-differential output and
single-ended input-single-ended output voltage gains. Use the following component values:
RT=10kΩ, RC=10kΩ, VCC=10 V, VEE=−10 V. (4, CO1)
Figure 2
4. For the circuit in figure 3, determine and sketch the output for given Vin. (03, CO2)
Figure 3
5. For the following circuit, determine o/p. (02, CO4)
6. The amplifier circuit shown in figure 4 is implemented
using a compensated OP-AMP and has an open loop
voltage gain Ao = 105 V/V and an open loop cut-off
frequency, fc = 8 Hz. Find voltage gain of the amplifier
at 15 KHz. (04, CO2)
Figure 4
7. Measurement of a circuit for an ideal op-amp shows voltage at op-amp o/p to be -2 V and
that at negative(-) input to be -3 V. For the amplifier to be ideal, what should be the voltage
at positive i/p? (01, CO1)
8. Open loop gain for the inverting op-amp is 100. Closed loop gain required is -25. If larger
resistor used is 100 kΩ, what will be the value of smaller resistor? (03, CO4)
9. For the following circuit, If VOUT = 1 volt for VIN = 0.1 volt and VOUT = 6 volt for VIN = 1 volt,
where VOUT is measured across RL connected at the output of this OP AMP, find the value
of RF/RIN . Vref is fixed. (02, CO2)
Department of Electronics & Communication Engineering, VNIT, Nagpur.
Mid Sem Exam March 2022
Fourth SemB.Tech(Electronics & Communication)
Analog circuit design (ECL308)
Slot- G (SET B) (Roll Nos- BT20ECE061 onwards and ex-students)
Time: 1Hr Marks: 25
1. Consider a differential amplifier with current mirror circuit in Figure 1. Determine the differential
voltage gain and current through diode in the following circuit if RB=8 kΩ, R=10kΩ, RC=10 kΩ,
VCC=15 V, VEE=−15 V. ( 4, CO1)
Figure1
2. For the dual input balanced output differential amplifier with RE= 4.7kΩ, RC= 2.2kΩ,
Rin1= Rin2= 50Ω, 𝛽=50 and VBE = 0.7V, determine output voltage if V1 = 20mV peak to peak
at 2KHz and V2 = 50mV peak to peak at 2KHz. What is the maximum peak to peak output
voltage without clipping? (2, CO1)
3. Using the circuit of Figure 2, determine the single-ended input-differential output and single-ended
input-single-ended output voltage gains. Use the following component values:
RT=10kΩ, RC=10kΩ, VCC= 15 V, VEE= −15 V. (4, CO1)
Figure 2
4. For the circuit in figure 3, determine and sketch the output. (03, CO2)
Figure 3
5. For the following circuit, determine o/p. (02, CO4)
6. The amplifier circuit shown in figure is implemented using
a compensated OP-AMP and has an open loop voltage gain
Ao = 105 V/V and an open loop cut-off frequency,
fc = 8 Hz. Find voltage gain of the amplifier at 30 KHz.
(04, CO2)
7. Measurement of a circuit for an ideal op-amp shows voltage at op-amp o/p to be -4 V and
that at negative(-) input to be -6 V. For the amplifier to be ideal, what should be the voltage
at positive i/p? (01, CO1)
8. Open loop gain for the inverting op-amp is 200. Closed loop gain required is -20. If larger
resistor used is 100 kΩ, what will be the value of smaller resistor? (03, CO4)
9. For the following circuit, If VOUT = 2 volt for VIN = 0.2 volt and VOUT = 8 volt for VIN = 2 volt,
where VOUT is measured across RL connected at the output of this OP AMP, find the value
of RF/RIN . Vref is fixed. (02, CO2)
