// Half Adder

module HA(s,c,a,b);
input a,b;
output s,c;
xor g1(s,a,b);
and g2(c,a,b);
endmodule

Module HA_tb;
reg a,b;
wire s,c;
HA uut(s,c,a,b);
initial begin
a=0;b=0;
#10;
a=1; b=0;
#10;

a=0; b=1;
#10;
a=1;
b=1;
#10; $finish();

end endmodule

// full Adder

module fourbitadder (cout,sum,a,b,cin);

input[3:0] a,b;
input cin;
output cout;
output[3:0] sum;
assign {cout,sum}=a+b+cin;

endmodule

module fourbitsub(bout,sum,a,b,cin

);
input[3:0] a,b;
input cin;
output bout;
output[3:0] sum;
parameter c=4'b0001;
assign {cout,sum}=a-b-c;

endmodule
s

module fourbit_tb( );
reg[3:0] a,b;
reg cin;
wire cout;
wire [3:0] sum;
fourbitadder uut (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));
initial begin
 a=4'b0000;b=4'b0001;cin=0; #10;
a=4'b0010;b=4'b1001;cin=1; #10; //add 2+9
a=4'b1111;b=4'b1001;cin=1; #10; //add 2+9
a=4'b1110;b=4'b1001;cin=1; #10; //add 2+9
a=4'b0010;b=4'b1011;cin=1; #10; //add 2+9

$finish;
end
endmodule

// 4 bit Adder

(a) Using Gate Level Modelling

module full_adder(A,B,Cin,S,C); input A,B,Cin;
ouput S,C; wire w1,w2,w3;
xor G1(w1,A,B); and G2(w2,A,B); cor G3(S,w1,Cin); and G4(w3,w1,Cin); or
G5(C,w3,w2); end module;
(b)Using Data flow level: module full_adder(
nput A,B,Cin, output S,C );
wire w1,w2,w3; assign w1 = A^ B; assign w2 = A&B;
assign S = w1 ^ Cin; assign w3 = w1 & Cin; assing C = w2 | w3; endmodule
module four bit adder (
input A1, A2, A3, A4, B1, B2, B3, B4,
output S0, S1, S2, S3, C3 );
wire C0, C1, C2;
full adder fa0 (.A(Al), .B(B1), .Cin(1'b0), .S(S1), .C(C1)); full adder fal
(.A(A2), .B(B2), .Cin (C0), .S(S1), .C(C1)); full adder fa2 (.A(A3), .B(B3), .Cin
(Cl), .S(S2), .C(C2)); full adder fa3 (.A(A4), .B(B4), .Cin (C2), .S(S3), .C(C3));
endmodule
(c) Using Behavoural level module four_bit_adder(
input [3:0] A,B,
output reg [3:0] S,
output reg C3 );
reg [4:0] sum; always @ ( * ) begin sum = A + B ;
S = sum[3:0]; C3 = sum[4]; end endmodule

module tb four_bit_adder(); reg [3:0] A, B;

wire [3:0] S; wire C3;
four bit adder uut (
.A1 (A[0]), .A2 (A[1]), .A3(A(2)), .A4 (A[3]), .B1 (B[0]), .B2 (B[1]), .B3
(B[2]), .B4(B[3]),
. SO (S[0]), .$1 (S[1]), .S2 (S[2]), .$3 ($[3]), .C3 (C3) ); initial begin
A = 4'bl010; B = 4'b0101; #10;
$display("A = %d, B = %d, S = %d, C = %3b", A, B, S, C3): A = 4'b1111; B = 4'b0001;
#10;
$display ("A = %d, B = %d, S = %d, C = %3b", A, B, S, C3); A = 4'b1000; B =
4'b0111; #10;
$display ("A = %d, B = %d, S = %d, C = %3b", A, B, S, C3); A = 4'b0000; B =
4'b0000; #10;
$display ("A = %d, B = %d, S = %d, C = %3b", A, B, S, C3); $finish;
end
endmodule

//

// 4 bit Subtratror
module full_subtractor(
input wire a, b, bin,
output wire diff, bout
);
wire xor1, not_a, and1, and2;

xor(xor1, a, b);
xor(diff, xor1, bin);
not(not_a, a);
and(and1, not_a, b);
and(and2, bin, xor1);
or(bout, and1, and2);

endmodule

module bit_subtractor(
input wire [3:0] a, b,
input wire bin,
output wire [3:0] diff,
output wire bout
);
wire b1, b2, b3;

full_subtractor fs0(.a(a[0]), .b(b[0]), .bin(bin), .diff(diff[0]), .bout(b1));

full_subtractor fs1(.a(a[1]), .b(b[1]), .bin(b1), .diff(diff[1]), .bout(b2));
full_subtractor fs2(.a(a[2]), .b(b[2]), .bin(b2), .diff(diff[2]), .bout(b3));
full_subtractor fs3(.a(a[3]), .b(b[3]), .bin(b3), .diff(diff[3]), .bout(bout));

endmodule

module tb_bit_subtractor;

reg [3:0] a, b;
reg bin;
wire [3:0] diff;
wire bout;

bit_subtractor uut (
.a(a),
.b(b),
.bin(bin),
.diff(diff),
.bout(bout)
);

initial begin
// Test Case 1: Subtract 4'b0000 from 4'b0000
a = 4'b0000; b = 4'b0000; bin = 0;
#10;
$display("A = %b, B = %b, Bin = %b, Diff = %b, Bout = %b", a, b, bin, diff,
bout);

// Test Case 2: Subtract 4'b0011 from 4'b0101

a = 4'b0101; b = 4'b0011; bin = 0;
#10;
$display("A = %b, B = %b, Bin = %b, Diff = %b, Bout = %b", a, b, bin, diff,
bout);
 // Test Case 3: Subtract 4'b1111 from 4'b0001
a = 4'b0001; b = 4'b1111; bin = 0;
#10;
$display("A = %b, B = %b, Bin = %b, Diff = %b, Bout = %b", a, b, bin, diff,
bout);

// Test Case 4: Subtract 4'b1111 from 4'b1111 with borrow in

a = 4'b1111; b = 4'b1111; bin = 1;
#10;
$display("A = %b, B = %b, Bin = %b, Diff = %b, Bout = %b", a, b, bin, diff,
bout);

// Test Case 5: Subtract 4'b1010 from 4'b1101

a = 4'b1101; b = 4'b1010; bin = 0;
#10;
$display("A = %b, B = %b, Bin = %b, Diff = %b, Bout = %b", a, b, bin, diff,
bout);

// End simulation
$finish;
end
endmodule

//Array multipler

module multiplier(
input [3:0] A,
input [3:0] B,
output [7:0] P
);
wire [3:0] pp0, pp1, pp2, pp3;
wire [7:0] sum1, sum2, sum3;
wire [7:0] shift_pp1, shift_pp2, shift_pp3;

assign pp0 = A & {4{B[0]}};

assign pp1 = A & {4{B[1]}};
assign pp2 = A & {4{B[2]}};
assign pp3 = A & {4{B[3]}};

assign shift_pp1 = {pp1, 1'b0};

assign shift_pp2 = {pp2, 2'b00};
assign shift_pp3 = {pp3, 3'b000};

assign sum1 = {4'b0000, pp0} + shift_pp1;

assign sum2 = sum1 + shift_pp2;
assign sum3 = sum2 + shift_pp3;

assign P = sum3;
endmodule

module arr_multiplier_tb;
reg [3:0] A;
reg [3:0] B;
wire [7:0] P;

multiplier uut (
.A(A),
 .B(B),
.P(P)
);

initial begin
A = 4'b0000;
B = 4'b0000;
$monitor("A = %b , B = %b , P = %b", A, B, P);
#10 A = 4'b0001; B = 4'b0001;
#10 A = 4'b0010; B = 4'b0011;
#10 A = 4'b0101; B = 4'b0101;
#10 A = 4'b0111; B = 4'b0011;
#10 A = 4'b1111; B = 4'b1111;
#10 A = 4'b1010; B = 4'b0101;
#10 A = 4'b1001; B = 4'b0110;
#10 $finish;
end
endmodule

// booth multiplier

module booth (
input [3:0] multiplicand,
input [3:0] multiplier,
output [7:0] product
);

reg [3:0] A;
reg [3:0] Q;
reg [3:0] M;
reg Qm1;
reg [7:0] result;
integer i;

always @* begin
A = 4'b0000;
Q = multiplier;
M = multiplicand;
Qm1 = 1'b0;
result = 8'b00000000;

for (i = 0; i < 4; i = i + 1) begin

case ({Q[0], Qm1})
2'b01: A = A + M;
2'b10: A = A - M;
default: ;
endcase

{A, Q, Qm1} = {A[3], A, Q, Qm1} >> 1;

end

result = {A, Q};

end

assign product = result;

endmodule

module tb_booth;
reg [3:0] multiplicand;
reg [3:0] multiplier;
wire [7:0] product;

booth uut (
.multiplicand(multiplicand),
.multiplier(multiplier),
.product(product)
);

initial begin
multiplicand = 4'd3; multiplier = 4'd2;
#10;
$display("Multiplicand: %d, Multiplier: %d, Product: %d", multiplicand,
multiplier, product);

multiplicand = 4'd4; multiplier = 4'd5;

#10;
$display("Multiplicand: %d, Multiplier: %d, Product: %d", multiplicand,
multiplier, product);

multiplicand = 4'd7; multiplier = 4'd3;

#10;
$display("Multiplicand: %d, Multiplier: %d, Product: %d", multiplicand,
multiplier, product);

multiplicand = 4'b1100; multiplier = 4'd3;

#10;
$display("Multiplicand: %d, Multiplier: %d, Product: %d", multiplicand,
multiplier, product);

$finish;
end
endmodule

// mod 13 cont

// Mod-13 Counter using JK Flip-Flops

module mod13_counter (
input clk_in,
input reset_n,
output reg [3:0] count_val
);

wire flip0, flip1, flip2, flip3;

wire flip0_n, flip1_n, flip2_n, flip3_n;

// Instantiate JK flip-flops
jkff jkff0 (
.clk(clk_in),
.rst_n(reset_n),
.j(1'b1),
 .k(1'b1),
.q(flip0),
.q_n(flip0_n)
);

jkff jkff1 (
.clk(flip0),
.rst_n(reset_n),
.j(1'b1),
.k(1'b1),
.q(flip1),
.q_n(flip1_n)
);

jkff jkff2 (
.clk(flip1),
.rst_n(reset_n),
.j(1'b1),
.k(1'b1),
.q(flip2),
.q_n(flip2_n)
);

jkff jkff3 (
.clk(flip2),
.rst_n(reset_n),
.j(1'b1),
.k(1'b1),
.q(flip3),
.q_n(flip3_n)
);

// Counting Logic
always @(posedge clk_in or negedge reset_n) begin
if (!reset_n)
count_val <= 4'd0;
else if (count_val == 4'd12)
count_val <= 4'd0;
else
count_val <= count_val + 1;
end
endmodule

// JK Flip-Flop Module
module jkff (
input clk,
input rst_n,
input j,
input k,
output reg q,
output reg q_n
);

always @(posedge clk or negedge rst_n) begin

 if (!rst_n) begin
q <= 1'b0;
q_n <= 1'b1;
end else begin
case ({j, k})
2'b00: ; // No change
2'b01: begin q <= 0; q_n <= 1; end
2'b10: begin q <= 1; q_n <= 0; end
2'b11: begin q <= ~q; q_n <= ~q_n; end
endcase
end
end

endmodule

// Testbench for Mod-13 Counter

module tb_mod13_counter;
reg clk_test;
reg rst_n_test;
wire [3:0] count_out;

// Instantiate the Mod-13 Counter

mod13_counter uut (
.clk_in(clk_test),
.reset_n(rst_n_test),
.count_val(count_out)
);

initial begin
clk_test = 0;
rst_n_test = 0;
#10 rst_n_test = 1;
#500 $finish;
end

// Generate Clock
always #5 clk_test = ~clk_test;

// Display the Counter Output

initial begin
$monitor("Time: %0t | Count: %0d", $time, count_out);
end
endmodule

// shift register

// SISO

`timescale 1ns / 1ps module d_flip_flop( input wire clk, input wire reset, input
wire d, output reg q
);
always @(posedge clk or posedge reset) begin

if (reset) q<=1'b0;
else q<=d; end
endmodule module shit_reg( input wire clk, input wire reset,
input wire serial_in, output wire serial_out
);
wire q0, q1, q2, q3;

d_flip_flop dff0(
.clk(clk),
.reset(reset),
.d(serial_in),
.q(q0)
);
d_flip_flop dff1(
.clk(clk),
.reset(reset), // Connect reset signal
.d(q0),
.q(q1)
);
d_flip_flop dff2(
.clk(clk),

.reset(reset), // Connect reset signal

.d(q1),
.q(q2)
);
d_flip_flop dff3(
.clk(clk),
.reset(reset), // Connect reset signal
.d(q2),
.q(q3)
);
assign serial_out = q3; endmodule TESTBENCH:
module tb_shit_reg; reg clk;
reg reset; reg serial_in;
wire serial_out; shit_reg uut (
.clk(clk),
.reset(reset),
.serial_in(serial_in),
.serial_out(serial_out)
);
initial begin clk = 0;
forever #5 clk = ~clk; // 10 ns clock period (100 MHz)

end

initial begin reset = 1;

serial_in = 0;
#10
reset = 0;
#10 serial_in = 1;
#10 serial_in = 0;
#10 serial_in = 1;
#10 serial_in = 1;
#10;
$display("serial_out at t = %0t ns : %b", $time, serial_out); #10 reset = 1;
#10 reset = 0;
#10 serial_in = 0;
#10 serial_in = 1;
#10 serial_in = 0;
#10;
$finish; end
initial begin
$monitor("At time %0t, clk = %b, reset = %b, serial_in = %b, serial_out = %b",
$time, clk, reset, serial_in, serial_out); end
endmodule
WAVEFORM:

// SIPO
module d_flip_flop( input wire clk, input wire reset, input wire d, output reg q
);

always @(posedge clk or posedge reset) begin if (reset)

q <= 1'b0;
else
q <= d; end endmodule

module shitsipo_reg( input wire clk,

input wire reset, input wire serial_in,
output wire [3:0] parallel_out // Parallel output
);
wire q0, q1, q2, q3;

d_flip_flop dff0(
.clk(clk),
.reset(reset),
.d(serial_in),
.q(q0)
);
d_flip_flop dff1(
.clk(clk),
.reset(reset),
.d(q0),
.q(q1)
);
d_flip_flop dff2(

.clk(clk),
.reset(reset),

.d(q1),
.q(q2)
);
d_flip_flop dff3(
.clk(clk),
.reset(reset),
.d(q2),
.q(q3)
);
assign parallel_out = {q3, q2, q1, q0}; // Parallel output assignment endmodule
TESTBENCH:
`timescale 1ns / 1ps

module test_shitsipo_reg;
 // Inputs
reg clk;
reg reset;
reg serial_in;

// Outputs
wire [3:0] parallel_out;

// Instantiate the shitsipo_reg module

shitsipo_reg uut (
.clk(clk),
.reset(reset),
.serial_in(serial_in),
.parallel_out(parallel_out)
);

// Generate clock signal

always begin
#5 clk = ~clk; // Clock period = 10ns (100MHz)
end

// Initial block to apply test vectors

initial begin
// Initialize inputs
clk = 0;
reset = 0;
serial_in = 0;

// Apply reset
reset = 1;
#10;
reset = 0;

// Shift in 4 bits (one bit at a time)

serial_in = 1; #10; // serial_in = 1
serial_in = 0; #10; // serial_in = 0
serial_in = 1; #10; // serial_in = 1
serial_in = 1; #10; // serial_in = 1

// Check output (parallel_out should be 1101)

#10;
$display("parallel_out = %b", parallel_out);

// Test with another sequence

serial_in = 0; #10; // serial_in = 0
serial_in = 1; #10; // serial_in = 1
serial_in = 0; #10; // serial_in = 0

// Check output (parallel_out should be 1001)

#10;
$display("parallel_out = %b", parallel_out);

// Finish simulation
$finish;
end

endmodule
WAVEFORM:
CODE:
`timescale 1ns / 1ps module d_flip_flop( input wire clk, input wire reset, input
wire d,
output reg q
);
always @(posedge clk or posedge reset) begin if (reset)
q <= 1'b0;
else
q <= d; end endmodule

module piso( input wire clk,

input wire reset,

input wire [3:0] parallel_in, output wire serial_out
);
wire q0, q1, q2, q3; d_flip_flop dff0(
.clk(clk),
.reset(reset),
.d(parallel_in[0]),
.q(q0)
);
d_flip_flop dff1(
.clk(clk),
.reset(reset),
.d(q0),
.q(q1)
);
d_flip_flop dff2(
.clk(clk),
.reset(reset),
.d(q1),
.q(q2)
);
d_flip_flop dff3(
.clk(clk),
.reset(reset),
.d(q2),

.q(q3)
);

assign serial_out = q3; endmodule

TESTBENCH:
module tb_piso; reg clk;
reg reset;
reg [3:0] parallel_in; wire serial_out;
piso uut (
.clk(clk),
.reset(reset),
.parallel_in(parallel_in),
.serial_out(serial_out)
);
initial begin clk = 0;
forever #5 clk = ~clk; end
initial begin reset = 1;
parallel_in = 4'b0000; #10;
reset = 0;
parallel_in = 4'b1010; #10;
$display("At t = %0t ns, serial_out = %b", $time, serial_out);

#10; // Wait one clock cycle

$display("At t = %0t ns, serial_out = %b", $time, serial_out); #10; // Wait one
more clock cycle

$display("At t = %0t ns, serial_out = %b", $time, serial_out); #10; // Wait one
more clock cycle
$display("At t = %0t ns, serial_out = %b", $time, serial_out); #10; // Wait one
more clock cycle
$display("At t = %0t ns, serial_out = %b", $time, serial_out);
$finish; end
initial begin
$monitor("At time %0t, clk = %b, reset = %b, parallel_in = %b, serial_out = %b",
$time, clk, reset, parallel_in, serial_out); end

endmodule

1)PIPO

module d_flip_flop( input wire clk, input wire reset, input wire d, output reg q
);
always @(posedge clk or posedge reset) begin if (reset)
q <= 1'b0;

else
q <= d; end endmodule
module pipo( input wire clk, input wire reset,

input wire [3:0] parallel_in, output wire [3:0] parallel_out

);
wire q0, q1, q2, q3; d_flip_flop dff0(
.clk(clk),
.reset(reset),
.d(parallel_in[0]),
.q(q0)
);
d_flip_flop dff1(
.clk(clk),
.reset(reset),
.d(q0),
.q(q1)
);
d_flip_flop dff2(
.clk(clk),
.reset(reset),
.d(q1),
.q(q2)
);

d_flip_flop dff3(
.clk(clk),
.reset(reset),
.d(q2),
.q(q3)
);
assign parallel_out = {q3, q2, q1, q0}; // Parallel output assignment

endmodule

TESTBENCH:

module tb_pipo; reg clk;

reg reset;
reg [3:0] parallel_in;
wire [3:0] parallel_out; pipo uut (
.clk(clk),
.reset(reset),
.parallel_in(parallel_in),
.parallel_out(parallel_out)
);
initial begin clk = 0;
forever #5 clk = ~clk; end
initial begin reset = 1;
parallel_in = 4'b0000; #10;

reset = 0;
parallel_in = 4'b1100; #10;
parallel_in = 4'b0000; #10;
$display("parallel_out at t = %0t ns : %b", $time, parallel_out); #10 parallel_in =
4'b1111;

#10;
parallel_in = 4'b0000; #10;
$display("parallel_out at t = %0t ns : %b", $time, parallel_out);
$finish; end initial begin
$monitor("At time %0t, clk = %b, reset = %b, parallel_in = %b, parallel_out = %b",
$time, clk, reset, parallel_in, parallel_out); end
endmodule

CODE:
`timescale 1ns / 1ps
module universal_shift_register ( input wire clk,
input wire reset, input wire load, input wire shift_left,
input wire shift_right, input wire [3:0] parallel_in,
output reg [3:0] parallel_out
);
reg [3:0] reg_out;

always @(posedge clk or posedge reset) begin if (reset) begin

reg_out <= 4'b0000; end else if (load) begin reg_out <= parallel_in;

end else if (shift_left) begin reg_out <= {reg_out[2:0], 1'b0}; end else if
(shift_right) begin reg_out <= {1'b0, reg_out[3:1]}; end
end
always @(*) begin parallel_out = reg_out; end
endmodule

TESTBENCH:
module tb_universal_shift_register; reg clk;
reg reset; reg load;
reg shift_left; reg shift_right;
reg [3:0] parallel_in;
wire [3:0] parallel_out; universal_shift_register uut (
.clk(clk),
.reset(reset),
.load(load),
.shift_left(shift_left),
.shift_right(shift_right),
.parallel_in(parallel_in),
.parallel_out(parallel_out)

);
initial begin clk = 0;
forever #5 clk = ~clk; end
initial begin reset = 1;
load = 0;
shift_left = 0;
shift_right = 0; parallel_in = 4'b0000;
52
#10;
reset = 0;
#10;
parallel_in = 4'b1010; load = 1;
#10;
load = 0;
#10;
shift_right = 1;
#10;
shift_right = 0;
#10;
shift_left = 1;
#10;
shift_left = 0;
#10;

parallel_in = 4'b0110; load = 1;

#10;
load = 0;
#10;
shift_right = 1;
#10;
shift_right = 0;
shift_left = 1;
#10;
shift_left = 0;
#10;

// sr flip flop

module sr_flipflop (
input S,
input R,
input clk,
output Q,
 output Qn
);
wire nand1_out, nand2_out;
nand(nand1_out, S, clk);
nand(nand2_out, R, clk);
nand(Q, nand1_out, Qn);
nand(Qn, nand2_out, Q);
endmodule

module sr_flipflop_tb;

reg S;
reg R;
reg clk;
wire Q;
wire Qn;

sr_flipflop uut (
.S(S),
.R(R),
.clk(clk),
.Q(Q),
.Qn(Qn)
);

// Clock generation (period = 10 time units)

always begin
#5 clk = ~clk;
end

initial begin
// Initialize inputs
clk = 0;
S = 0;
R = 0;

// Apply stimulus to S and R

#10 S = 1; R = 0;
#10 S = 0; R = 1;
#10 S = 1; R = 1; // Invalid state
#10 S = 0; R = 0;
#10 S = 1; R = 0;
#10 S = 0; R = 0;

// Finish simulation
#50 $finish;
end

// Monitor signal changes during simulation

initial begin
$monitor("Time = %0d, S = %b, R = %b, clk = %b, Q = %b, Qn = %b", $time, S,
R, clk, Q, Qn);
end
endmodule
// jk

module flipflop (
input clk, rst_n,
input j,k,
output reg q,
output q_bar
);

always@(posedge clk) begin // for synchronous reset

if(!rst_n) q <= 0;
else begin
case({j,k})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= ~q; // Toggle
endcase
end
end
assign q_bar = ~q;
endmodule

module tb_flip_flop;
reg clk, rst_n;
reg j, k;
wire q, q_bar;
flipflop uut (
.clk(clk),
.rst_n(rst_n),
.j(j),
.k(k),
.q(q),
.q_bar(q_bar)
);

always #5 clk = ~clk;

initial begin
clk = 0; rst_n = 0;
j = 0; k = 0;
// Apply reset
#10 rst_n = 1; // Release reset after 10 ns
// No change (j = 0, k = 0)
#10 j = 0; k = 0;
// Reset q (j = 0, k = 1)
#10 j = 0; k = 1;
// Set q (j = 1, k = 0)
#10 j = 1; k = 0;
// Toggle q (j = 1, k = 1)
#10 j = 1; k = 1;
// Toggle q again (j = 1, k = 1)
#10 j = 1; k = 1;
 #20 $finish;
end
endmodule

// T ff

module T_flip_flop (
input T,
input clk,
output reg Q
);

always @(posedge clk) begin

if (T == 1)
Q <= ~Q; // Toggle Q when T = 1
else
Q <= Q; // No change when T = 0
end

endmodule

module tb_T_flip_flop;

reg T; // Input signal T

reg clk; // Input clock signal
wire Q; // Output signal Q

// Instantiate the T Flip-Flop

T_flip_flop uut (
.T(T),
.clk(clk),
.Q(Q)
);

// Clock generation (clock toggles every 5 time units)

always begin
#5 clk = ~clk; // Clock toggle every 5 time units
end

// Initial block to apply test vectors

initial begin
// Initialize inputs
clk = 0;
T = 0; // Start with T = 0

// Apply different test cases to T

#10 T = 0; // No change to Q
#10 T = 1; // Toggle Q
#10 T = 0; // No change to Q
#10 T = 1; // Toggle Q
#10 T = 1; // Toggle Q again
#10 T = 0; // No change to Q
 // End simulation after some time
#50 $finish;
end

// Monitor changes and display values

initial begin
$monitor("Time = %0d, T = %b, clk = %b, Q = %b", $time, T, clk, Q);
end

endmodule

// dff

module d_flipflop (
input D,
input clk,
output Q,
output Qn
);
wire nand1_out, nand2_out, nand3_out, nand4_out, Dn;
not(Dn, D);

nand(nand1_out, D, clk);
nand(nand2_out, Dn, clk);
nand(Q, nand1_out, Qn);
nand(Qn, nand2_out, Q);
endmodule

module d_flipflop_tb;

reg D;
reg clk;
wire Q;
wire Qn;

d_flipflop uut (
.D(D),
.clk(clk),
.Q(Q),
.Qn(Qn)
);

// Clock generation (period = 10 time units)

always begin
#5 clk = ~clk;
end

initial begin
// Initial values for inputs
clk = 0;
D = 0;

// Stimulus - Apply input patterns

#10 D = 1;
#10 D = 0;
 #10 D = 1;
#10 D = 0;

// Finish simulation after 50 time units

#50 $finish;
end

// Monitor signal changes during simulation

initial begin
$monitor("Time = %0d, D = %b, clk = %b, Q = %b, Qn = %b", $time, D, clk, Q,
Qn);
end
endmodule

// deg to rad
module degtoradian(

input wire [15:0] degrees, // 16-bit input for degrees

output wire [31:0] radians // 32-bit output for radians (fixed-point)
);
// Define constants
// pi/180 in fixed-point (multiplied by a scale factor, e.g., 2^16 for 16.16
format)
parameter PI_DIV_180 = 32'd1144; // Approximation of (π/180) * 2^16

// Perform the multiplication in fixed-point

// radians = degrees * (π/180) >> 16
assign radians = (degrees * PI_DIV_180) >> 16;

endmodule
module degtoradian_tb(

);
reg [15:0] degrees;
wire [31:0] radians;

// Instantiate the module

degtoradian uut (
.degrees(degrees),
.radians(radians)
);

initial begin
// Test cases
degrees = 16'd0; #10;
degrees = 16'd90; #10;
degrees = 16'd180; #10;
degrees = 16'd360; #10;

// Display results
$monitor("Degrees: %d, Radians (Fixed-Point): %d", degrees, radians);
end
endmodule