TCAD-Based Simulation of Hot-Carrier Degradation in p-Channel

MOSFETs Using Silicon Energy-Balance and Oxide Carrier-Transport

Equations

S. K. Mukundan, M. P. Pagey, C. R. Cirba,

R. D. Schrimpf, and K. F. Galloway
Department of Electrical Engineering and Computer Science,
Vanderbilt University, Nashville, TN 37235

September 3, 2000

Abstract

We present a TCAD-based approach for characterizing hot-carrier degradation in p-channel MOSFETs

that includes models for hot-electron injection, carrier transport, and electron trapping in the oxide. The
energy-balance equations have been solved in the silicon substrate to accurately model the carrier-heating
and injection processes. This approach clearly illustrates the physical mechanisms responsible for hot-carrier
degradation in p-channel MOSFETs. The simulations have been compared with experimental data obtained
from 0.8μm SOI pMOS devices and show an excellent match.

1 Introduction

In the past decade, the dimensions of devices used in modern integrated circuits have been scaled aggressively to
meet the demands for higher densities and faster operation. However, the power-supply voltages have not scaled
proportionately due to restrictions placed by issues such as compatibility with previous technologies, physical limits
on the threshold voltage, noise margins, and manufacturability constraints. This disproportionate scaling gives
rise to high lateral electric fields in metal-oxide-semiconductor field-effect transistors (MOSFETs) under normal
circuit operation. Such high fields result in energetic carriers that can overcome the Si-SiO2 energy barrier and
be injected into the gate oxide. The injected carriers can be trapped at defect sites in the oxide and/or create
interface traps that cause a change in the electrostatic potential and field distribution in the device under normal
device operation. This can result in significant changes in the electrical characteristics of the device such as the
threshold voltage, transconductance, and drain current [1, 2, 3]. The hot-carrier-induced device degradation has,
thus, become a fundamental reliability issue in deep-sub-micron MOSFETs [4].

The process of hot-carrier degradation has been modeled in the past using approaches based on the lucky-electron
concept [5]. Several semi-empirical models derived from the lucky-electron injection theory have been proposed
that predict the time-dependence of hot-carrier-induced device parameter shifts [6, 7, 8]. However, these models
utilize technology-dependent fitting parameters and do not capture the underlying physical mechanisms. Other
models based on Monte-Carlo simulations [9] or energy transport [10] have also been used to analyze the hot-carrier
degradation phenomena. The high computational cost involved in performing Monte-Carlo simulation limits its
applicability and thus, it is mainly utilized for validation purposes. Some of the past approaches based on energy
transport bear some similarities to the approach presented in this paper. These similarities and differences will be
discussed later in this paper. In this work, we present a TCAD-based approach for modeling hot-carrier degradation
in p-channel MOS transistors which focuses on modeling the basic mechanisms which are responsible for hot-
carrier degradation. In particular, we utilize energy-balance equations to account for non-local carrier heating

1
effects [11, 12]. The carrier injection into the oxide has been modeled using thermionic boundary condition [13].
Drift-diffusion transport equations for electrons and holes have been solved in the oxide in order to simulate the
effect of oxide field on trapped charge distribution. The carrier trapping rate in the oxide has been simulated
using a first order rate equation. The physics-based device simulation approach presented here offers an improved
understanding of the underlying mechanisms and reduces empiricism and technology dependence. Furthermore,
the implementation in a commercial TCAD tool makes this approach suitable for technology optimization for
hot-carrier reliability.

2 Models

A vast amount of research is available to clearly shown that the hot-carrier response of a device is strongly
dependent on the geometry and doping profile of the device. Thus, the use of process simulation to obtain
the structural description of the device is essential to correctly model its behavior. Hot-carrier-induced device
degradation proceeds through a series of physical mechanisms triggered by the presence of high electric fields.
These mechanisms and their dependence on each other need to be accurately modeled in order to predict the
hot-carrier response of the device. In particular, specific model choices need to be made for the following physical
mechanisms:

Carrier transport in silicon The accurate modeling of carrier distributions in the silicon and their energies is
essential to calculate the impact generation rate.

Impact generation Electron-hole pair generation in high-field regions due to impact generation is a primary
source of carriers injected into the oxide.

Hot-carrier injection The location and flux of the hot-carrier injection current determines the device degradation
rate.

Carrier transport in the oxide The simulation of carrier transport under applied biases is essential to determine
the spatial distribution of trapped charge in the oxide.

Electron trapping In pMOS devices, the primary oxide degradation mechanism is trapping of injected electrons
at defects in the oxide.

Effect of trapped charge on channel mobility The device degradation is measured in terms of the influence
of trapped charge in the oxide on the carrier conduction in the channel.

The essence of the approach presented here is contained in the model choices that were made to self-consistently
simulate the carrier heating and injection processes in silicon and the carrier transport and trapping processes in
the oxide. This section describes the approach we used to obtain the device structure as well as the model choices
that were made for the physical mechanisms that influence the hot-carrier degradation process.

2.1 Device Geometry

The SOI transistor structure used in the device simulations presented here was obtained from SILVACO’s ATHENATM [14]
process simulator. The two-dimensional cross section of the device was simulated from the description of the
process used to fabricate the test devices. The device structure produced by the process simulator is shown in
Fig. 1. This figure shows the doping profile in the device as obtained from process simulation. The fabricated
devices had body contacts to control the body bias and measure the body current. The modeling of devices
with such body contacts requires the use of three-dimensional simulation tools. In order to reduce the simulation
time, we have reduced the problem to a two-dimensional domain by approximating the effect of a body contact
using an artificial “body” electrode in the silicon film as shown in Fig. 1. The size and location of this electrode

2
were chosen to minimize its effect on the potential distribution in the device. This approximation was verified
by comparing simulated IDS -VGS characteristics of structures with and without the artificial body contact with
corresponding experimental characteristics of devices with and without body contacts. SILVACO’s ATLASTM [15]
device simulator was used to perform all the simulations reported in this paper.

Doping Concentration (/cm3) 1021

1020
1019
-1.0 Gate 1018
1017
1016
-0.8 1015

-0.6 Source Drain

Buried Oxide
-0.4
Body contact

-0.2

0.0
Substrate

5.2 5.6 6.0 6.4 6.8 7.2

Figure 1: Structure and doping profile of the SOI p-channel transistor used for the simulations in this paper. This
structure was obtained from process simulation. The dotted lines indicate the locations of the source-body and
drain-body junctions. An artificial body electrode contact was used to simulate the effect of a body contact. The
non-symmetric nature of the source-body and drain body junction shapes is a consequence of introducing this
artificial body electrode and is not a part of the fabrication process.

2.2 Carrier Transport in Silicon

Carrier transport in semiconductors has traditionally been modeled using drift-diffusion equations. This approach
assumes that the carrier energy distribution is Maxwellian in nature. Furthermore, drift-diffusion-based models
assume that energy gained by carriers due to high electric fields is a function of the local electric field only. In
other words, the energy gained by a carrier after traveling a certain distance in a high-electric-field region is
typically calculated by assuming that the electric field is constant over that distance. Both these assumptions are
utilized in the “lucky-electron” model for hot-carrier injection. However, these assumptions break down in the
case of ultra-small geometry devices. In particular, Monte-Carlo simulations have shown that the high-energy tail
of hot carriers is non-Maxwellian in nature. Similarly, in aggressively scaled devices, the electric-field distribution
has a sharp peak near the drain region of the device. In such devices, the use of local electric fields to calculate
carrier heating will over-estimate the impact-generation rate. In this paper, the energy-balance equations have
been utilized to account for the non-Maxwellian nature of the carrier energy distribution as well as the “non-local”
nature of carrier heating. In brief, the energy-balance transport model provides continuity equations for the carrier
energies, and expresses the carrier mobilities and impact ionization rates as functions of the carrier energies rather
than the local electric field. During the simulation of hot-carrier degradation, we have solved the energy-balance
transport equations in silicon regions of the device to obtain a better approximation to the impact-generation rate
due to carrier heating.

3
2.3 Impact Generation Rate

The hot-carrier-injection flux into the oxide is a strong function of the rate of generation of electron-hole pairs
due to impact-ionization in silicon. Hence, in order to simulate hot-carrier injection, we need to accurately model
the impact-ionization process. As mentioned above, the use of energy-balance transport equations is essential for
this. In general, the generation rate associated with impact ionization has the form:

Jn Jp
G = αn + αp (1)
q q

where αn and αp are the electron and hole ionization coefficients. In the simulations reported here, impact
ionization in silicon due to channel hot carriers is simulated using the model proposed by Selberherr [16]. This
model accounts for carrier energy dependence of the impact generation rate by expressing the impact ionization
coefficients as functions of the carrier energy.

2.4 Hot-Carrier Injection

The hot-carrier-induced device degradation is caused by interaction between injected carriers and oxide defects.
The carrier-injection flux is a strong function of the device structure, applied biases, and the impact-generation
rate. Furthermore, the location and the magnitude of the injection flux determines the extent to which the carrier
trapping in the oxide will be observed as a shift in electrical characteristics of the device. It is needless to say
that the success of a hot-carrier modeling approach rests on the accurate modeling of the hot-carrier injection
currents.

The rate of carrier injection into the gate oxide is traditionally calculated using approaches based on the “lucky-
electron” model. As mentioned above, the use of the local electric field to calculate carrier energies can result
in over-estimation of carrier injection while using this model. A similar approach has been used by Schwerin and
Weber in [2] where they have used a modified form of the lucky-electron model to account of non-local carrier-
heating effects on the carrier injection current without using energy-balance equations. Such approaches calculate
the hot-carrier injection currents through post-processing of the simulated carrier and potential distributions. In
other words, the coupling between carrier injection and trapping in the oxide and the carrier transport and fields
in silicon is neglected. As mentioned above, we account for non-local carrier heating effects through the use of
energy-balance equations. Unlike previous approaches, in this work, we self-consistently solve the carrier transport
and trapping in the oxide as well as the carrier transport and impact ionization in silicon. The energy-balance
equations are used to obtain the carrier-energy distribution in silicon. The carrier injection from the semiconductor
into the oxide is calculated by imposing a thermionic boundary condition [13] at the Si-SiO2 interface.

2.5 Carrier Transport in the Oxide

The traditional approaches for modeling hot-carrier-induced device degradation utilize models for physical pro-
cesses occurring in the semiconductor regions of the device but provide no models for the transport of injected
carriers in the oxide or their interactions with defects in the oxide. Schwerin and Weber [2] have utilized drift-
diffusion equations to model carrier transport in the oxide. As mentioned above, they obtain the injection current
density using a modified lucky-electron model. Once the carrier-injection flux is obtained by post-processing the
simulation results in the semiconductor region of the device, they solve the carrier transport equations in the oxide
separately to obtain the carrier trapping rates. In other words, in their simulations Schwerin and Weber solve the
transport equations in the semiconductor and oxide separately assuming that the transport in the semiconductor
can be decoupled from the carrier transport in the oxide. Furthermore, they assume the injected current density
decays exponentially as a function of the distance from the Si-SiO2 interface without providing any physical basis
for this assumption. The “distance from the interface” used in calculating the exponential decay of the injected
current cannot be used for oxides with arbitrary (non-rectangular) shapes.

4
In this work, we have attempted to extend the conventional hot-carrier simulation approaches in a manner similar
to Schwerin and Weber but without making the assumptions listed above. As mentioned earlier, the carrier
injection flux is obtained by imposing a thermionic boundary condition at the Si-SiO2 interface. This allows us
to solve the carrier transport equations in the oxide and the semiconductor regions of the device simultaneously.
In our approach, the transport of injected carriers in the oxide is simulated by treating the oxide as a wide-
bandgap semiconductor with a bandgap of 9 eV. As carrier heating processes are relatively insignificant in the
oxide, the carrier transport in the oxide has been modeled using only the drift-diffusion equations. The values of
the electron and hole mobilities in the oxide have been estimated from the literature to be 20 cm2 /V − s [17]
and 10−15 cm2 /V − s [18] respectively. The injected carriers are assumed to be in quasi-equilibrium with the
local oxide electric field and hence conventional drift-diffusion equations are valid for the carriers in the oxide.
Finally, the self-consistent simulation of carrier transport in semiconductor and oxide regions of the device allows
us to eliminate the assumption that the injected current density decays exponentially inside the oxide as used by
Schwerin and Weber.

2.6 Electron Trapping

In general, the gate oxides of MOS devices have a significant amount of defects incorporated in them during the
fabrication process. These defects introduce energy levels in the bandgap of the oxide. The injected carriers can
get emitted from their corresponding conductive bands into these energy levels. The carriers which occupy such
energy states appear relatively immobile and can remain “trapped” in these states for long periods of time before
they are emitted back to the conductive bands. Thus, the trapped carriers appear as a fixed (i.e. immobile) charge
in the oxide. In the study of hot-carrier degradation, the defects which trap the carriers for the entire duration
of the experiment are of most concern. Hence, in our simulations we assume that a carrier that gets trapped at
a defect never gets emitted back. In the case of hot-carrier degradation in p-channel devices, for a given drain
bias, the worst-case gate bias condition corresponds to the bias which results in the maximum gate current. The
primary degradation mechanism under this bias condition has been shown to be the injection and trapping of
electrons into the gate oxide. This has also been verified experimentally for the devices for which results are
presented here. In the case of device of smaller geometries, other effects such as interface trap generation and
hole trapping may also need to be included.

In our simulations, we have approximated the rate of trapping of injected carriers using the expression:

dnt Jn
= σn (NTe − nt ) (2)
dt q

where, nt is the density of trapped electrons, σn is the average capture cross section of electrons at the defects,
Jn is the electron current density, q is the electronic charge, and NTe is the initial density of available defect
sites in the oxide. These defects have been assumed to be uniformly distributed throughout the oxide region.
The parameters NTe and σn were chosen to give the best fit to experimental data (NTe = 1.0 × 1019 /cm3 and
σn = 1.0 × 10−18 cm2 ). The values used in our simulations are consistent with those previously published in
independent reports [19, 20].

2.7 Effect of Trapped Charge on Channel Mobility

In order to compare the hot-carrier simulation results with experimental data, we need to simulate the effect
of trapped charge in the oxide on the device characteristics. The presence of fixed charge in the oxide can
significantly change the channel conductivity by affecting the mobility of carriers in the inversion layer. We have
utilized the model presented by Lombardi et al. [21] to estimate the channel mobility in the presence of trapped
charge in the oxide. The model parameters were adjusted to give the best fit between simulated and experimental
IDS -VGS characteristics before hot-carrier stress. The same parameters were used to simulated the post-stress
device characteristics.

5
3 Experimental

The simulation approach presented here has been calibrated and verified using hot-carrier stressing experiments
on p-channel SOI MOSFETs with L×W=0.8μm×50μm and a gate oxide thickness of 15 nm. The MOSFETs
were fabricated on SIMOX wafers with buried oxide thickness of 400 nm. The devices used for this study had
body contacts to control the body bias and monitor the body current during the stress.

Accelerated stress experiments on p-channel transistors show that the hot-carrier-induced device parameter shift
vs gate bias shift correlates well with the gate current [22]. In other words, for a given drain bias and stress period,
the largest parameter shift is observed at a gate-bias which results in the largest gate current. This criterion was
used to decide the stress biases during our experiments. All the hot-carrier stressing experiments were performed
at VDS =-10V and VGS =-0.8V for 3000 seconds. As mentioned above, this bias condition resulted in the maximum
gate current at VDS =-10V. The stress experiment was repeated on several devices from the same wafer. The
experimental results shown in this paper represent typical measurements. The same bias conditions were also
used during the device simulations.

4 Results

The experimental gate current IGS vs VGS plot in Fig. 2 shows that the maximum gate current occurs at a gate
bias of VGS =-0.8V for VDS =-10V. This bias condition was chosen for hot-carrier stressing. At this bias condition,
a large number of carriers are generated near the drain due to impact ionization. The simulated spatial distribution
of carrier energies is shown in Fig. 3 while the impact generation rate is shown in Fig. 4. Under the influence of
the local electric field the electrons move towards the gate while the holes are swept to the body. As the electrons
travel towards the gate oxide, they gain energy and localized electron injection into the oxide takes place near the
drain region of the device. The injected electron concentration in the gate oxide is shown in Fig. 5.

0.8
Ig/Igmax

0.6

0.4

0.2

0
0 -0.5 -1 -1.5 -2 -2.5 -3
VGS (V)

Figure 2: Experimental gate current vs gate voltage characteristics at a drain bias of -10 V. The gate currents
peaks at a gate bias of 0.8 V. This bias condition is used for the stress.

The volume density of trapped electrons in the oxide modeled using Eq. 2 is shown in Fig. 6. As expected, the
trapping is maximum near the region of maximum carrier injection into the oxide. Fig. 7 compares the potential
distribution under normal operating conditions of VGS =-5 V and VDS =-5 V before stress and after 3000s of stress.

6
 Gate
Electron Temperature (K)

1000

500

Source 200 Drain

Body Contact

Figure 3: Electron temperature in silicon during p-MOS stressing at VDS =-10 V and VGS =-0.8 V.

Gate
Impact Generation Rate (/s-cm3)

1024

1012

Source 10 Drain

Body Contact

Figure 4: Impact generation rate at stress bias, VDS =-10 V and VGS =-0.8 V.

7
 Injected Electron Density (/cm3)

1010

105

100

LDD

Figure 5: The concentration of injected electrons in the oxide after 3000s of stress.

It clearly shows the effect of the trapped electrons in the oxide on the potential distribution under normal operating
conditions. Fig. 8 compares the effective trapped electron density at different points along the channel at different
stress times. This is calculated by converting the volume density of trapped electrons shown in Fig. 6 into an areal
density at each point along the interface from source to drain. The areal density is calculated by weighting the
volume density of charge at a particular grid point in the oxide with the ratio of the distance of that point from
the gate terminal and the thickness of the gate oxide. It clearly shows the localized charge distribution of negative
charge increasing in density as we move from source to drain as well as the saturation of the trapped electron
density close to the drain. This saturation behavior is expected as all the available traps become completely filled
with electrons. This result compares well with the trends shown by Schwerin and Weber in [2].

The pre- and post-stress drain currents are shown as functions of the gate bias at a drain bias of -0.1 V in Fig. 9,
showing an increase in the current after stress. This figure shows both experimental data and simulated results,
which are in excellent agreement. The increase in the current can be explained as a result of the localized lowering
of the threshold voltage due to the trapped electrons in the oxide. Fig. 10 shows a plot of the experimental and
simulated relative transconductance change with respect to the initial transconductance as a function of the stress
time. The increase in the transconductance is due to an apparent channel shortening as a result of the negative
charge in the gate oxide. The simulation results agree closely with the experimental data. The parameter shift
due to electron trapping in pMOS devices is known to have a linear time dependence on a semi-log plot[8, 23].
A physical model for this dependence can be found in [23]. As can be seen from Fig. 10, our simulation results
(as well as experimental results) correctly predict this linear dependence.

5 Conclusions

A novel hot-carrier modeling approach based on self-consistent solution of semiconductor energy-balance equations
and carrier transport and trapping in the gate oxide has been successfully applied to simulate hot-carrier response
of p-MOS SOI MOSFETs. In this work, we validated our approach using devices with relatively large channel
lengths; however, the reduced empiricism in this approach makes it particularly applicable to ultra-small geometry
devices where conventional hot-carrier modeling approaches break down. The approach has been implemented in
a commercial TCAD toolset which makes it suitable for technology optimization for hot-carrier reliability.

8
 Trapped Electron Density (/cm3)

1018

1015

1010

LDD

Figure 6: Trapped electron density in the oxide after 3000s of stress. Maximum electron injection occurs above
the region of maximum impact generation in Fig. 4.

6 Acknowledgements

The authors would like to thank Randall J. Milanowski and Chris Nicklaw from Dynamics Research Corpora-
tion (San Diego), Eugene Kelley from the United States Space and Naval Warfare Systems Command (San
Diego), and Lloyd Massengill from Vanderbilt University for their contribution to this work. We would also like
to thank John Hutson and Tamera Anderson for their help with the experiments.

References
[1] A. Schwerin, W. Hansch, and W. Weber, “The Relationship Between Oxide Charge and Device Degradation:
A Comparative Study of n- and p-Channel MOSFETs,” IEEE Transactions on Electron Devices, vol. 34, pp.
2493, 1987. 1

[2] A. Schwerin and W. Weber, “2-D Simulation of p-MOSFET Hot-Carrier Degradation,” Microelectronic
Engineering, vol. 28, pp. 277–284, 1995. 1, 4, 8

[3] Paul Heremans, Rudi Bellens, Guido Groeseneken, and Herman E. Maes, “Consistent Model for the Hot-
Carrier Degradation in n-Channel and p-Channel MOSFET’s,” IEEE Transactions on Electron Devices, vol.
35, no. 12, pp. 2194–2209, December 1988. 1

[4] E. Takeda, C. Y. Yang, and A. Miura-Hamada, Hot-Carrier Effects in MOS Devices, Academic Press, San
Diego, 1995. 1

[5] Simon Tam, Ping-Keung Ko, and Chenming Hu, “Lucky-Electron Model of Channel Hot-Electron Injection
in MOSFET’s,” IEEE Transactions on Electron Device, vol. ED-31, no. 9, pp. 1116–1125, September 1984.
1

[6] Chenming Hu, Simon C. Tam, Fu-Chieh Hsu, Ping-Keung Ko, Tung-Yi Chan, and Kyle W. Terrill, “Hot-
Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement,” IEEE Transactions on Electron
Devices, vol. ED-32, no. 2, pp. 375–384, February 1985. 1

9
 -1.1
Potential (V)

-1.0 5.91

3.94
-0.9
1.97

0.0
-0.8

-0.7

-0.6

-0.5

-0.4
5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2

(a) Before stress.

-1.1
Potential (V)

-1.0 5.91

3.94
-0.9
1.97

0.0
-0.8

-0.7

-0.6

-0.5

-0.4
5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2

(b) After stress.

Figure 7: Potential distribution in the device under normal operating conditions of VGS =-5 V and VDS =-5 V
before and after 3000s of stress.

10
 8
1s

Trapped electron density (x1012 /cm2)

7 500s
3000s
6

0
6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8
X (µ m)

Figure 8: Effective trapped electron density as a function of lateral position.The trapped charge after 1s, 500s,
and 3000s of stress are shown. X increases from source to drain (see scale in Fig. 7).

14

12
Drain Current (A/ m)

10

4 Pre-Stress Simulation
Pre-Stress Experiment
2 Post-Stress Simulation
Post-Stress Experiment

0
0 -1 -2 -3 -4 -5 -6
Gate Bias (V)

Figure 9: Drain current vs gate voltage before and after 3000s of stress. Drain currents are measured at a drain
bias of -0.1 V with the gate voltage swept from 0 V to -5 V. Experimental data are shown as dots and the
simulation results are shown as lines.

11
 0.24

0.2

0.16

Gm/Gm0
0.12

0.08

0.04 Experiment
Simulation
0
1 10 100 1000 10000
Stress Time (s)

Figure 10: The relative change in the transconductance with respect to the initial transconductance as a function
of stress time.

[7] E. Takeda and N. Suzuki, “An Empirical Model for Device Degradation Due to Hot-Carrier Injection,” IEEE
Electron Device Letters, vol. EDL-4, no. 4, pp. 111–113, April 1983. 1

[8] Martin Brox, E. Wohlrab, and Werner Weber, “A Physical Lifetime Prediction Method for Hot-Carrier-
Stressed p-MOS Transistors,” Proc. IEDM, pp. 525–528, 1991. 1, 8

[9] A. Duncan, U. Ravaioli, and J. Jakumeit, “Full-Band Monte-Carlo Investigation of Hot-Carrier Trends in
the Scaling of Metal-Oxide-Semiconductor Field-Effect Transistors,” IEEE Transactions on Electron Devices,
vol. 45, no. 4, pp. 867–876, Apr. 1998. 1

[10] S. L. Wang, N. Goldsman, Q. Lin, and J. Frey, “Rely: A Physics-Based CAD Tool for Predicting Time-
Dependent Hot-Electron Induced Degradation in MOSFETs,” Solid-State Electronics, vol. 36, pp. 833, 1993.
1

[11] Wilfried Hansch and Siegfried Selberherr, “MINIMOS 3: A MOSFET Simulator that Includes Energy Bal-
ance,” IEEE Transactions on Electron Devices, vol. ED-34, no. 5, pp. 1074–1078, May 1987. 2

[12] W. Hansch and M. M. Mattausch, “The Hot-Electron Problem in Small Semiconductor Devices,” Journal
of Applied Physics, vol. 60, pp. 650, 1986. 2

[13] Dietmar Schroeder, Modelling of Interface Carrier Transport for Device Simulation, Springer-Verlag, 1994.
2, 4

[14] SILVACO International, ATHENA User’s Manual, 2D Process Simulation Software, 1998. 2

[15] SILVACO International, ATLAS User’s Manual, Device Simulation Software, 1998. 3

[16] S. Selberherr, Analysis and Simulation of Semiconductor Devices, Springer-Verlag, New York, 1984. 4

[17] R. C. Hughes, E. P. EerNisse, and H. J. Stein, “Hole Transport in MOS Oxides,” IEEE Transactions on
Nuclear Science, vol. 22, pp. 2227, 1975. 5

[18] R. C. Hughes, “Time-Resolved Hole Transport in a-SiO2 ,” Physical Review B, vol. 15, no. 4, pp. 2012–2020,
15 February 1977. 5

12
[19] J. M. Aitken, D. R. Young, and K. Pan, “Electron Trapping in Electron-Beam Irradiated SiO2 ,” Journal of
Applied Physics, vol. 49, pp. 3386, 1978. 5

[20] J. F. Conley, Jr, P. M. Lenahan, and B. D. Wallace, “Electron Spin Resonance Characterization of Trapping
Centers in Unibond Buried Oxides,” IEEE Transactions on Nuclear Science, vol. 43, no. 6, pp. 2635–2638,
December 1996. 5
[21] C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “A Physically Based Mobility Model for Numerical
Simulation of Nonplanar Devices,” IEEE Transactions on Computer-Aided Design, vol. 7, pp. 1164, 1988.
5

[22] T. C. Ong, K. Seki, P. K. Ko, and C. Hu, “Hot-Carrier-Induced Degradation in p-MOSFETs Under AC
Stress,” IEEE Electron Device Letters, vol. 9, pp. 211, 1988. 6
[23] Qin Wang, Martin Brox, Wolfgang H. Krautschneider, and Werner Weber, “Explanation and Model for the
Logarithmic Time Dependence of p-MOSFET Degradation,” IEEE Electron Device Letters, vol. 12, no. 5,
pp. 218–220, May 1991. 8

13