This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2562112, IEEE Journal
of Emerging and Selected Topics in Power Electronics
JESTPE-2016-01-0031 1

Design and Application of High Voltage SiC

JFET and its power modules
Sizhe Chen, Ao liu, Junwei He, Song Bai, and Kuang Sheng, Senior Member, IEEE

 work at a higher voltage level with acceptable on-state

Abstract—This paper presents structure design, prototype resistance. On the other hand, with no minority carrier
development and testing of high voltage SiC TI-VJFETs. Key injections, high voltage SiC unipolar devices, e.g. MOSFETs
design factors, including drift layer doping concentration and and JFETs can work at a much higher frequency and the volume
thickness, channel dimensions and termination structures are
of system’s passive component will be reduced. The current
studied with numerical simulations. Devices are then fabricated in
our research level facilities. The fabricated device has an active capacity of unipolar device is relatively low. But high current
region of 4mm2 and can conduct a current of 2.8A at drain voltage can readily be achieved with larger chip size or by paralleling
of 3V and gate bias of 2.9V. With a negative gate bias of -5V, the more chips in a power module.
breakdown voltage is over 4500V. Based on these devices, two Compared with MOSFET or other device structures, SiC
modules are designed and developed. One is a 4500V/50A SiC JFET has unique properties. Having no gate oxide concerns, it
JFET power module. The other one is an all-SiC power module
can fully benefit from the superior properties of SiC material.
with SiC JFETs and SiC JBS diodes. And the second one is also
evaluated in a high frequency boost converter. Testing results For example, with a dedicated package, SiC JFET can work at
show that this All-SiC module is capable of working at a an extremely high ambient temperature of 450°C [10]. In
frequency up to 100kHz with both turn-on and turn-off time less general, SiC JFET structures can be divided into two
than 150ns. A high converter efficiency of 97% is obtained at categories, namely lateral channel structure [11] and vertical
50kHz switching frequency and the efficiency is 95% at switching channel structure [8] [12]. However, the former one usually
frequency of 100kHz. This work demonstrates that SiC JFET and
needs epitaxial regrowth technology which is beyond
its power module can be used for SiC device applications in
medium voltage range. capabilities of many research facilities. On the other hand,
vertical channel JFET structure shows great potentials in
Index Terms—Silicon carbide, JFETs, Multichip modules obtaining low specific-on resistance and large drain current.
For example, a record low resistance of 2.8mΩcm2 with 1900V
blocking voltage is reported in [13]. And very large area
I. INTRODUCTION devices with high output current have also been reported in
[14]-[16]. For extremely high voltages, the first 10kV SiC JFET
W ith wide bandgap, high thermal conductivity, and large
critical electrical field, Silicon carbide (SiC) have been
widely recognized as an ideal material for next generation
is reported in [17] and a large area high voltage device up to
9kV are introduced in [18].
power semiconductors [1] [2]. Compared with other wide Apart from device structures, some research works are
bandgap materials, such as gallium nitride (GaN) or diamond, focused on SiC JFET based power modules and power
SiC has the most mature material quality and fabrication converters [19]-[21]. In [20], a SiC JFET based three phase
technology. Numerous SiC power devices has been PWM rectifier was tested at an ambient temperature above
demonstrated, such as SBDs, MOSFETs, JFETs and BJTs 100°C. And in [21], a 1200V, 100A three-phase power module
[3]-[9] and some of them have been introduced to commercial based on SiC JFETs was developed. And a three-phase inverter
market. based on this module was also introduced.
Although its present target market is at 600V to 1200V, SiC However, among these publications, few works are focused
power device is also expected to replace Si IGBTs in medium on SiC JFETs at medium voltage range. And there are even
voltage range (from 3.3kV to 6.5kV). On one hand, high critical fewer studies on power modules and their applications with
electric field in SiC material allows power devices to be medium voltage SiC JFETs. In this paper, device design and
fabricated with very thin drift layers. So unipolar device can prototype development of 4.5kV SiC JFETs is introduced. With
fabricated devices, two SiC JFET based power module are
Manuscript received January 10, 2016; revised March 21, 2016; accepted developed. One is a SiC JFET power module with the power
April 14, 2016. This work was supported by the National High Technology rating of 4500V, 50A and the other one is an integrated all-SiC
Research and Development Program of China (863 Program)
(No.2011AA050401) and National Science Fund for Distinguished Young
power module based on SiC JFETs and SiC JBS diodes. With
Scholars (No. 51225701). the second module, a kW-level boost converter is demonstrated
S. Chen, J. He, and K. Sheng are with the College of Electrical Engineering, in this work. The present paper is organized as follows: Section
Zhejiang University, Hangzhou, China (e-mail: chensizhe@zju.edu.cn;
hejunwei@zju.edu.cn; shengk@zju.edu.cn).
II describes the device design of SiC JFET, with both active
A. Liu and S. Bai are with Nanjing Electronic Devices Institute, Nanjing, region and termination structure designs; Section III presents
China (e-mail: wsygdhra@126.com; 13809020747@163.com).

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2562112, IEEE Journal
of Emerging and Selected Topics in Power Electronics
JESTPE-2016-01-0031 2

Fig. 2. Simulated transfer characteristics of TI-VJFETs with different channel

doping concentrations. The drain voltage keeps at 5V in the simulation.
Fig. 1. Schematic cross-sectional view of TI-VJFET unit cell.
the device fabrication processes and in-situ device doping concentration (Nch) and channel length (Lch). They are
characterization; The 4500V/50A SiC JFET power module, studied and verified by numerical simulations.
including module assembly and characterization is shown in B. Channel width and doping concentration
Section IV; Section V introduces the integrated power module
The channel width and channel doping concentration control
and the DC-DC converter based on it; And finally Section VI
both the on-state and off-state performance. With wider channel
gives conclusion. Part of the work in Section V has been
opening or higher doping concentration, the threshold voltage
reported in [22].
decreases, but the saturation current density will increase. In
device design, channel doping concentration is usually
II. DEVICE DESIGN AND SIMULATION
A. Device structure
The trenched-and-implanted vertical JFET (TI-VJFET)
structure [8], shown in Fig. 1 is used as the device structure in
this work. With no requirement of epitaxial regrowth or critical
lithography alignment, this structure is simple to fabricate and
can achieve a high current density. By fine adjusting the
channel width, devices can readily be either normally-on or
normally-off, showing great convenience in device design and
fabrication. Compared with normally-on device, normally-off
device usually has lower current conducting capability and high
specific on-resistance due to strong gate-depletion-region
overlap [23]. It should be mentioned that in order to obtain both
high current density and normally-off performance, a lot of
cascode configurations have been put forward based on
normally-on JFETs and low voltage normally-off devices
[24]–[26]. But this is beyond the topic of the present paper.
TI-VJFET structure typically consists three n-type epitaxial
layers, including one heavily doped layer on the top, one
channel layer in the middle and one lightly dope layer at the
bottom. The top heavily doped layer (n++ layer) is used to form
source ohmic contact and provide process margin for
ion-implantation. The middle n-type layer (channel layer) is for
the vertical channel region. And the lightly doped bottom layer
(n- drift layer) is used to support high voltages. In this work, the
device drift layer thickness is 50m and its doping
concentration is 1.71015cm‐3. Based on numerical simulations,
the ideal breakdown voltage of this drift layer is about 6.5kV.
P-type regions in Fig. 1 are formed by vertical and tilted Fig. 3. Simulated (a) output characteristics and (b) transfer characteristics of
aluminum ion-implantations. And other design parameters of TI-VJFETs with different channel widths. The output curves are simulated
TI-VJFET include vertical channel opening (Wch), channel with a gate bias of 2.6V, and the transfer curves are simulated with a drain
voltage of 5V. The dash line indicates power density of 200W/cm2.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2562112, IEEE Journal
of Emerging and Selected Topics in Power Electronics
JESTPE-2016-01-0031 3

determined first for two reasons. One is that this is a material

property and will not be changed when SiC wafer is ordered.
However, channel width is more flexible and can be adjusted
accordingly with mesa width during device fabrication.
Second, for devices with breakdown voltage higher than
4000V, the conduction resistance is dominant by drift layer.
And the channel doping concentration only controls gate
threshold voltage. Fig. 2 shows the simulated transfer curves
with different Nch. The channel length is set to be 2.1m and
channel width is 1.1m. In simulations, when Nch increases
from 51015cm-3 to 91015cm-3, the threshold voltage drops to
0.1V from 1.3V. Since the threshold voltage is designed to be
around 1V, channel concentration is set to be 71015cm-3.
The effect of channel width is studied when channel doping
concentration is fixed. In device simulation, Wch changes from Fig. 5. Short channel effects in TI-VJFETs with different channel lengths and
0.8μm to 1.2μm and the channel length keeps at 1.8μm. The different gate bias conditions.
results are shown in Fig. 3. Fig. 3(a) shows the output
characteristics by simulation. The dash line indicates the power increases to 1.2μm, the device shows normally-on
dissipation limit of 200W/cm2. As it is discussed above, due to performance. To have a threshold voltage of 1V, the channel
relatively thick drift layer, the conducting current is not width is designed to be 1μm.
sensitive to the channel openings. By increasing the channel C. Channel length and short channel effect
opening, the conducting current changes a little. However, in The device performance with different channel length is also
contrast to output performance, the device transfer curves in studied. Fig. 4(a) shows the simulated output characteristics of
Fig. 3(b) are highly depend on channel width. When Wch TI-VJFETs with different length. And fig 4(b) shows their
transfer characteristics. Compared with channel width and
doping concentration, different channel lengths do not have
obvious influence on device performance. For example, by
decreasing channel length from 2.1m to 1.5m, the threshold
voltage only decreases by 0.2V. In practice, larger channel and
deep trenches also bring more challenges in device
manufacturing.
It needs to be mentioned that although the channel length has
little effect on device conduction performance, a long channel,
normally longer than 1.2m is necessary for TI-VJFET
structure. This is mainly because longer channel brings better
blocking performance. When channel is short, the potential
barrier established by reserve gate bias only extends a short
vertical distance. As drain voltage increases, the drain potential
will penetrate into the channel and lower the potential barrier.

Fig. 4. Simulated (a) output characteristics and (b) transfer characteristics of

TI-VJFETs with different channel lengths. The output curves are simulated
with a gate bias of 2.6V, and the transfer curves are simulated with a drain Fig. 6. Surface electric field and potential distribution of the floating guard
voltage of 5V. The dash line indicates power density of 200W/cm2. ring termination structure.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2562112, IEEE Journal
of Emerging and Selected Topics in Power Electronics
JESTPE-2016-01-0031 4

And electron injection can occur. This situation is clearly ion-implantations. Tilted implantations are used to form
shown in Fig. 5. With zero gate bias, all three devices with vertical PN junctions on the channel sidewalls. And normal
different channel lengths lose their voltage blocking implantations are used to form high voltage blocking junctions
capabilities. And even with the gate bias of -10V, the device and surface P++ regions for gate ohmic contact. For termination
with 0.8m channel length still presents a clear pre-breakdown structures, P+ rings are formed simultaneously in the same
characteristic. implantation process. After ion-implantations, sample wafer is
cleaned thoroughly and annealed at 1600C for 30min to
D. Termination structure
activate the implanted Al atoms. And the high temperature
Floating guard ring structure is used as the edge termination annealing process is protected in Argon atmosphere. Fig. 8
to achieve designed blocking voltage. This method is used for shows the implanted Al profile from SIMS analysis after post
two reasons. First, floating guard ring structure is compatible annealing process.
with our device fabrication process and no additional mask or
etching step is needed. Second, compared with junction
termination extension or other methods, this structure is shown
to be more robust and less sensitive with wafer doping
concentration and process variations [27].
To obtain a breakdown voltage up to 6kV, more than 50 rings
are used in present design. Fig. 6 shows the simulated electric
and potential distribution at the surface. To have a balanced
electric field, the spacing between adjunct rings gradually
becomes smaller from outer rings to inner rings [28].

III. DEVICE FABRICATION

Based on above numerical simulations, 4H-SiC wafers with
three N-doped epi-layers are specially ordered for device
fabrication. The fabrication process begins with trench etching Fig. 8. Al profile of implanted layer after annealing from SIMS analysis.
on SiC surface. Reactive ion etching (RIE) method is used to
The surface passivation is accomplished by a 1.5 hour wet
form these deep trenches. The etching depth is about 4μm. And
oxidation at 1150C, followed by a 200nm PECVD Si3N4 and
metal mask, mainly consisted of nickel is used as etching mask.
SiO2 layer. The passivation layer is then re-opened at active
Although the channel length is only about 2μm, the other 2μm
region and nickel metal is sputtered for source and gate
channel above it is reserved for ion-implantation margin and
contacts. Rapid thermal annealing (RTA) process is used to
transition region from top N++ layer to P++ region to prevent
form a good ohmic contact. Fig. 9 shows the SEM picture of the
gate early breakdown. The mesa line width is around 2μm. So
mesa structure after gate and source contacts formation. The
the channel is left to be 1μm width after sidewall
drain contact on the backside is also formed by RTA process but
ion-implantations. Fig. 7 is a SEM picture of the cross section
with a tri-layer metallization of Ti/Ni/Ag. The Ag layer is
view of the mesa and trench structures on SiC surface. The
needed since it can prevent Ni metal from oxidation during the
roughness on its cross section is mainly caused by sample
annealing process.
preparation for the SEM observation.
Finally, a dielectric material, e.g. polyimide is spin-coated on
The P+ regions in mesa sidewalls and trench bottoms in Fig.
the sample to fill the trenches and provide isolation of gate
1 are formed by multiple normal and tilted Al
electrodes and source electrodes. The polyimide layer is then

Fig. 9. SEM photograph of the mesa structure after gate and source contacts
Fig. 7. Cross-sectional view of the mesa and trench structures on SiC surface.
formation.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2562112, IEEE Journal
of Emerging and Selected Topics in Power Electronics
JESTPE-2016-01-0031 5

Fig. 12. Breakdown curve of single TI-VJFET with gate bias of -5V.
Fig. 10. Optical photograph of a JFET die after device fabrication. induced resistance. The wafer substrate has a specific resistance
etched back until the mesa tops are exposed. And a thick Al of 0.54mΩcm2 based on its specifications. The wafer drift layer
metal of 3.5μm is deposited and patterned by wet etching to is about 50μm in thickness and the doping concentration is
form the source pad and gate overlay pad. Fig. 10 shows the 1.7×1015cm-3. Assuming an electron mobility of 750cm2/Vs, it
optical picture of one single TI-VJFET chip after device has a specific resistance of 16.5mΩcm2. So the resistance of the
fabrication. The chip has been diced from SiC wafer and remaining two parts, namely channel resistance and that
soldered on a copper substrate. induced by process is 11.5mΩcm2. Due to process variations
Static performance is measured with Tektronix 371A curve and relatively conservative device design, the channel
tracer and a home built high voltage testing set-up. Fig. 11 resistance is believed to be larger than expected. High channel
shows the output characteristics of one device. The device’s resistance is mainly because the actual current conducting path
threshold voltage is around 1V. With the gate voltage of 2.5V, (Wch in Fig.1 minus two depletion width on both sides) is
drain current is 1A at the drain voltage of 4V, whereas it narrow in this device. This is especially true for normally-off
increases to over 3A when gate voltage is increased to 2.9V. JFET in which the channel has to be narrow enough to have a
Gate current is also measured at different gate bias. At the gate good pinch-off capability at the off state. Fig. 12 shows the
voltage of 2.9V, gate current is about 30mA. Considering that blocking capability of the same device in Fig. 11. It is noted that
the drain current is over 3A, the current gain is over 100 at this this device has a relatively low leakage current. Although this
bias condition. And at the gate voltage of 2.5V, gate current is device show a normally-off performance in forward
0.26mA and the current gain increases to about 3800. As for the characteristics, a negative gate voltage is necessary to
device on-resistance, at drain voltage of 1V, the chip resistance guarantee pinch-off the gate channel. At off-state, the gate bias
is 1.6Ω when gate voltage is 2.5V. And it decreases to 0.71Ω is kept at -5V and the device has a low leakage current density
when gate voltage is increased to 2.9V. Considering that the of 0.15mA/cm2 at the drain voltage of 4500V. If we adopt
active area is about 4mm2, the device has a specific 0.1mA/cm2 as the metric to define breakdown voltage, this
on-resistance of 28.5mΩcm2 when gate voltage is 2.9V. This tested device has a breakdown voltage of 4300V in above bias
resistance can be split into three main parts, including wafer condition.
intrinsic resistance, device channel resistance and process
IV. DEVELOPMENT OF 4500V/50A SIC JFET MODULE
A. Module Design and fabrication
To increase the current capacity, multiple JFET chips are
parallel-connected and packaged in a power module. Taking the
device in Fig. 11 as an example, it can conduct a current of 2.8A
with drain voltage of 3V and gate voltage of 2.9V. Giving
enough design margins, 22 chips are used to obtain a current
rating of 50A. As for the module design, a relatively thick
alumina nitride (AlN) ceramic of 0.63mm is chosen to provide
enough voltage blocking capability. The copper layer has a
thickness of 0.3mm and the separation between different
copper islands is designed to be 2mm, other than 1mm normally
seen in low voltage power module.
The standard 62mm×108mm module is used in this work. It
has two independent DBC substrates and they are connected by
Fig. 11. Output characteristics of single TI-VJFET device. bonding wires in the module. Fig. 13 shows one of the DBCs

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of Emerging and Selected Topics in Power Electronics
JESTPE-2016-01-0031 6

Fig. 15. Breakdown performance of 19 TI-VJFET devices in parallel.

Fig. 13. DBC substrate and the SiC JFET chips on it after soldering and wire
bonding. a current of 50A when the drain voltage is 4.5V. Fig. 15 shows
after device soldering and wire bonding. A two-step soldering the blocking characteristics of this module. With a gate bias of
process is used here. First, devices are soldered onto DBC -20V, the module has a breakdown voltage over 4500V.
substrates at a relatively high temperature. Ultrasonic wire Comparing against Fig. 12, it is observed that the leakage
bonding is then used to provide connections between devices current curve of this 19-chip-paralleled module is somewhat
and devices to DBC substrate. After devices are connected, different from that of a single chip. This is because of the
static tests, especially voltage blocking tests are conducted to difficulties in achieving highly uniform JFET channel opening
verify if the devices are fully functional. In present module, across a whole wafer. And this will leads to different leakage
only 19 chips are still working after the first soldering and wire currents for different chips even on the same wafer.
bonding. After screening, the DBC is soldered onto a thick Cu
substrate at a lower temperature to finish the module V. DEVELOPMENT OF FULL-SIC POWER MODULE AND ITS
fabrication. Special attentions have to be paid to the chips’ APPLICATIONS
positions on the DBC substrate due to the safety and thermal A. Module Design and fabrication
considerations. Based on simulations with ANSYS software, Along with SiC TI-VJFETs, 4500V rating SiC junction
the thermal resistance of junction-to-case is 1.25K/W in our barrier diode (JBS) is also fabricated. The device design and
design, presenting good thermal performance. fabrication process is similar with [6]. The active area of SiC
B. Static characterization JBS is 9mm2. The conducting current is about 4A at the anode
Both forward and blocking performance are characterized bias of 3V. With both SiC JFETs and SiC JBS diodes, an all-SiC
with the fabricated module. The forward performance is integrated power module is developed. Four JFET chips and
measured by the high power curve tracer (Tektronix 371A) and four JBS chips are first parallel connected. And they are
the blocking characteristics are measured by a self-built high connected in series in the module. The module design and
voltage testing platform. Fig. 14 shows module’s output fabrication process is similar with above JFET module.
characteristics. Since 19 chips are packaged in the module, B. Static and switching characteristics
current characterization mode is used to provide enough Both static and switching tests are performed with this
driving capability. With a gate current of 500mA, module. In static state, the JFET leg and SBD leg in module are
corresponding to gate voltage of 2.7V, the module can conduct tested separately. In dynamic testing, the switching
performance is evaluated by a double-pulse test. The JFET leg
works as the switching device, and the SBD leg works as its
freewheeling diode.
Fig. 16 shows the forward characteristics of the SBD leg and
the JFET leg in the module. As it is shown, four SiC SBDs have
a large conduction current over 20A at the anode voltage of 3V,
whereas four JFETs can only conduct 13A at the same drain
voltage and the gate bias of 3V. Increasing gate bias would
increase the conduction current. However, since SiC JFET is a
p-n junction controlled device, a gate bias larger than 3V will
lead to an obvious gate current, thus increasing the gate losses.
Based on our measurement, the gate current of these
four-paralleled JFETs is about 1mA when gate voltage is 2.5V.
However, it increases to 160mA when gate voltage is 3V.
Fig. 14. Output characteristics of 19 TI-VJFET devices in parallel. Compared with SiC JFETs, the schottky diodes have a larger

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2562112, IEEE Journal
of Emerging and Selected Topics in Power Electronics
JESTPE-2016-01-0031 7

Fig. 16. Forward characteristics of diode leg and JFET leg in the module.
Each leg has 4 chips in parallel.

Fig. 18. Switching waveforms of the fabricated module in the double pulse
test. (a) Turn-on waveform, (b) Turn-off waveform.
Fig. 17. Blocking characteristics of diode leg and JFET leg in the module.
Each leg has 4 chips in parallel. Fig. 18 shows the turn-on and turn-off waveforms
on-state current. On one hand, the active area of SiC SBD respectively. As it is shown, the turn-on time of this module is
(3mm×3mm) is bigger than that of SiC JFET (1.8mm×2.2mm). 140ns, whereas the turn-off time is about 100ns. These results
On the other hand, as it’s shown in Section III, the presence of a indicate that the fabricate module has desired forward, blocking
long and narrow channel in JFET structure will lead to a and fast switching capabilities and can be used for high voltage
relatively large specific on-resistance. and high frequency applications.
The blocking performance of the fabricated module is shown C. DC-DC converter based on full-SiC power module
in Fig. 17. It is shown that the diode leg have a blocking voltage
Inspired by the good switching capability, a prototype boost
of about 4kV with a leakage current density of 0.8mA/cm2. And
converter is developed to fully demonstrate the potential of the
the JFET leg can support a drain voltage of 3500V before
SiC module. The boost converter is selected because of its
avalanche breakdown. And the leakage current density is about
simplicity and versatility in power conversion systems. And
0.5mA/cm2. It is noted that the JFETs used in this module are
SiC JFET leg works as the switching device and the SBD leg
fabricated in a different batch. Compared with previous results,
works as the diode in the circuit.
the device breakdown voltage appears to be lower. As for SiC
SBDs, although they seem to be leaky, the leakage current
density (0.83mA/cm2) actually remains at a relatively low level
with reverse voltage of 4000V.
The module’s dynamic performance is evaluated with a
double-pulse test circuit. The load inductor is 1.32mH and the
test is under 1800V dc bus voltage and 8A load current.
Considering the gate pinch-off voltage and forward conduction
voltage, 5V is chosen for turn-on and -20V is used for turn-off
for the gate voltage. A high gate turn-on voltage is used to
increase turn-on speed of JFET. And at static state, the gate
Fig. 19. The kW-level boost converter circuit based on fabricated full-SiC
voltage is pinched at around 3V. power module with gate drive schematic.

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Fig. 19 shows the schematic diagram of converter circuit and

the JFET gate drive circuit. Compared with Si IGBT, SiC
MOSFET or other counterpart, one of the main drawbacks of
SiC JFETs is that they are not easy to drive. At the off-state, a
negative gate bias is always needed to make sure that the device
channel is fully depleted. And in the conduction state, the gate
voltage should be no larger than the gate turn on voltage since it
will lead to non-negligible gate current. However, these issues
can be addressed by specially designed drive circuit [29]-[32].
In this work, a resistor-capacitor-diode (RCD) network, first
proposed in [29] is adopted as the drive circuit. This driving
topology is then largely used for normally-on JFET devices
[21] [30]. In this work, a resistor Rp of 100kΩ, a capacitor Cp of
100nF and a diode Dp are used in this network. And a gate
resistor, Rg is also serially connected in the circuit. Two Fig. 21 System efficiency of the converter at different working frequencies.
working conditions are considered here. First, during the
off-state, if the supply voltage is more negative than the gate The boost converter is working at continuous conduction
reverse avalanche voltage, the leakage current of the gate is mode (CCM) in both 50kHz and 100kHz. A high voltage DC
limited by resistor Rp and it is therefore impossible to drive the source is used as the power supply and a set of power resistors
gate to avalanche. Second, during the on-state, a positive is used as the circuit load. By either condition, the circuit duty
current peak is supplied by Cp to charge gate-source cycle is kept at 0.62.
capacitance and a fast turn-on process is achieved. The drive IC Fig. 20 shows the system losses break down in both 50kHz
used in this work is IXDN609. An ADUM5241 chip (not and 100kHz cases. In Fig. 20, apart from the other losses
depicted in this diagram) is used to provide isolated voltage coming from the system passive components, the switching
source for the gate driver IC. loss is the dominate part in the system loss. And it generally
increases with higher system power. Compared with the case of
50kHz, it even takes a larger part when switching frequency is
increased to 100kHz. The system efficiency is also evaluated
under different working conditions and presented in Fig. 21.
With the frequency of 50kHz, the system efficiency is increased
from 93.92% to 97.05% with different system power from
800W to 2400W by changing load resistance. And for the case
of 100kHz, the system efficiency is a littler lower due to large
switching losses and the system have a highest efficiency of
95.4%.

VI. CONCLUSIONS
In summary, this paper demonstrates the design and
development of high voltage SiC TI-VJFETs. The device
design on both active region and termination structure are
studied with numerous numerical simulations. And some key
fabrication steps are introduced. Different batches of SiC JFETs
are fabricated in our facilities and then tested. For a single
device, the active region is 4mm2 and the conducting current is
about 2.8A at the drain voltage of 3V. And the breakdown
voltage is over 4500V with a negative gate bias of -5V. Two
power modules are developed with SiC JFETs. One has a power
rating of 4500V/50A. And the other is an integrated SiC power
module based on both SiC JFETs and JBS diodes. And this
module is also evaluated by a high frequency boost converter.
The result shows that it is capable of working at a frequency up
to 100kHz. This work demonstrates that SiC JFET and its
power module can be used for SiC device applications in the
medium voltage range.

Fig. 20. Loss analysis of the boost converter in (a) 50kHz and (b) 100kHz
switching frequency.

2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2562112, IEEE Journal
of Emerging and Selected Topics in Power Electronics
JESTPE-2016-01-0031 9

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2168-6777 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2016.2562112, IEEE Journal
of Emerging and Selected Topics in Power Electronics
JESTPE-2016-01-0031 10

Junwei He received the B.S. degree and the

M.S. degree in power electronics from
Zhejiang University, Hangzhou, China, in
2012 and 2015, respectively.
His research interests include Testing and
packaging technologies of SiC power device
and SiC power device application.

Song Bai has been with the SiC device

group at Nanjing Electronic Devices
Institute since 2004. Currently he heads
research on SiC power device development
at State Key Laboratory of Wide-Bandgap
Semiconductor Power Electronic Devices.
He earned a PhD degree in physics from the
University of Pittsburgh in 2003 for his
doctoral work on the characterization of SiC. He is the author or
co-author of over 20 publications and holds seven patents.

Kuang Sheng (M’99–SM’08) received the

B.Sc. degree in electrical engineering from
Zhejiang University, Hangzhou, China, in
1995, and the Ph.D. degree in electrical
engineering from Heriot-Watt University,
Edinburgh, U.K., in 1999. He was a
Postdoctoral Research Associate at
Cambridge University, Cambridge, U.K.,
between 1999 and 2002.
He was at Rutgers University, New Brunswick, NJ, where he
was an Assistant Professor and a tenured Professor from 2002
to 2009. He led a team that reported the first power IC on SiC.
He is currently at Zhejiang University as a tenured Professor.
He has published approximately 90 technical papers in
international journals and conferences and is a holder of a
patent. His research interests include all aspects of power
semiconductor devices and ICs on SiC and Si.
Dr. Sheng serves as an Associate Editor of the IEEE
TRANSACTIONS ON POWER ELECTRONICS and the
IEEE TRANSACTIONS ON INDUSTRIAL
APPLICATIONS.

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