TMP275

SBOS363D − JUNE 2006 − REVISED AUGUST 2007

0.5°C Digital Out Temperature Sensor

FEATURES DESCRIPTION
D EIGHT ADDRESSES
The TMP275 is a 0.5°C accurate, Two-Wire, serial output
D DIGITAL OUTPUT: Two-Wire Serial Interface temperature sensor available in an MSOP-8 or an SO-8
D RESOLUTION: 9- to 12-Bits, User-Selectable package. The TMP275 is capable of reading temperatures
with a resolution of 0.0625°C.
D ACCURACY:
±0.5°C (max) from −20°C to +100°C The TMP275 is SMBus-compatible and allows up to eight
D LOW QUIESCENT CURRENT: devices on one bus. It is ideal for extended temperature
50µA, 0.1µA Standby measurement in a variety of communication, computer,
D WIDE SUPPLY RANGE: 2.7V to 5.5V consumer, environmental, industrial, and instrumentation
applications.
D SMALL MSOP-8 AND SO-8 PACKAGES
D NO POWER-UP SEQUENCE REQUIRED; The TMP275 is specified for operation over a temperature
TWO-WIRE BUS PULL-UPS CAN BE range of −40°C to +125°C.
ENABLED BEFORE V+
Temperature
APPLICATIONS
D POWER-SUPPLY TEMPERATURE SDA
1
Diode
Temp.
Control 8
V+
Logic
MONITORING Sensor

D COMPUTER PERIPHERAL THERMAL 2 7

PROTECTION SCL A0
∆Σ
D NOTEBOOK COMPUTERS A/D
Serial
Interface
D CELL PHONES ALERT
3
Converter
6
A1
D BATTERY MANAGEMENT
D OFFICE MACHINES 4
Config.
5
GND OSC and Temp. A2
D THERMOSTAT CONTROLS Register

D ENVIRONMENTAL MONITORING AND HVAC

D ELECTROMECHANICAL DEVICE TMP275

TEMPERATURE
TEM PER AT URE ER RO R AT 25 _ C TEM PER ATURE ERRO R vs TEMPERATURE
0.500

0.375
Temperature Error (_ C )

0.250

0.125
Population

− 0.125

− 0.250

− 0.375

− 0.500
− 55 − 35 − 15
− 0.50

− 0.40

− 0.30

− 0.20

− 0.10

0.00

0.10

0.20

0.30

0.40

0.50

5 25 45 65 85 105 125 130

Temperature ( _ C )
Temperature Error (_ C)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

             
 Copyright  2006−2007, Texas Instruments Incorporated
                  

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This integrated circuit can be damaged by ESD. Texas

ABSOLUTE MAXIMUM RATINGS(1) Instruments recommends that all integrated circuits be
Power Supply, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V handled with appropriate precautions. Failure to observe
Input Voltage(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 7.0V proper handling and installation procedures can cause damage.
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD damage can range from subtle performance degradation to
Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +127°C complete device failure. Precision integrated circuits may be more
Storage Temperature Range . . . . . . . . . . . . . . . . . −60°C to +130°C susceptible to damage because very small parametric changes could
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . . . . +150°C cause the device not to meet its published specifications.
ESD Rating:
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 4000V
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . 1000V
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Input voltage rating applies to all TMP275 input voltages.

ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
TMP275 MSOP-8 DGK T275
TMP275 SO-8 D TMP275
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.

PIN ASSIGNMENTS
Top View

SDA 1 8 V+

SCL 2 7 A0

ALERT 3 6 A1

GND 4 5 A2

MSOP−8, SO−8

NOTE: Pin 1 is determined by orienting the package as indicated in the diagram.

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ELECTRICAL CHARACTERISTICS
At TA = −40°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted.
TMP275
PARAMETER CONDITION UNITS
MIN TYP MAX
TEMPERATURE INPUT
Range −40 +125 °C
Accuracy (Temperature Error) −20°C to +100°C, V+ = 3.3V ±0.0625 ±0.5 °C
0°C to +100°C, V+ = 3.0V to 3.6V ±0.0625 ±0.75 °C
−40°C to +125°C, V+ = 3.0V to 3.6V ±0.0625 ±1 °C
+25°C to +100°C, V+ = 3.3V to 5.5V 0.2 ±1.5 °C
Resolution(1) Selectable +0.0625 °C
DIGITAL INPUT/OUTPUT
Input Capacitance 3 pF
Input Logic Levels:
VIH 0.7(V+) 6.0 V
VIL −0.5 0.3(V+) V
Leakage Input Current, IIN 0V ≤ VIN ≤ 6V 1 µA
Input Voltage Hysteresis SCL and SDA Pins 500 mV
Output Logic Levels:
VOL SDA IOL = 3mA 0 0.15 0.4 V
VOL ALERT IOL = 4mA 0 0.15 0.4 V
Resolution Selectable 9 to 12 Bits
Conversion Time 9-Bit 27.5 37.5 ms
10-Bit 55 75 ms
11-Bit 110 150 ms
12-Bit 220 300 ms
Timeout Time 25 54 74 ms
POWER SUPPLY
Operating Range 2.7 5.5 V
Quiescent Current IQ Serial Bus Inactive 50 85 µA
Serial Bus Active, SCL Freq = 400kHz 100 µA
Serial Bus Active, SCL Freq = 3.4MHz 410 µA
Shutdown Current ISD Serial Bus Inactive 0.1 3 µA
Serial Bus Active, SCL Freq = 400kHz 60 µA
Serial Bus Active, SCL Freq = 3.4MHz 380 µA
TEMPERATURE RANGE
Specified Range −40 +125 °C
Operating Range −55 +127 °C
Thermal Resistance qJA
MSOP-8 250 °C/W
SO-8 150 °C/W
(1) Specified for 12-bit resolution.

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TYPICAL CHARACTERISTICS
At TA = +25°C and V+ = 5.0V, unless otherwise noted.

QUIESCENT CURRENT vs TEMPERATURE SHUTDOWN CURRENT vs TEMPERATURE

85 1.0
0.9
75 0.8
0.7
65 0.6
V+ = 5V

ISD (µA)
IQ (µA)

0.5
55
0.4
0.3
45
0.2
V+ = 2.7V
0.1
35
0.0
Serial Bus Inactive
25 −0.1
−55 −35 −15 5 25 45 65 85 105 125 130 −55 −35 −15 5 25 45 65 85 105 125 130
Temperature (_ C) Temperature (_ C)

CONVERSION TIME vs TEMPERATURE TEMPERATURE ERROR vs TEMPERATURE

300 0.500

0.375
V+ = 5V
Conversion Time (ms)

250
Temperature Error (_C)

0.250

0.125
200 0
V+ = 2.7V
−0.125
150
−0.250
−0.375
12−bit resolution.
100 −0.500
−55 −35 −15 5 25 45 65 85 105 125 130 −55 −35 −15 5 25 45 65 85 105 125 130
Temperature (_ C) Temperature (_ C)

QUIESCENT CURRENT WITH TEMPERATURE ERROR AT 25_C

BUS ACTIVITY vs TEMPERATURE
500
Hs MODE
450
FAST MODE
400
350
Population

300
IQ (µA)

250
200
125_C
150
25_ C
100
50
−55_C
−0.50

−0.30

−0.20

−0.10

0
−0.40

0.00

0.10

0.20

0.30

0.40

0.50

1k 10k 100k 1M 10M

Frequency (Hz) Temperature Error (_C)

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APPLICATIONS INFORMATION Pointer

The TMP275 is a digital temperature sensor that is optimal Register
for thermal management and thermal protection
applications. The TMP275 is Two-Wire and SMBus
interface-compatible, and is specified over a temperature Temperature
range of −40°C to +125°C. Register

The TMP275 requires no external components for

SCL
operation except for pull-up resistors on SCL, SDA, and Configuration
ALERT, although a 0.1µF bypass capacitor is Register
I/O
recommended, as shown in Figure 1. Control
Interface
TLOW
V+ Register
SDA

0.1µF THIGH
8 Register
7
SCL 2 A0
To 6
Two−Wire TMP275 A1 Figure 2. Internal Register Structure of the
Controller
SDA 1 5
A2 TMP275
3 ALERT
4 (Output) P1 P0 REGISTER
0 0 Temperature Register (READ Only)
NOTE: SCL, SDA, and ALERT
pins require pull−up resistors. 0 1 Configuration Register (READ/WRITE)
1 0 TLOW Register (READ/WRITE)
GND
1 1 THIGH Register (READ/WRITE)
Figure 1. Typical Connections of the TMP275 Table 2. Pointer Addresses of the TMP275
The sensing device of the TMP275 is the chip itself. TEMPERATURE REGISTER
Thermal paths run through the package leads as well as
the plastic package. The lower thermal resistance of metal The Temperature Register of the TMP275 is a 12-bit,
causes the leads to provide the primary thermal path. read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data, and are
To maintain accuracy in applications requiring air or
described in Table 3 and Table 4. Note that byte 1 is the
surface temperature measurement, care should be taken
most significant byte, followed by byte 2, the least
to isolate the package and leads from ambient air
significant byte. The first 12 bits are used to indicate
temperature. A thermally-conductive adhesive will assist
temperature, with all remaining bits equal to zero. The
in achieving accurate surface temperature measurement.
least significant byte does not have to be read if that
information is not needed. Data format for temperature is
POINTER REGISTER
summarized in Table 5. Following power-up or reset, the
Figure 2 shows the internal register structure of the
Temperature Register will read 0°C until the first
TMP275. The 8-bit Pointer Register of the devices is used conversion is complete.
to address a given data register. The Pointer Register uses
the two LSBs to identify which of the data registers should
D7 D6 D5 D4 D3 D2 D1 D0
respond to a read or write command. Table 1 identifies the
bits of the Pointer Register byte. Table 2 describes the T11 T10 T9 T8 T7 T6 T5 T4
pointer address of the registers available in the TMP275. Table 3. Byte 1 of Temperature Register
Power-up reset value of P1/P0 is 00.
D7 D6 D5 D4 D3 D2 D1 D0
P7 P6 P5 P4 P3 P2 P1 P0 T3 T2 T1 T0 0 0 0 0
0 0 0 0 0 0 Register Bits Table 4. Byte 2 of Temperature Register
Table 1. Pointer Register Byte

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TEMPERATURE DIGITAL OUTPUT HEX POLARITY (POL)

(°C) (BINARY) The Polarity Bit of the TMP275 allows the user to adjust the
128 0111 1111 1111 7FF polarity of the ALERT pin output. If POL = 0, the ALERT pin
127.9375 0111 1111 1111 7FF will be active LOW, as shown in Figure 3. For POL = 1, the
100 0110 0100 0000 640 ALERT pin will be active HIGH, and the state of the ALERT
80 0101 0000 0000 500 pin is inverted.
75 0100 1011 0000 4B0
50 0011 0010 0000 320
25 0001 1001 0000 190
0.25 0000 0000 0100 004 T HIG H
Measured
0 0000 0000 0000 000 Temperature
−0.25 1111 1111 1100 FFC TL O W
−25 1110 0111 0000 E70
−55 1100 1001 0000 C90
Table 5. Temperature Data Format TMP275 ALERT PIN
(Comparator Mode)
POL = 0
The user can obtain 9, 10, 11, or 12 bits of resolution by
TMP275 ALERT PIN
addressing the Configuration Register and setting the
(Interrupt Mode)
resolution bits accordingly. For 9-, 10-, or 11-bit resolution, POL = 0
the most significant bits in the Temperature Register are TMP275 ALERT PIN
used with the unused LSBs set to zero. (Comparator Mode)
POL = 1
TMP275 ALERT PIN
CONFIGURATION REGISTER (Interrupt Mode)
The Configuration Register is an 8-bit read/write register POL = 1

used to store bits that control the operational modes of the

temperature sensor. Read/write operations are performed
Read Read Read
MSB first. The format of the Configuration Register for the
Time
TMP275 is shown in Table 6, followed by a breakdown of
the register bits. The power-up/reset value of the
Configuration Register is all bits equal to 0. Figure 3. Output Transfer Function Diagrams

BYTE D7 D6 D5 D4 D3 D2 D1 D0
FAULT QUEUE (F1/F0)
1 OS R1 R0 F1 F0 POL TM SD A fault condition is defined as when the measured
temperature exceeds the user-defined limits set in the
Table 6. Configuration Register Format THIGH and TLOW Registers. Additionally, the number of
fault conditions required to generate an alert may be
SHUTDOWN MODE (SD) programmed using the fault queue. The fault queue is
The Shutdown Mode of the TMP275 allows the user to provided to prevent a false alert as a result of
save maximum power by shutting down all device circuitry environmental noise. The fault queue requires
other than the serial interface, which reduces current consecutive fault measurements in order to trigger the
consumption to typically less than 0.1µA. Shutdown Mode alert function. Table 7 defines the number of measured
is enabled when the SD bit is 1; the device will shut down faults that may be programmed to trigger an alert condition
once the current conversion is completed. When SD is in the device. For THIGH and TLOW register format and byte
equal to 0, the device will maintain a continuous order, see section High and Low Limit Registers.
conversion state.
F1 F0 CONSECUTIVE FAULTS
THERMOSTAT MODE (TM)
0 0 1
The Thermostat Mode bit of the TMP275 indicates to the
0 1 2
device whether to operate in Comparator Mode (TM = 0)
1 0 4
or Interrupt Mode (TM = 1). For more information on
comparator and interrupt modes, see the High and Low 1 1 6
Limit Registers section. Table 7. Fault Settings of the TMP275

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CONVERTER RESOLUTION (R1/R0) Both operational modes are represented in Figure 3.

The Converter Resolution Bits control the resolution of the Table 9 and Table 10 describe the format for the THIGH and
internal Analog-to-Digital (A/D) converter. This control TLOW registers. Note that the most significant byte is sent
allows the user to maximize efficiency by programming for first, followed by the least significant byte. Power-up reset
higher resolution or faster conversion time. Table 8 values for THIGH and TLOW are:
identifies the Resolution Bits and the relationship between THIGH = 80°C and TLOW = 75°C
resolution and conversion time.
The format of the data for THIGH and TLOW is the same as
for the Temperature Register.
CONVERSION TIME
R1 R0 RESOLUTION (typical)
BYTE D7 D6 D5 D4 D3 D2 D1 D0
0 0 9 Bits (0.5°C) 27.5ms
1 H11 H10 H9 H8 H7 H6 H5 H4
0 1 10 Bits (0.25°C) 55ms
1 0 11 Bits (0.125°C) 110ms BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 1 12 Bits (0.0625°C) 220ms 2 H3 H2 H1 H0 0 0 0 0
Table 8. Resolution of the TMP275 Table 9. Bytes 1 and 2 of THIGH Register

ONE-SHOT (OS) BYTE D7 D6 D5 D4 D3 D2 D1 D0

The TMP275 features a One-Shot Temperature 1 L11 L10 L9 L8 L7 L6 L5 L4
Measurement Mode. When the device is in Shutdown
BYTE D7 D6 D5 D4 D3 D2 D1 D0
Mode, writing a ‘1’ to the OS bit starts a single temperature
2 L3 L2 L1 L0 0 0 0 0
conversion. The device returns to the shutdown state at
the completion of the single conversion. This mode is Table 10. Bytes 1 and 2 of TLOW Register
useful for reducing power consumption in the TMP275
when continuous temperature monitoring is not required. All 12 bits for the Temperature, THIGH, and TLOW registers
When the configuration register is read, the OS always are used in the comparisons for the ALERT function for all
reads zero. converter resolutions. The three LSBs in THIGH and TLOW
can affect the ALERT output even if the converter is
configured for 9-bit resolution.
HIGH AND LOW LIMIT REGISTERS
In Comparator Mode (TM = 0), the ALERT pin of the SERIAL INTERFACE
TMP275 becomes active when the temperature equals or
exceeds the value in THIGH and generates a consecutive The TMP275 operates only as a slave device on the
number of faults according to fault bits F1 and F0. The Two-Wire bus and SMBus. Connections to the bus are
made via the open-drain I/O lines SDA and SCL. The SDA
ALERT pin remains active until the temperature falls below
the indicated TLOW value for the same number of faults. and SCL pins feature integrated spike suppression filters
and Schmitt triggers to minimize the effects of input spikes
In Interrupt Mode (TM = 1), the ALERT pin becomes active and bus noise. The TMP275 supports the transmission
when the temperature equals or exceeds THIGH for a protocol for fast (1kHz to 400kHz) and high-speed (1kHz
consecutive number of fault conditions. The ALERT pin to 3.4MHz) modes. All data bytes are transmitted MSB
remains active until a read operation of any register first.
occurs, or the device successfully responds to the SMBus
Alert Response Address. The ALERT pin is also cleared SERIAL BUS ADDRESS
if the device is placed in Shutdown Mode. Once the ALERT To communicate with the TMP275, the master must first
pin is cleared, it only becomes active again by the address slave devices via a slave address byte. The slave
temperature falling below TLOW. When the temperature address byte consists of seven address bits, and a
falls below TLOW, the ALERT pin becomes active and direction bit indicating the intent of executing a read or
remain active until cleared by a read operation of any write operation.
register or a successful response to the SMBus Alert
Response Address. Once the ALERT pin is cleared, the The TMP275 features three address pins allowing up to
above cycle repeats, with the ALERT pin becoming active eight devices to be connected per bus. Pin logic levels are
when the temperature equals or exceeds THIGH. The described in Table 11. The address pins of the TMP275 are
ALERT pin can also be cleared by resetting the device with read after reset, at start of communication, or in response
the General Call Reset command. This command also to a Two-Wire address acquire request. Following reading
clears the state of the internal registers in the device, the state of the pins the address is latched to minimize
returning the device to Comparator Mode (TM = 0). power dissipation associated with detection.

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A2 A1 A0 SLAVE ADDRESS Figure 6 for details of this sequence. If repeated reads

0 0 0 1001000 from the same register are desired, it is not necessary to
0 0 1 1001001 continually send the Pointer Register bytes, as the
TMP275 remembers the Pointer Register value until it is
0 1 0 1001010
changed by the next write operation.
0 1 1 1001011
1 0 0 1001100 Note that register bytes are sent most-significant byte first,
1 0 1 1001101 followed by the least significant byte.
1 1 0 1001110
1 1 1 1001111
SLAVE MODE OPERATIONS
The TMP275 can operate as a slave receiver or slave
Table 11. Address Pins and Slave Addresses for transmitter.
the TMP275
Slave Receiver Mode:
BUS OVERVIEW The first byte transmitted by the master is the slave
The device that initiates the transfer is called a master, and address, with the R/W bit LOW. The TMP275 then
the devices controlled by the master are slaves. The bus acknowledges reception of a valid address. The next byte
must be controlled by a master device that generates the transmitted by the master is the Pointer Register. The
serial clock (SCL), controls the bus access, and generates TMP275 then acknowledges reception of the Pointer
the START and STOP conditions. Register byte. The next byte or bytes are written to the
register addressed by the Pointer Register. The TMP275
To address a specific device, a START condition is acknowledges reception of each data byte. The master
initiated, indicated by pulling the data-line (SDA) from a may terminate data transfer by generating a START or
HIGH to LOW logic level while SCL is HIGH. All slaves on STOP condition.
the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended. Slave Transmitter Mode:
During the ninth clock pulse, the slave being addressed The first byte is transmitted by the master and is the slave
responds to the master by generating an Acknowledge address, with the R/W bit HIGH. The slave acknowledges
and pulling SDA LOW. reception of a valid slave address. The next byte is
transmitted by the slave and is the most significant byte of
Data transfer is then initiated and sent over eight clock the register indicated by the Pointer Register. The master
pulses followed by an Acknowledge Bit. During data acknowledges reception of the data byte. The next byte
transfer SDA must remain stable while SCL is HIGH, as transmitted by the slave is the least significant byte. The
any change in SDA while SCL is HIGH is interpreted as a master acknowledges reception of the data byte. The
control signal. master may terminate data transfer by generating a
Not-Acknowledge on reception of any data byte, or
Once all data has been transferred, the master generates
generating a START or STOP condition.
a STOP condition indicated by pulling SDA from LOW to
HIGH, while SCL is HIGH.
SMBus ALERT FUNCTION
The TMP275 supports the SMBus Alert function. When
WRITING/READING TO THE TMP275 the TMP275 is operating in Interrupt Mode (TM = 1), the
Accessing a particular register on the TMP275 is ALERT pin of the TMP275 may be connected as an
accomplished by writing the appropriate value to the SMBus Alert signal. When a master senses that an ALERT
Pointer Register. The value for the Pointer Register is the condition is present on the ALERT line, the master sends
first byte transferred after the slave address byte with the an SMBus Alert command (00011001) on the bus. If the
R/W bit LOW. Every write operation to the TMP275 ALERT pin of the TMP275 is active, the device
requires a value for the Pointer Register. (Refer to acknowledges the SMBus Alert command and responds
Figure 5.) by returning its slave address on the SDA line. The eighth
bit (LSB) of the slave address byte indicates if the
When reading from the TMP275, the last value stored in
temperature exceeding THIGH or falling below TLOW
the Pointer Register by a write operation is used to
caused the ALERT condition. This bit will be HIGH if the
determine which register is read by a read operation. To
temperature is greater than or equal to THIGH. This bit will
change the register pointer for a read operation, a new
be LOW if the temperature is less than TLOW. Refer to
value must be written to the Pointer Register. This is
Figure 7 for details of this sequence.
accomplished by issuing a slave address byte with the
R/W bit LOW, followed by the Pointer Register Byte. No If multiple devices on the bus respond to the SMBus Alert
additional data is required. The master can then generate command, arbitration during the slave address portion of
a START condition and send the slave address byte with the SMBus Alert command determines which device will
the R/W bit HIGH to initiate the read command. See clear its ALERT status. If the TMP275 wins the arbitration,

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its ALERT pin will become inactive at the completion of the TIMING DIAGRAMS
SMBus Alert command. If the TMP275 loses the
arbitration, its ALERT pin will remain active. The TMP275 is Two-Wire and SMBus-compatible.
Figure 4 to Figure 7 describe the various operations on the
GENERAL CALL TMP275. Bus definitions are given below. Parameters for
The TMP275 responds to a Two-Wire General Call Figure 4 are defined in Table 12.
address (0000000) if the eighth bit is 0. The device
acknowledges the General Call address and responds to Bus Idle: Both SDA and SCL lines remain HIGH.
commands in the second byte. If the second byte is
00000100, the TMP275 latches the status of the address
pins, but does not reset. If the second byte is 00000110, Start Data Transfer: A change in the state of the SDA line,
the TMP275 latches the status of the address pins and from HIGH to LOW, while the SCL line is HIGH, defines a
resets the internal registers to the power-up values. START condition. Each data transfer is initiated with a
START condition.
HIGH-SPEED MODE
In order for the Two-Wire bus to operate at frequencies
above 400kHz, the master device must issue an Hs-mode Stop Data Transfer: A change in the state of the SDA line
master code (00001XXX) as the first byte after a START from LOW to HIGH while the SCL line is HIGH defines a
condition to switch the bus to high-speed operation. The STOP condition. Each data transfer is terminated with a
TMP275 will not acknowledge this byte, but will switch its repeated START or STOP condition.
input filters on SDA and SCL and its output filters on SDA
to operate in Hs-mode, allowing transfers at up to 3.4MHz. Data Transfer: The number of data bytes transferred
After the Hs-mode master code has been issued, the between a START and a STOP condition is not limited and
master transmits a Two-Wire slave address to initiate a is determined by the master device. The receiver
data transfer operation. The bus continues to operate in acknowledges the transfer of data.
Hs-mode until a STOP condition occurs on the bus. Upon
receiving the STOP condition, the TMP275 switches the
input and output filters back to fast-mode operation. Acknowledge: Each receiving device, when addressed,
is obliged to generate an Acknowledge bit. A device that
TIMEOUT FUNCTION acknowledges must pull down the SDA line during the
The TMP275 resets the serial interface if either SCL or Acknowledge clock pulse in such a way that the SDA line
SDA is held LOW for 54ms (typ) between a START and is stable LOW during the HIGH period of the Acknowledge
STOP condition. The TMP275 releases the bus if it is clock pulse. Setup and hold times must be taken into
pulled LOW and waits for a START condition. To avoid account. On a master receive, the termination of the data
activating the timeout function, it is necessary to maintain transfer can be signaled by the master generating a
a communication speed of at least 1kHz for SCL operating Not-Acknowledge on the last byte that has been
frequency. transmitted by the slave.

FAST MODE HIGH-SPEED MODE

PARAMETER UNITS
MIN MAX MIN MAX
SCL Operating Frequency f(SCL) 0.001 0.4 0.001 3.4 MHz
Bus Free Time Between STOP and START Condition t(BUF) 600 160 ns
Hold time after repeated START condition.
t(HDSTA) 100 100 ns
After this period, the first clock is generated.
Repeated START Condition Setup Time t(SUSTA) 100 100 ns
STOP Condition Setup Time t(SUSTO) 100 100 ns
Data Hold Time t(HDDAT) 0 0 ns
Data Setup Time t(SUDAT) 100 10 ns
SCL Clock LOW Period t(LOW) 1300 160 ns
SCL Clock HIGH Period t(HIGH) 600 60 ns
Clock/Data Fall Time tF 300 160 ns
Clock/Data Rise Time tR 300 160 ns
for SCLK ≤ 100kHz tR 1000 ns

Table 12. Timing Diagram Definitions for the TMP275

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SBOS363D − JUNE 2006 − REVISED AUGUST 2007

TWO-WIRE TIMING DIAGRAMS

t(LOW)
tR tF t(HDSTA)

SCL

t(HDSTA) t(HIGH) t(SUSTA) t(SUSTO)

t(HDDAT) t(SUDAT)

SDA
t(BU F )

P S S P

Figure 4. Two-Wire Timing Diagram

1 9 1 9

SCL …

SDA 1 0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 P1 P0 …
Start By ACK By ACK By
Master TMP275 TMP275
Frame 1 Two−Wire Slave Address Byte Frame 2 Pointer Register Byte

1 9 1 9
SCL
(Continued)

SDA
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
ACK By ACK By Stop By
TMP275 TMP275 Master
Frame 3 Data Byte 1 Frame 4 Data Byte 2

Figure 5. Two-Wire Timing Diagram for TMP275 Write Word Format

10
 "
#$%
www.ti.com
SBOS363D − JUNE 2006 − REVISED AUGUST 2007

1 9 1 9

SCL …

SDA 1 0 0 1 0 0 0 R/W 0 0 0 0 0 0 P1 P0 …
Start By ACK By ACK By
Master TMP275 TMP275
Frame 1 Two−Wire Slave Address Byte Frame 2 Pointer Register Byte

1 9 1 9
SCL …
(Continued)

SDA
1 0 0 1 0 0 0 R/W D7 D6 D5 D4 D3 D2 D1 D0 …
(Continued)
Start By ACK By From ACK By
Master TMP275 TMP275 Master
Frame 3 Two−Wire Slave Address Byte Frame 4 Data Byte 1 Read Register

1 9
SCL
(Continued)

SDA
D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
From ACK By Stop By
TMP275 Master Master
Frame 5 Data Byte 2 Read Register NOTE: Address Pins A0, A1, A2 = 0

Figure 6. Two-Wire Timing Diagram for Read Word Format

ALERT

1 9 1 9

SCL

SDA 0 0 0 1 1 0 0 R/W 1 0 0 1 0 0 0 S ta tu s

Start By ACK By From NACK By Stop By

Master TMP275 TMP275 Master Master
Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address Byte

NOTE: Address Pins A0, A1, A2 = 0

Figure 7. Timing Diagram for SMBus ALERT

11
 PACKAGE OPTION ADDENDUM

www.ti.com 16-Jul-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (3) (4/5)

TMP275AID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275
& no Sb/Br)
TMP275AIDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275
& no Sb/Br)
TMP275AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T275
& no Sb/Br)
TMP275AIDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T275
& no Sb/Br)
TMP275AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T275
& no Sb/Br)
TMP275AIDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 T275
& no Sb/Br)
TMP275AIDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275
& no Sb/Br)
TMP275AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 TMP275
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 16-Jul-2013

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP275AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TMP275AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TMP275AIDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TMP275AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMP275AIDGKR VSSOP DGK 8 2500 370.0 355.0 55.0
TMP275AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
TMP275AIDGKT VSSOP DGK 8 250 366.0 364.0 50.0
TMP275AIDR SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
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