TMP100-Q1, TMP101-Q1

SBOS581B – SEPTEMBER 2011 – REVISED JUNE 2022

TMP100-Q1 and TMP101-Q1 Temperature Sensor With I2C and SMBus Interface with
Alert Function in SOT-23 Package

1 Features 3 Description
• AEC-Q100 qualified with the following results: The TMP100-Q1 and TMP101-Q1 devices are
– Temperature grade 1: −55°C to +125°C digital temperature sensors designed for negative
operating temperature range temperature coefficient (NTC) and positive
– HBM ESD component classification level 2 temperature coefficient (PTC) thermistor replacement.
– CDM ESD component classification level C5 The devices offer a typical accuracy of ±1°C without
• Functional Safety-Capable requiring calibration or external component signal
– Documentation available to aid functional safety conditioning. Device temperature sensors are highly
system design linear and do not require complex calculations or
• Digital output: SMBus™, two-wire, and I2C look-up tables to derive the temperature. The on-chip,
interface compatibility 12-bit ADC offers resolutions down to 0.0625°C. The
• Resolution: 9 to 12 bits, user-selectable devices are available in 6-Pin SOT-23 packages.
• Accuracy: The TMP100-Q1 and TMP101-Q1 devices feature
– ±1°C (typical) from –55°C to 125°C SMBus, Two-Wire, and I2C interface compatibility. The
– ±2°C (maximum) from –55°C to 125°C TMP100-Q1 device allows up to eight devices on one
• Low quiescent current: 45-μA, 0.1-μA standby bus. The TMP101-Q1 device offers an SMBus Alert
• Wide supply range: 2.7 V to 5.5 V function with up to three devices per bus.
• TMP100-Q1 features two address pins
• TMP101-Q1 features one address pin and an The TMP100-Q1 and TMP101-Q1 devices are
ALERT pin designed for extended temperature measurement in
• 6-pin SOT-23 package a variety of communication, computer, consumer,
environmental, industrial, and instrumentation
2 Applications applications.
• Power-supply temperature monitoring The TMP100-Q1 and TMP101-Q1 devices are
• Battery management specified for operation over a temperature range of
• Thermostat controls −55°C to 125°C.
• Automotive:
Device Information(1)
– Head unit
PART NUMBER PACKAGE BODY SIZE (NOM)
– Cluster
– Body electronics TMP100-Q1 SOT-23 (6) 2.90 mm × 1.60 mm
– Lighting TMP101-Q1 SOT-23 (6) 2.90 mm × 1.60 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
Temperature Temperature
Diode Diode
1 Control 6 1 Control 6
SCL Temp SDA SCL Temp SDA
Logic Logic
Sensor Sensor

2

Serial 5 2

Serial 5
GND ADC ADD0 GND ADC ADD0
Interface Interface
Converter Converter

Config Config
3 OSC and Temp 4 3 OSC and Temp 4
ADD1 V+ ALERT V+
Register Register

TMP100-Q1 Block Diagram TMP101-Q1 Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes..........................................14
2 Applications..................................................................... 1 7.5 Programming............................................................ 14
3 Description.......................................................................1 8 Application and Implementation.................................. 19
4 Revision History.............................................................. 2 8.1 Application Information............................................. 19
5 Pin Configuration and Functions...................................3 8.2 Typical Application.................................................... 19
6 Specifications.................................................................. 4 9 Power Supply Recommendations................................20
6.1 Absolute Maximum Ratings........................................ 4 10 Layout...........................................................................21
6.2 ESD Ratings............................................................... 4 10.1 Layout Guidelines................................................... 21
6.3 Recommended Operating Conditions.........................4 10.2 Layout Examples.................................................... 21
6.4 Thermal Information....................................................4 11 Device and Documentation Support..........................23
6.5 Electrical Characteristics.............................................5 11.1 Receiving Notification of Documentation Updates.. 23
6.6 Timing Requirements.................................................. 6 11.2 Support Resources................................................. 23
6.7 Typical Characteristics................................................ 7 11.3 Trademarks............................................................. 23
7 Detailed Description........................................................8 11.4 Electrostatic Discharge Caution.............................. 23
7.1 Overview..................................................................... 8 11.5 Glossary.................................................................. 23
7.2 Functional Block Diagram........................................... 8 12 Mechanical, Packaging, and Orderable
7.3 Feature Description.....................................................9 Information.................................................................... 23

4 Revision History
Changes from Revision A (May 2017) to Revision B (June 2022) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added Functional Safety information to the Features section............................................................................ 1

Changes from Revision * (September 2011) to Revision A (May 2017) Page

• Added the Device Information table, Pin Configuration and Functions section, Handling Ratings table, Timing
Requirements table, Switching Characteristics tableFeature Description section , Device Functional Modes
section, Application and Implementation section, Power Supply Recommendations section, Layout section,
Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section 1

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5 Pin Configuration and Functions

SCL 1 6 SDA SCL 1 6 SDA

GND 2 5 ADD0 GND 2 5 ADD0

ADD1 3 4 V+ ALERT 3 4 V+

Not to scale Not to scale

Figure 5-1. TMP100-Q1 DBV Package 6-Pin SOT-23 Figure 5-2. TMP101-Q1 DBV Package 6-Pin SOT-23
Top View Top View

Table 5-1. Pin Functions

PIN
NO. I/O DESCRIPTION
NAME
TMP100-Q1 TMP101-Q1
ADD0 5 5 I Address select. Connect to GND, V+, or leave floating.
ADD1 3 — I Address select. Connect to GND, V+, or leave floating.
ALERT — 3 O Overtemperature alert. Open-drain output; requires a pullup resistor.
GND 2 2 — Ground
SCL 1 1 I Serial clock. Open-drain output; requires a pullup resistor.
SDA 6 6 I/O Serial data. Open-drain output; requires a pullup resistor.
V+ 4 4 I Supply voltage, 2.7 V to 5.5 V

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply, V+ 7.5 V
Input voltage(2) –0.5 7.5 V
Operating temperature –55 125 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –60 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input voltage rating applies to all TMP100-Q1 and TMP101-Q1 input voltages.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC Q100-002 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Q100-011 ±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage 2.7 5.5 V
Operating free-air temperature, TA –55 125 °C

6.4 Thermal Information

TMP100-Q1,
TMP101-Q1
THERMAL METRIC(1) UNIT
DBV (SOT-23)
6 PINS
RθJA Junction-to-ambient thermal resistance 182.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 115 °C/W
RθJB Junction-to-board thermal resistance 30.2 °C/W
ψJT Junction-to-top characterization parameter 17.1 °C/W
ψJB Junction-to-board characterization parameter 29.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

At TA = −55°C to 125°C and V+ = 2.7 V to 5.5 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE INPUT
Range –55 125 °C
−25°C to 85°C ±0.5 ±2
Accuracy (temperature error) °C
−55°C to 125°C ±1 ±2
Accuracy (temperature error) vs. supply 0.2 ±0.5 °C/V
Resolution Selectable 0.0625 °C
DIGITAL INPUT/OUTPUT
Input capacitance 3 pF
VIH High-level input logic 0.7 (V+) 6 V
VIL Low-level input logic −0.5 0.3 (V+) V
IIN Input current 0 V ≤ VIN ≤ 6 V 1 µA
VOL Low-level output logic SDA IOL = 3 mA 0 0.15 0.4 V
VOL Low-level output logic ALERT IOL = 4 mA 0 0.15 0.4 V
Resolution Selectable 9 12 Bits
9 bits 40 75
10 bits 80 150
Conversion time ms
11 bits 160 300
12 bits 320 600
9 bits 25
10 bits 12
Conversion rate s/s
11 bits 6
12 bits 3
POWER SUPPLY
Operating range 2.7 5.5 V
Serial bus inactive 45 75
IQ Quiescent current Serial bus active, SCL frequency = 400 kHz 70 µA
Serial bus active, SCL frequency = 3.4 MHz 150
Serial bus inactive 0.1 13
ISD Shutdown current Serial bus active, SCL frequency = 400 kHz 20 µA
Serial bus active, SCL frequency = 3.4 MHz 100
TEMPERATURE RANGE
Specified range –55 125 °C
Storage range –60 150 °C

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6.6 Timing Requirements

FAST MODE HIGH-SPEED MODE
PARAMETER UNIT
MIN MAX MIN MAX
f(SCL) SCL operating frequency 0.4 2 MHz
t(BUF) Bus free time between STOP and START condition 1300 160 ns
Hold time after repeated START condition.
t(HDSTA) 600 160 ns
After this period, the first clock is generated.
t(SUSTA) Repeated START condition setup time 600 160 ns
t(SUSTO) STOP condition setup time 600 160 ns
t(HDDAT) Data hold time 20 900 20 170 ns
t(SUDAT) Data setup time 100 20 ns
t(LOW) SCL clock LOW period 1300 360 ns
t(HIGH) SCL clock HIGH period 600 60 ns
tRC, tFC Clock rise and fall time 300 40 ns
tRD, tFD Data rise and fall time 300 170 ns

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6.7 Typical Characteristics

At TA = 25°C and V+ = 5 V, unless otherwise noted.

70 1
0.9
0.8
60 0.7
V+ = 5 V
0.6

ISD (µA)
I Q (µA)

0.5
50
0.4
0.3
V+ = 27 V
0.2
40
0.1
0
Serial Bus Inactive
30 −0.1
−60 −40 −20 0 20 40 60 80 100 120 140 −60 −40 −20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Figure 6-1. Quiescent Current vs. Temperature Figure 6-2. Shutdown Current vs. Temperature
400 2.0

1.5
Temperature Error (°C)
Conversion Time (ms)

1.0
350
V+ = 5 V 0.5

0.0

−0.5
300
V+ = 2.7 V
−1.0

−1.5
NOTE: 12−bit resolution. 3 Typical Units NOTE: 12−bit resolution.
250 −2.0
−60 −40 −20 0 20 40 60 80 100 120 140 −60 −40 −20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Figure 6-3. Conversion Time vs. Temperature Figure 6-4. Temperature Accuracy vs. Temperature
180

160
125°C
140
25°C
120
I Q (µA)

100
125°C
80
25°C −55°C
60
40
−55°C
20
FAST MODE Hs MODE
0
10k 100k 1M 10M
SCL Frequency (Hz)
Figure 6-5. Quiescent Current With Bus Activity vs. Temperature

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7 Detailed Description
7.1 Overview
The TMP100-Q1 and TMP101-Q1 devices are digital temperature sensors optimal for thermal management
and thermal protection applications. The TMP100-Q1 and TMP101-Q1 devices are Two-Wire, SMBus, and
I2C interface-compatible. These devices are specified over a operating temperature range of −55°C to 125°C.
The Functional Block Diagram section shows the internal block diagrams of the TMP100-Q1 and TMP101-Q1
devices.
The temperature sensor in the TMP100-Q1 and TMP101-Q1 devices is the chip itself. Thermal paths run
through the package leads as well as the plastic package. The package leads provide the primary thermal path
because of the lower thermal resistance of the metal. The GND pin of the TMP100-Q1 or TMP101-Q1 is directly
connected to the metal lead frame, and is the best choice for thermal input.
7.2 Functional Block Diagram
Temperature
Diode
1 Control 6
SCL Temp SDA
Logic
Sensor

2

Serial 5
GND ADC ADD0
Interface
Converter

Config
3 OSC and Temp 4
ADD1 V+
Register

Figure 7-1. TMP100-Q1 Block Diagram

Temperature
Diode
1 Control 6
SCL Temp SDA
Logic
Sensor

2

Serial 5
GND ADC ADD0
Interface
Converter

Config
3 OSC and Temp 4
ALERT V+
Register

Figure 7-2. TMP101-Q1 Block Diagram

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7.3 Feature Description

7.3.1 Digital Temperature Output
The digital output from each temperature measurement conversion is stored in the read-only Temperature
Register. The Temperature Register of the TMP100-Q1 or TMP101-Q1 device is a 12-bit, read-only register that
stores the output of the most recent conversion. Two bytes must be read to obtain data and are listed in Table
7-6 and Table 7-7. The first 12 bits are used to indicate temperature with all the remaining bits equal to zero. The
data format for temperature is listed in Table 7-1. Negative numbers are represented in binary twos complement
format. Following power-up or reset, the temperature register reads 0°C until the first conversion is complete.
The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration Register and setting the
resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits (MSBs) in the Temperature
Register are used with the unused least significant bits (LSBs) set to zero.
Table 7-1. Temperature Data Format
TEMPERATURE DIGITAL OUTPUT
(°C) BINARY HEX
128 0111 1111 1111 7FF
127.9375 0111 1111 1111 7FF
100 0110 0100 0000 640
80 0101 0000 0000 500
75 0100 1011 0000 4B0
50 0011 0010 0000 320
25 0001 1001 0000 190
0.25 0000 0000 0100 004
0 0000 0000 0000 000
–0.25 1111 1111 1100 FFC
–25 1110 0111 0000 E70
–55 1100 1001 0000 C90
–128 1000 0000 0000 800

7.3.2 Serial Interface

The TMP100-Q1 and TMP101-Q1 devices operate only as target devices on the SMBus, Two-Wire, and I2C
interface-compatible bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The
TMP100-Q1 and TMP101-Q1 devices support the transmission protocol for fast (up to 400 kHz) and high-speed
(up to 2 MHz) modes. All data bytes are transmitted MSB first.
7.3.3 Bus Overview
The device that initiates the transfer is called a controller, and the devices controlled by the controller are targets.
The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access,
and generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data line (SDA) from a HIGH
to LOW logic level while SCL is HIGH. All targets on the bus shift in the target address byte, with the last bit
indicating whether a read or write operation is intended. During the ninth clock pulse, the target being addressed
responds to the controller by generating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data
transfer, SDA must remain stable while SCL is HIGH because any change in SDA while SCL is HIGH is
interpreted as a control signal.
When all data are transferred, the controller generates a STOP condition indicated by pulling SDA from LOW to
HIGH, while SCL is HIGH.

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7.3.4 Serial Bus Address

To program the TMP100-Q1 and TMP101-Q1 devices, the controller must first address target devices through
a target address byte. The target address byte consists of seven address bits and a direction bit indicating the
intent of executing a read or write operation.
The TMP100-Q1 device features two address pins to allow up to eight devices to be addressed on a single I2C
interface. Table 7-2 describes the pin logic levels used to properly connect up to eight devices. Float indicates
the pin is left unconnected. The state of pins ADD0 and ADD1 is sampled on the first I2C bus communication
and must be set before any activity on the interface.
Table 7-2. Address Pins and Target Addresses for the TMP100-Q1
ADD1 ADD0 TARGET ADDRESS
0 0 1001000
0 Float 1001001
0 1 1001010
1 0 1001100
1 Float 1001101
1 1 1001110
Float 0 1001011
Float 1 1001111

The TMP101-Q1 device features one address pin and an ALERT pin, allowing up to three devices to be
connected per bus. Pin logic levels are described in Table 7-3. The address pins of the TMP100-Q1 and
TMP101-Q1 devices are read after reset or in response to an I2C address acquire request. Following reading,
the state of the address pins is latched to minimize power dissipation associated with detection.
Table 7-3. Address Pins and Target Addresses for the TMP101-Q1
ADD0 TARGET ADDRESS
0 1001000
Float 1001001
1 1001010

7.3.5 Writing and Reading to the TMP100-Q1 and TMP101-Q1

Accessing a particular register on the TMP100-Q1 and TMP101-Q1 devices is accomplished by writing the
appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after
the I2C target address byte with the R/ W bit LOW. Every write operation to the TMP100-Q1 and TMP101-Q1
devices requires a value for the Pointer Register (see Figure 7-4).
When reading from the TMP100-Q1 and TMP101-Q1 devices, the last value stored in the Pointer Register by a
write operation is used to determine which register is read by a read operation. To change the register pointer
for a read operation, a new value must be written to the Pointer Register. This action is accomplished by issuing
an I2C target address byte with the R/ W bit LOW, followed by the Pointer Register Byte. No additional data
are required. The controller can then generate a START condition and send the I2C target address byte with
the R/ W bit HIGH to initiate the read command; see Figure 7-5 for details of this sequence. If repeated reads
from the same register are desired, the Pointer Register bytes do not have to be continually sent because the
TMP100-Q1 and TMP101-Q1 devices remember the Pointer Register value until that value is changed by the
next write operation.

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7.3.6 Target Mode Operations

The TMP100-Q1 and TMP101-Q1 devices can operate as a target receiver or target transmitter.
7.3.6.1 Target Receiver Mode
The first byte transmitted by the controller is the target address, with the R/ W bit LOW. The TMP100-Q1
or TMP101-Q1 devices then acknowledges reception of a valid address. The next byte transmitted by the
controller is the Pointer Register. The TMP100-Q1 or TMP101-Q1 devices then acknowledges reception of the
Pointer Register byte. The next byte or bytes are written to the register addressed by the Pointer Register. The
TMP100-Q1 and TMP101-Q1 devices acknowledge reception of each data byte. The controller can terminate
data transfer by generating a START or STOP condition.
7.3.6.2 Target Transmitter Mode
The first byte is transmitted by the controller and is the target address, with the R/ W bit HIGH. The target
acknowledges reception of a valid target address. The next byte is transmitted by the target and is the most
significant byte of the register indicated by the Pointer Register. The controller acknowledges reception of the
data byte. The next byte transmitted by the target is the least significant byte. The controller acknowledges
reception of the data byte. The controller can terminate data transfer by generating a Not-Acknowledge on
reception of any data byte, or generating a START or STOP condition.
7.3.7 SMBus Alert Function
The TMP101-Q1 device supports the SMBus Alert function. When the TMP101-Q1 device is operating in
Interrupt Mode (TM = 1), the ALERT pin of the TMP101-Q1 device can be connected as an SMBus Alert signal.
When a controller senses that an ALERT condition is present on the ALERT line, the controller sends an SMBus
Alert command (00011001) on the bus. If the ALERT pin of the TMP101-Q1 device is active, the TMP101-Q1
device acknowledges the SMBus Alert command and responds by returning its target address on the SDA line.
The eighth bit (LSB) of the target address byte indicates if the temperature exceeding THIGH or falling below
TLOW caused the ALERT condition. For POL = 0, this bit is LOW if the temperature is greater than or equal to
THIGH. This bit is HIGH if the temperature is less than TLOW. The polarity of this bit is inverted if POL = 1; see
Figure 7-6 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the target address
portion of the SMBus alert command determine which device clears its ALERT status. If the TMP101-Q1 device
wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the
TMP101-Q1 loses the arbitration, its ALERT pin remains active.
The TMP100-Q1 device also responds to the SMBus ALERT command if its TM bit is set to 1. Because the
device does not have an ALERT pin, the device must periodically poll the device by issuing an SMBus Alert
command. If the TMP100-Q1 device generates an ALERT, the device acknowledges the SMBus Alert command
and returns its target address in the next byte.
7.3.8 General Call
The TMP100-Q1 and TMP101-Q1 devices respond to the I2C General Call address (0000000) if the eighth bit
is 0. The device acknowledges the General Call address and responds to commands in the second byte. If the
second byte is 00000100, the TMP100-Q1 and TMP101-Q1 devices latch the status of their address pins, but
do not reset. If the second byte is 00000110, the TMP100-Q1 and TMP101-Q1 devices latch the status of their
address pins and reset their internal registers.
7.3.9 High-Speed Mode
In order for the I2C bus to operate at frequencies above 400 kHz, the controller device must issue an Hs-mode
controller code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation.
The TMP100-Q1 and TMP101-Q1 devices do not acknowledge this byte as required by the I2C specification,
but do switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing
transfers at up to 2 MHz. After the Hs-mode controller code is issued, the controller transmits an I2C target
address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition

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occurs on the bus. Upon receiving the STOP condition, the TMP100-Q1 and TMP101-Q1 devices switch the
input and output filter back to fast-mode operation.
7.3.10 POR (Power-On Reset)
The TMP100-Q1 and TMP101-Q1 devices both have on-chip, power-on reset circuits that reset the device to
default settings when the device is powered on. This circuit activates when the power supply is less than 0.3
V for more than 100 ms. If the TMP100-Q1 and TMP101-Q1 devices are powered down by removing supply
voltage from the device, but the supply voltage is not assured to be less than 0.3 V, TI recommends issuing a
General Call reset command on the I2C interface bus to ensure that the TMP100-Q1 and TMP101-Q1 devices
are completely reset.
7.3.11 Timing Diagrams
The TMP100-Q1 and TMP101-Q1 devices are Two-Wire, SMBUs, and I2C interface-compatible. Figure 7-3 to
Figure 7-6 describe the various operations on the TMP100-Q1 and TMP101-Q1. The following list provides bus
definitions. Parameters for Figure 7-3 are defined in the Timing Requirements table.
Bus Idle: Both SDA and SCL lines remain HIGH.
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH,
defines a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH
defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the controller device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be
taken into account. On a controller receive, the termination of the data transfer can be signaled by the controller
generating a Not-Acknowledge on the last byte that is transmitted by the target.
t(LOW)
tFC t(HDSTA)
tRC

SCL

t(HDSTA) t(HIGH) t(SUSTA) t(SUSTO)

t(HDDAT) t(SUDAT)

SDA
t(BUF)
tRD tFD
P S S P

Figure 7-3. I2C Timing Diagram

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1 9 1 9

SCL …

SDA 1 0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 P1 P0 …
Start By ACK By ACK By
Target TMP100-Q1 orTMP101-Q1 TMP100-Q1 or TMP101-Q1
Frame 1 I2C Target Address Byte Frame 2 Pointer Register Byte

1 9 1 9
SCL
(Continued)

SDA
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
ACK By ACK By Stop By
TMP100-Q1 or TMP101-Q1 TMP100-Q1 or TMP101-Q1 Target
Frame 3 Data Byte 1 Frame 4 Data Byte 2

Figure 7-4. I2C Timing Diagram for Write Word Format

1 9 1 9

SCL …

SDA 1 0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 P1 P0 …
Start By ACK By ACK By
Controller TMP 100-Q1orTMP101-Q1 TMP 100-Q1or TMP 101-Q1

Frame 1 I2C Target Address Byte Frame 2 Pointer Register Byte

1 9 1 9
SCL …
(Continued)

SDA
1 0 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 …
(Continued)
Start By ACK By From ACK By
Controller TMP 100-Q1orTMP101-Q1 TMP 100-Q1orTMP 101-Q1 Controller
2
Frame 3 I C Target Address Byte Frame 4 Data Byte 1 Read Register

1 9
SCL
(Continued)

SDA
D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
From ACK By Stop By
TMP100-Q1orTMP101-Q1 Controller Controller
Frame 5 Data Byte 2 Read Register

Figure 7-5. I2C Timing Diagram for Read Word Format

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ALERT

1 9 1 9

SCL

SDA 0 0 0 1 1 0 0 R/W 1 0 0 1 A2 A1 A0 S ta tu s

Start By ACK By From NACK By Stop By

Controller TMP100-Q1 or TMP101-Q1 TMP 100-Q1 or TMP 101-Q1 Controller Controller
Frame 1 SMBus ALERT R esponse Address Byte Frame 2 Target Address From TMP100-Q1

Figure 7-6. Timing Diagram for SMBus ALERT

7.4 Device Functional Modes

7.4.1 Shutdown Mode (SD)
The Shutdown Mode of the TMP100-Q1 and TMP101-Q1 devices lets the user save maximum power by
shutting down all device circuitry other than the serial interface, which reduces current consumption to less
than 1 µA. For the TMP100-Q1 and TMP101-Q1 devices, Shutdown Mode is enabled when the SD bit is 1.
The device shuts down when the current conversion is completed. For SD equal to 0, the device maintains
continuous conversion.
7.4.2 OS/ALERT (OS)
The TMP100-Q1 and TMP101-Q1 devices feature a One-Shot Temperature Measurement Mode. When the
device is in Shutdown Mode, writing 1 to the OS/ALERT bit starts a single temperature conversion. The device
returns to the shutdown state at the completion of the single conversion. This feature is useful to reduce power
consumption in the TMP100-Q1 and TMP101-Q1 devices when continuous monitoring of temperature is not
required.
Reading the OS/ALERT bit provides information about the Comparator Mode status. The state of the POL bit
inverts the polarity of data returned from the OS/ALERT bit. For POL = 0, the OS/ALERT reads as 1 until the
temperature equals or exceeds THIGH for the programmed number of consecutive faults, causing the OS/ALERT
bit to read as 0. The OS/ALERT bit continues to read as 0 until the temperature falls below TLOW for the
programmed number of consecutive faults when the OS/ALERT bit again reads as 1. The status of the TM bit
does not affect the status of the OS/ALERT bit.
7.4.3 Thermostat Mode (TM)
The Thermostat Mode bit of the TMP101-Q1 device indicates to the device whether to operate in Comparator
Mode (TM = 0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see the
High- and Low-Limit Registers section.
7.4.4 Comparator Mode (TM = 0)
In Comparator Mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in
the THIGH register and remains active until the temperature falls below the value in the TLOW register. For more
information on the Comparator Mode, see the High- and Low-Limit Registers section.
7.4.5 Interrupt Mode (TM = 1)
In Interrupt Mode (TM = 1), the ALERT pin is activated when the temperature exceeds THIGH or goes below
the TLOW registers. The ALERT pin is cleared when the host controller reads the temperature register. For more
information on the interrupt mode, see the High- and Low-Limit Registers section.
7.5 Programming
7.5.1 Pointer Register
Figure 7-7 shows the internal register structure of the TMP100-Q1 and TMP101-Q1 devices. The 8-bit Pointer
Register of the TMP100-Q1 and TMP101-Q1 devices is used to address a given data register. The Pointer
Register uses the two LSBs to identify which of the data registers respond to a read or write command. Table 7-4

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identifies the bits of the Pointer Register byte. Table 7-5 describes the pointer address of the registers available
in the TMP100-Q1 and TMP101-Q1 devices. The power-up reset value of P1 and P0 is 00.

Pointer
Register

Temperature
Register

SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA

THIGH
Register

Figure 7-7. Internal Register Structure of the TMP100-Q1 and TMP101-Q1

7.5.1.1 Pointer Register Byte (pointer = N/A) [reset = 00h]

Table 7-4. Pointer Register Byte
P7 P6 P5 P4 P3 P2 P1 P0
0 0 0 0 0 0 Register Bits

7.5.1.2 Pointer Addresses of the TMP100-Q1 and TMP101-Q1 Registers

Table 7-5. Pointer Addresses of the TMP100-Q1 and TMP101-Q1 Registers
P1 P0 TYPE REGISTER
0 0 R only, default Temperature Register
0 1 R/W Configuration Register
1 0 R/W TLOW Register
1 1 R/W THIGH Register

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7.5.2 Temperature Register

The Temperature Register of the TMP100-Q1 or TMP101-Q1 devices is a 12-bit, read-only register that stores
the output of the most recent conversion. Two bytes must be read to obtain data, and are described in Table
7-6 and Table 7-7. The first 12 bits are used to indicate temperature, with all remaining bits equal to zero. Data
format for temperature is summarized in Table 7-1. Following power-up or reset, the Temperature Register reads
0°C until the first conversion is complete.
Table 7-6. Byte 1 of the Temperature Register
D7 D6 D5 D4 D3 D2 D1 D0
T11 T10 T9 T8 T7 T6 T5 T4

Table 7-7. Byte 2 of the Temperature Register

D7 D6 D5 D4 D3 D2 D1 D0
T3 T2 T1 T0 0 0 0 0

7.5.3 Configuration Register

The Configuration Register is an 8-bit read and write register used to store bits that control the operational
modes of the temperature sensor. Read and write operations are performed MSB-first. The format of the
Configuration Register for the TMP100-Q1 and TMP101-Q1 devices is shown in Table 7-8, followed by a
breakdown of the register bits. The power-up or reset value of the Configuration Register is all bits equal to 0.
The OS/ALERT bit reads as 1 after power-up or reset value.
Table 7-8. Configuration Register Format
BYTE D7 D6 D5 D4 D3 D2 D1 D0
1 OS/ALERT R1 R0 F1 F0 POL TM SD

7.5.3.1 Shutdown Mode (SD)

The Shutdown Mode of the TMP100-Q1 and TMP101-Q1 devices allows the user to save maximum power
by shutting down all device circuitry other than the serial interface, which reduces current consumption to less
than 1 µA. For the TMP100-Q1 and TMP101-Q1 devices, Shutdown Mode is enabled when the SD bit is 1.
The device shuts down when the current conversion is completed. For SD equal to 0, the device maintains
continuous conversion.
7.5.3.2 Thermostat Mode (TM)
The Thermostat Mode bit of the TMP101-Q1 device indicates to the device whether to operate in Comparator
Mode (TM = 0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see High-
and Low-Limit Registers.
7.5.3.3 Polarity (POL)
The Polarity bit of the TMP101-Q1 device lets the user adjust the polarity of the ALERT pin output. If the POL bit
is set to 0 (default), the ALERT pin becomes active low. When the POL bit is set to 1, the ALERT pin becomes
active high and the state of the ALERT pin is inverted. The operation of the ALERT pin in various modes is
illustrated in Figure 7-8.

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THIGH
Measured
Temperature

TLOW

TMP101-Q1ALERT PIN
(Comparator Mode)
POL = 0
TMP101-Q1ALERT PIN
(Interrupt Mode)
POL = 0
TMP101-Q1ALERT PIN
(Comparator Mode)
POL = 1
TMP101-Q1ALERT PIN
(Interrupt Mode)
POL = 1

Read Read Read

Time

Figure 7-8. Output Transfer Function Diagrams

7.5.3.4 Fault Queue (F1, F0)

A fault condition occurs when the measured temperature exceeds the user-defined limits set in the THIGH and
TLOW Registers. Additionally, the number of fault conditions required to generate an alert can be programmed
using the Fault Queue. The Fault Queue is provided to prevent a false alert resulting from environmental
noise. The Fault Queue requires consecutive fault measurements in order to trigger the alert function. If the
temperature falls below TLOW before reaching the number of programmed consecutive faults limit, the count is
reset to 0. Table 7-9 defines the number of measured faults that can be programmed to trigger an alert condition
in the device.
Table 7-9. Fault Settings of the TMP100-Q1 and TMP101-Q1
F1 F0 CONSECUTIVE FAULTS
0 0 1
0 1 2
1 0 4
1 1 6

7.5.3.5 Converter Resolution (R1, R0)

The Converter Resolution bits control the resolution of the internal analog-to-digital converter (ADC), thus
allowing the user to maximize efficiency by programming for higher resolution or faster conversion time. Table
7-10 identifies the Resolution bits and the relationship between resolution and conversion time.
Table 7-10. Resolution of the TMP100-Q1 and TMP101-Q1
CONVERSION TIME
R1 R0 RESOLUTION
(Typical)
0 0 9 bits (0.5°C) 40 ms
0 1 10 bits (0.25°C) 80 ms
1 0 11 bits (0.125°C) 160 ms
1 1 12 bits (0.0625°C) 320 ms

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7.5.3.6 OS/ALERT (OS)

The TMP100-Q1 and TMP101-Q1 devices feature a One-Shot Temperature Measurement Mode. When the
device is in Shutdown Mode, writing 1 to the OS/ALERT bit starts a single temperature conversion. The device
returns to the shutdown state at the completion of the single conversion. This feature is useful to reduce power
consumption in the TMP100-Q1 and TMP101-Q1 when continuous temperature monitoring is not required.
Reading the OS/ALERT bit provides information about the Comparator Mode status. The state of the POL bit
inverts the polarity of data returned from the OS/ALERT bit. For POL = 0, the OS/ALERT reads as 1 until the
temperature equals or exceeds THIGH for the programmed number of consecutive faults, causing the OS/ALERT
bit to read as 0. The OS/ALERT bit continues to read as 0 until the temperature falls below TLOW for the
programmed number of consecutive faults when the OS/ALERT bit again reads as 1. The status of the TM bit
does not affect the status of the OS/ALERT bit.
7.5.4 High- and Low-Limit Registers
In Comparator Mode (TM = 0), the ALERT pin of the TMP101-Q1 becomes active when the temperature equals
or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0.
The ALERT pin remains active until the temperature falls below the indicated TLOW value for the same number of
faults.
In Interrupt Mode (TM = 1) the ALERT pin becomes active when the temperature equals or exceeds THIGH for
a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register
occurs or the device successfully responds to the SMBus Alert Response Address. The ALERT pin is also
cleared if the device is placed in Shutdown Mode. When the ALERT pin is cleared, it only becomes active again
by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin becomes active
and remains active until cleared by a read operation of any register or a successful response to the SMBus Alert
Response Address. When the ALERT pin is cleared, the above cycle repeats with the ALERT pin becoming
active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the
device with the General Call Reset command. This action also clears the state of the internal registers in the
device, returning the device to Comparator Mode (TM = 0).
Both operational modes are represented in Figure 7-8. Table 7-11, Table 7-12, Table 7-13, and Table 7-14
describe the format for the THIGH and TLOW registers. Power-up reset values for THIGH and TLOW are: THIGH =
80°C and TLOW = 75°C. The format of the data for THIGH and TLOW is the same as for the Temperature Register.
Table 7-11. Byte 1 of the THIGH Register
D7 D6 D5 D4 D3 D2 D1 D0
H11 H10 H9 H8 H7 H6 H5 H4

Table 7-12. Byte 2 of the THIGH Register

D7 D6 D5 D4 D3 D2 D1 D0
H3 H2 H1 H0 0 0 0 0

Table 7-13. Byte 1 of the TLOW Register

D7 D6 D5 D4 D3 D2 D1 D0
L11 L10 L9 L8 L7 L6 L5 L4

Table 7-14. Byte 2 of the TLOW Register

D7 D6 D5 D4 D3 D2 D1 D0
L3 L2 L1 L0 0 0 0 0

All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function
for all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the
converter is configured for 9-bit resolution.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The TMP100-Q1 and TMP101-Q1 devices are used to measure the printed circuit board (PCB) temperature of
the board location where the devices are mounted. The TMP100-Q1 features two address pins to allow up to
eight devices to be addressed on a single I2C interface. The TMP101-Q1 device features one address pin and
an ALERT pin, allowing up to three devices to be connected per bus. The TMP100-Q1 and TMP101-Q1 devices
require no external components for operation except for pullup resistors on SCL, SDA, and ALERT (TMP101-Q1
device), although a 0.1-μF bypass capacitor is recommended.
The sensing device of the TMP100-Q1 and TMP101-Q1 devices is the chip itself. Thermal paths run through
the package leads as well as the plastic package. The die flag of the lead frame is connected to GND. The
lower thermal resistance of metal causes the leads to provide the primary thermal path. The GND pin of the
TMP100-Q1 or TMP101-Q1 device is directly connected to the metal lead frame, and is the best choice for
thermal input.
8.2 Typical Application
Supply Voltage Supply Voltage
2.7 V to 5.5 V 2.7 V to 5.5 V

Supply Bypass Supply Bypass

Capacitor Capacitor
Pull-Up Resistors 0.01 µF Pull-Up Resistors 0.01 µF
5-kΩ 5-kΩ

TMP100-Q1 TMP101-Q1
Two-Wire 1 6 Two-Wire 1 6
Host Controller SCL SDA Host Controller SCL SDA

2 5 2 5
GND ADD0 GND ADD0

3 4 3 4
ADD1 V+ ALERT V+

Figure 8-1. Typical Connections of the TMP100-Q1 Figure 8-2. Typical Connections of the TMP101-Q1

8.2.1 Design Requirements

The TMP100-Q1 and TMP101-Q1 devices require pullup resistors on the SCL, SDA, and ALERT (TMP101-Q1
device) pins. The recommended value for the pullup resistor is 5-kΩ. In some applications, the pullup resistor
can be lower or higher than 5-kΩ but must not exceed 3 mA of current on the SCL and SDA pins, and must not
exceed 4 mA on the ALERT (TMP101-Q1) pin. A 0.1-μF bypass capacitor is recommended, as shown in Figure
8-1 and Figure 8-2. The SCL, SDA, and ALERT lines can be pulled up to a supply that is equal to or higher than
VS through the pullup resistors. For the TMP100-Q1, to configure one of eight different addresses on the bus,
connect ADD0 and ADD1 to either the GND pin, V+ pin, or float. Float indicates the pin is left unconnected. For
the TMP101-Q1 device, to configure one of three different addresses on the bus, connect ADD0 to either the
GND pin, V+ pin, or float.
8.2.2 Detailed Design Procedure
Place the TMP100-Q1 and TMP101-Q1 devices in close proximity to the heat source that must be monitored,
with a proper layout for good thermal coupling. This placement ensures that temperature changes are captured

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within the shortest possible time interval. To maintain accuracy in applications that require air or surface
temperature measurement, care must be taken to isolate the package and leads from ambient air temperature. A
thermally-conductive adhesive is helpful in achieving accurate surface temperature measurement.
8.2.3 Application Curve
Figure 8-3 shows the step response of the TMP100-Q1 and TMP101-Q1 devices to a submersion in an oil bath
of 100°C from room temperature (27°C). The time constant, or the time for the output to reach 63% of the input
step, is 0.9 s. The time-constant result depends on the PCB that the TMP100-Q1 and TMP101-Q1 devices are
mounted. For this test, the TMP100-Q1 and TMP101-Q1 devices are soldered to a two-layer PCB that measures
0.375 inch × 0.437 inch.
100
95
90
85
80
Temperature (qC)

75
70
65
60
55
50
45
40
35
30
25
-1 1 3 5 7 9 11 13 15 17 19
Time (s)

Figure 8-3. Temperature Step Response

9 Power Supply Recommendations

The TMP100-Q1 and TMP101-Q1 devices operate with power supply in the range of 2.7 V to 5.5 V. A power-
supply bypass capacitor is required for stability; place this capacitor as close as possible to the supply and
ground pins of the device. A typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or
high-impedance power supplies can require additional decoupling capacitors to reject power-supply noise.

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10 Layout
10.1 Layout Guidelines
Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The recommended
value of this bypass capacitor is 0.01 μF. Additional decoupling capacitance can be added to compensate for
noisy or high-impedance power supplies. Pull up the open-drain output pins SDA , SCL, and ALERT (TMP101-
Q1) through 5-kΩ pullup resistors.
10.2 Layout Examples
Via to Power or Ground Plane

Via to Internal Layer

Pull-Up Resistors

SCL SDA

GND ADD0
Supply Voltage

ADD1 V+
Supply Bypass
Capacitor

Ground Plane for

Thermal Coupling
to Heat Source

Serial Bus Traces

Heat Source

Figure 10-1. TMP100-Q1 Layout Example

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Via to Power or Ground Plane

Via to Internal Layer

Pull-Up Resistors

SCL SDA

GND ADD0

Supply Voltage
ALERT V+

Supply Bypass
Capacitor

Ground Plane for

Thermal Coupling
to Heat Source

Serial Bus Traces

Heat Source

Figure 10-2. TMP101-Q1 Layout Example

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11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
SMBus™ is a trademark of NXP Semiconductors.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TMP100AQDBVRQ1 Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 100Q
TMP100AQDBVRQ1.B Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 100Q
TMP101NAQDBVRQ1 Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 DUGQ
TMP101NAQDBVRQ1.B Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 DUGQ

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TMP100-Q1, TMP101-Q1 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

• Catalog : TMP100, TMP101

• Enhanced Product : TMP100-EP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP100AQDBVRQ1 SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TMP101NAQDBVRQ1 SOT-23 DBV 6 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMP100AQDBVRQ1 SOT-23 DBV 6 3000 445.0 220.0 345.0
TMP101NAQDBVRQ1 SOT-23 DBV 6 3000 445.0 220.0 345.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214840/G 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

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 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/G 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/G 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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