®

RT8125E

High Efficiency Single Synchronous Buck PWM Controller

General Description Features
The RT8125E PWM controller provides high efficiency,  Richtek Mach ResponseTM Technology
excellent transient response, and high DC output accuracy  1% High Accuracy 0.8V Reference
needed for CPU core, I/O, and chipset RAM supplies in  VCC Input Range : 4.5V to 13.2V
notebook computers.  VOUT Operating Range : 0.3V to 3.3V
 Power Stage Input Range : 1.5V to 24V
Richtek Mach ResponseTM technology is specifically
 Fixed Operating Frequency : 300kHz
designed for providing 100ns “instant-on” response to
 VIN Detection
load transients while maintaining a relatively constant
 LG_OCSET for Current Limit
switching frequency.
 PGOOD Indicator
The RT8125E achieves high efficiency at a reduced cost  Embedded Bootstrap Switch
by eliminating the current sense resistor found in  Ω)
High Side Gate Driver Pull Low Resistor (10kΩ
traditional current mode PWMs. Efficiency is further  Current Limit with Low Side Current Sense Scheme
enhanced by its ability to drive very large synchronous  Enable Function with Internal Pull High Current
rectifier MOSFETs. The Buck conversion allows this device  OVP/UVP/OTP/Pre-OVP/Current Limit
to directly step down high voltage batteries at the highest  Shutdown Current <100μ μA
possible efficiency. The RT8125E provides an 1% high  RoHS Compliant and Halogen Free
accuracy 0.8V reference voltage with minimum 1mA
source/sink current for high accuracy output application. Applications
 Generic DC/DC Power Regulator
Pin Configurations  Mother Boards and Desktop Servers
(TOP VIEW)
BOOT 1 10 REFOUT
UGATE 2 9 REFIN
GND

PHASE 3 8 PGOOD
LGATE/OCSET 4 7 EN
VCC 5 11 6 FB

WDFN-10L 3x3

Simplified Application Circuit

VIN
VCC VCC
RT8125E

UGATE
Enable EN
BOOT
PGOOD PGOOD
PHASE VOUT
REFOUT LGATE/
OCSET

REFIN FB
GND

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RT8125E
Ordering Information Marking Information
RT8125E 8Y= : Product code
8Y=YM YMDNN : Date code
Package Type DNN
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)

Note :
Richtek products are :
 RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
 Suitable for use in SnPb or Pb-free soldering processes.

Functional Pin Description

Pin No. Pin Name Pin Function
Bootstrap Supply for High Side Gate Driver. Connect a capacitor between
1 BOOT
this pin and the PHASE pin.
2 UGATE Gate Drive Output for the External High Side MOSFET.
Switch Node. It behaves as the current sense comparator input for low side
3 PHASE
MOSFET RDS(ON) sensing and reference voltage for on-time generation.
Gate Drive Output for the Low Side External MOSFET. Connect a resistor
(ROCSET) between this pin and GND to set the output current limit level. If
4 LGATE/OCSET
ROCSET is not present , or the setting threshold greater than 400mV, the OC
threshold is internally present to 315mV (typ.)
Supply Voltage Input. It provides the power for the Buck controller, the low
5 VCC side driver and the bootstrap circuit for high side driver. Bypass to GND with
a 4.7F ceramic capacitor.
VOUT Feedback Voltage Input. Connect the FB to a resistive voltage divider
6 FB
from VOUT to GND to set the output voltage from 0.3V to 3.3V
7 EN Enable Control Input.
Open-drain Power Good Indicator. High impedance indicates that power is
8 PGOOD
good.
Reference Input. Connect a current console to REFIN pin, and connect a
9 REFIN resistor between REFIN and REFOUT to tune up/down FB reference
voltage.
Reference Voltage Output. It provides an 1% high accuracy reference 0.8V
10 REFOUT with 2mA source/sink ability. Bypass to GND with a maximum 6.8nF ceramic
capacitor.
11 Ground. The exposed pad must be soldered to a large PCB and connected
GND
(Exposed Pad) to GND for maximum power dissipation.

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 RT8125E
Function Block Diagram

On-time
PHASE One Shot
R BOOT
VREF
REFIN +
+
- S Q UGATE
Comp
PHASE
Minimum TOFF VCC

+ OVP
Latch LGATE/OCSET
125% VREF -
GND
FB - UVP Thermal
50% VREF + Hiccup Shutdown

-
90% VREF + Sample
LDO + and Hold
VCC SS REF + Gm
& POR -
-
VIN
Detection + VDET
-

EN REFOUT PGOOD

Operation
The RT8125E is suitable for low external component count constant over the entire input voltage range. Another one-
configuration with appropriate amount of Equivalent Series shot sets a minimum off-time (400ns typ.).
Resistance (ESR) capacitor(s) at the output. The output The on-time comparator has two inputs, one is from the
ripple valley voltage is monitored at a feedback point output voltage, the other is from the input voltage. The on-
voltage. The synchronous high side MOSFET is turned time of the high side switch is designed to be directly
on at the beginning of each cycle. After the internal one- proportional to the output voltage and inversely proportional
shot timer expires, the MOSFET is turned off. The pulse to the input voltage. The implementation results in a nearly
width of this one-shot is determined by the converter's constant switching frequency without the need of a clock
input and output voltages to keep the frequency fairly generator.

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RT8125E
Absolute Maximum Ratings (Note 1)
 VCC to GND ---------------------------------------------------------------------------------------------------------------- −0.3V to 15V
 PGOOD, FB, EN, REFOUT, REFIN ---------------------------------------------------------------------------------- −0.3V to 6.5V
 BOOT to GND -------------------------------------------------------------------------------------------------------------- −0.3V to 40V
< 100ns ---------------------------------------------------------------------------------------------------------------------- −0.3V to 45V
 BOOT to PHASE ---------------------------------------------------------------------------------------------------------- −0.3V to 15V
< 100ns ---------------------------------------------------------------------------------------------------------------------- −0.3V to 20V
 PHASE to GND

DC ----------------------------------------------------------------------------------------------------------------------------- −5V to 25V

< 100ns ---------------------------------------------------------------------------------------------------------------------- −10V to 30V
 UGATE to GND ------------------------------------------------------------------------------------------------------------ −0.3V to 40V
< 100ns ---------------------------------------------------------------------------------------------------------------------- −10V to 45V
 UGATE to PHASE

DC ----------------------------------------------------------------------------------------------------------------------------- 0.3V to 15V

< 100ns ---------------------------------------------------------------------------------------------------------------------- −5V to 20V
 LGATE to GND

DC ----------------------------------------------------------------------------------------------------------------------------- −0.3V to 15V

< 100ns ---------------------------------------------------------------------------------------------------------------------- −5V to 20V
 Power Dissipation, PD @ TA = 25°C

WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------- 3.27W

 Package Thermal Resistance (Note 2)

WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------- 30.5°C/W

WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------- 7.5°C/W
 Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
 Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
 Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)

HBM (Human Body Model) ---------------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 Input Voltage, VIN --------------------------------------------------------------------------------------------------------- 1.5V to 24V
 Supply Voltage, VCC ----------------------------------------------------------------------------------------------------- 4.5V to 13.2V
 Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C

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 RT8125E
Electrical Characteristics
(VCC = 5V, VIN = 15V, EN = 5V, TA = 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

PWM Controller
Rising Edge 3.75 4.1 4.5
VCC POR Threshold V
Falling Edge -- 3.8 4
VCC Quiescent Supply FB Forced above the Regulation
IQ -- 500 1250 A
Current Point, EN = 5V, REFOUT Current = 0
VCC Shutdown Current ISHDN VCC Current, EN = 0V -- -- 100 A
VCC = 4.5V to 13.2V, Sink/ Source
REFOUT (Note 5) VREFOUT 786 794 802 mV
Current = 2mA
REFOUT Source / Sink
IREFOUT -- -- 2 mA
Current
FB Input Bias Current FB = 0.8V 1 0 1 A
REFIN Input Voltage Range 0.3 -- 3.3 V
Switching Frequency (Note 6) 270 300 330 kHz
Minimum Off-Time 250 -- -- ns
Current Sensing
IOCSET 9 10 11 A
Soft-Start Time TSS REFIN = 0.8V, No Load -- 0.7 -- ms
Protection Function
Current Limit Setting Range LGATE 50 -- 400 mV
Current Limit Threshold ROCSET NC -- 315 -- mV
UVP Detect, FB Lower than REFIN
UV Threshold 225 300 375 mV
Voltage
OVP Detect, FB Higher than REFIN
OVP Threshold 225 300 375 mV
Voltage
REFIN Absolute OVP
3.35 3.5 -- V
Threshold
Thermal Shutdown Latch -- 140 -- C
VIN Detection Threshold VDET 0.5 -- -- V
Driver On-Resistance
VBOOT  VPHASE = 12V, Source
UGATE Driver Source RUGATEsr -- 1.5 3 
Current = 100mA
UGATE Driver Sink RUGATEsk BOOT  PHASE = 12V, ISINK = 10mA -- 2.25 4 
LGATE Driver Source RLGATEsr VCC = 12V, Source Current = 100mA -- 1.5 3 
LGATE Driver Sink RLGATEsk VCC = 12V, ISINK = 10mA -- 1 2 
LGATE Rising (PHASE = 1.5V) -- 30 -- ns
Dead Time
UGATE Rising -- 30 --
Internal Boost Charging
VCC to BOOT, 10mA -- -- 80 
Switch On-Resistance

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RT8125E
Parameter Symbol Test Conditions Min Typ Max Unit
EN Threshold
EN Internal Pull High Current EN = 0V 5 -- -- A

Enable Input Logic-High VIH 2.4 -- 5.5

V
Voltage Logic-Low VIL -- -- 0.4
PGOOD (PGOOD High w/o OVP or UVP)
PGOOD Blanking Time PGOOD Rising Edge After Soft-Start 1 3 5 ms
Output Low Voltage ISINK = 4mA -- -- 0.3 V
Leakage Current High State, Forced to 5V -- -- 1 A

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. The reference voltage shift -6mV from 0.8V for offset canceling under feedback valley control.
Note 6. No production tested. Test condition VIN = 8V, VOUT = 1.1V, IOUT = 10A using application circuit.

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 RT8125E
Typical Application Circuit

5 VIN
VCC VCC
4.7µF RT8125E
7 2
Enable EN UGATE
100k BOOT 1
5V 0.1µF
8 PGOOD PHASE 3
PGOOD VOUT
10
REFOUT LGATE/ 4
OCSET
ROCSET
9 FB 6
REFIN
GND
11 (Exposed Pad)

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RT8125E
Typical Operating Characteristics
Efficiency vs. Load Current Output Voltage vs. Load Current
100 1.55
90 1.54
80 1.53

Output Voltage (V)

70 1.52
Efficiency (%)

60 1.51
50 1.50
40 1.49
30 1.48
20 1.47
10 1.46
VIN = VCC = 12V, VOUT = 1.5V VIN = VCC = 12V
0 1.45
0.01 0.1 1 10 100 0 2 4 6 8 10 12 14 16 18 20
Load Current (A) Load Current (A)

Frequency vs. Load Current TON vs. Temperature

450 500

400
480
350
Frequency (kHz)1

460
300
TON (ns)

250 440

200 420
150
400
100
380
50
VIN = VCC = 12V, VOUT = 1.5V VIN = VCC = 12V, VOUT = 1.5V, No Load
0 360
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
Load Current (A) Temperature (°C)

Output Voltage vs. Temperature Load Transient Response

1.55
1.54 VOUT (100mV/Div)
1.53
Output Voltage (V)

1.52
1.51
1.50
1.49
1.48
1.47 IOUT (10A/Div)
1.46
VIN = VCC = 12V, No Load VIN = VCC = 12V, VOUT = 1.5V
1.45
-50 -25 0 25 50 75 100 125 Time (200μs/Div)
Temperature (°C)

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 RT8125E

Power On from EN Power Off from EN

EN EN
(5V/Div) (5V/Div)

VOUT VOUT
(1V/Div) (1V/Div)
PGOOD PGOOD
(10V/Div) (10V/Div)

UGATE UGATE
(20V/Div) VIN = VCC = 12V, IOUT = 50mA (20V/Div) VIN = VCC = 12V, IOUT = 10A

Time (1ms/Div) Time (100μs/Div)

Dynamic Output Voltage Control Dynamic Output Voltage Control

VOUT (100mV/Div)

VOUT (100mV/Div)

VREFIN (200mV/Div)
VREFIN (200mV/Div)

VIN = VCC = 12V, VIN = VCC = 12V,

IREFIN = 50μA x 1steps, IOUT = 10A IREFIN = -10μA x 5steps, IOUT = 10A

Time (20μs/Div) Time (200μs/Div)

OVP

VFB
(1V/Div)

VOUT
(1V/Div)

PGOOD
(5V/Div)
LGATE
(20V/Div) VIN = VCC = 12V

Time (100μs/Div)

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RT8125E
Application Information
VIN Detection
The RT8125E PWM controller provides high efficiency,
excellent transient response, and high DC output accuracy Once VCC exceeds its power on reset (POR) rising
needed for CPU core, I/O, and chipset RAM supplies in threshold voltage and the EN pin is set free, UGATE will
notebook computers. Richtek Mach Response TM output continuous pulses (~40kHz, 100ns), and LGATE
technology is specifically designed for providing 100ns will be forced low for converter input voltage VIN detection.
“instant-on” response to load steps while maintaining a If the voltage pulses at the PHASE pin are less than
relatively constant operating frequency and inductor VIN detection threshold (VDET) when UGATE is turned off
operating point over a wide range of input voltages. The more than 3 cycles, VIN is recognized as ready. Then,
topology solves the poor load transient response timing the controller will initiate soft-start operation. For ensuring
problems of fixed frequency current mode PWMs and the VIN can be defected, the Phase to GND can't place
avoids the problems caused by widely varying switching schottky diode to avoid the phase voltage will be clamped
frequencies in conventional constant on-time and constant to around -0.3V.
off-time PWM schemes.
Internal Soft-Start
Supply Voltage and Power On Reset (POR) The RT8125E provides an internal soft-start function. The
The input voltage range for VCC is from 4.5 V to 13.2 V soft-start function is used to prevent large inrush current
with respect to GND. An internal linear regulator regulates and output voltage overshoot while the converter is being
the supply voltage for internal control logic circuit. A powered-up. The soft-start function automatically begins
minimum 0.1μF ceramic capacitor is recommended to once the chip is enabled. An internal current source
bypass the supply voltage. Place the bypassing capacitor charges the internal soft-start capacitor such that the
near the IC. VCC also supplies the integrated MOSFET internal soft-start voltage ramps up uniformly. The FB
drivers. A bootstrap diode is embedded to facilitate PCB voltage will track the internal soft-start voltage during the
design and reduce the total BOM cost. No external soft-start interval. After the internal soft-start voltage
Schottky diode is required in real applications. exceeds the reference voltage, the FB voltage no longer
tracks the soft-start voltage but rather follows the reference
The Power On Reset (POR) circuit monitors the supply
voltage. Therefore, the duty cycle of the UGATE signal as
voltage at the VCC pin. If VCC exceeds the POR rising
well as the input current at power up are limited.
threshold voltage (4.2V typ.), the controller resets and
prepares the PWM for operation. If VCC falls below the
POR falling threshold during normal operation, all
MOSFETs stop switching. The POR rising and falling
threshold has a hysteresis (0.12V typ.) to prevent
unintentional noise based reset.

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 RT8125E

POR POR
VCC threshold threshold

EN

LGATE

UGATE

3.3V

0.8V

Internal
SS

FB

PGOOD Soft-Start
(TSS)

Normal Operation LG turns on to

OCP VIN PGOOD discharge output
Programming Detection Blanking Time voltage

Figure 1. Soft-Start Timing Chart

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RT8125E
Soft Discharge Current Limit
When VCC is less than POR falling threshold or EN goes The RT8125E provides lossless over current protection
low, the discharging mode will active. During discharging by detecting the voltage drop across the low side MOSFET
mode, LGATE will deliver discharging pulse and an internal when it is turned on. The over current trip threshold is set
switch from FB to GND will also create a path for by an external resistor, ROCSET, at LGATE. During LGATE
discharging the output capacitor's residual charge to GND is turned on, the RT8125E senses the PHASE voltage
until the phase pin voltage below 0.7V. and compares to the OCP threshold. If the sensed PHASE
voltage is lower than the OCP threshold, OCP will be
Output Voltage Setting triggered. When OCP is triggered, LGATE will turn on to
The RT8125E supports external reference input to provide prevent inductor current from increasing until the OCP
more flexible applications. The REFIN pin and REFOUT condition is released.
pin are implemented to be external reference input
function. The RT8125E allows the output voltage of the Current Limit Setting
DC/DC converter to be adjusted via an external resistor Over current threshold is externally programmed by adding
divider. It will try to maintain the feedback pin at REFIN a resistor (ROCSET) between LGATE and GND. Once VCC
pin input voltage. exceeds the POR threshold and the EN pin is enabled,
an internal current source IOCSET flows through ROCSET.
VOUT For maintain the OCP threshold accuracy while
temperature variation, the current source (IOCSET) has an
RFB1 approximately 4500ppm/°C temperature slope to
FB compensate the dependency of RDS(ON) of MOSFET. The
RFB2 voltage across ROCSET is stored as the over current
protection threshold VOCSET. After that, the current source
Figure 2. Output Voltage Setting is switched off. ROCSET can be determined using the
following equation :
V
IVALLEY  RLGDS(ON)
ROCSET =
 VOUT IOCSET
where IVALLEY represents the desired inductor OCP trip
VOUT
current (valley inductor current). If ROCSET is not present,
VVal
there is no current path for IOCSET to build the OCP
threshold. In this situation, the OCP threshold is internally
t preset to 315mV (typical).
tON
For RT8125E, the OCP threshold in soft-start period will
Figure 3. Output Voltage Waveform
be reduced ot half of setting value. For example, if the
desired OCP threshold is 30A,the OCP threshold will be
According to the resistor divider network above, the output
15A during soft-start period. For RT8125E, the OCP
voltage is set as :
 threshold is same as steady state during soft-stare period.
 R   V
VOUT =  VREFOUT   1 FB1    OUT
  RFB2   2 For ensure current limit threshold accuracy, the Ciss of
low-side MOSFET must less than 8nF.
Note that the reference voltage at DEM is exceeds than
CCM threshold 1%.

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 RT8125E
Over Voltage Protection (OVP) Comp
FB - UVP
The output voltage is scaled by the divider resistors and 50% + Hiccup
VREF
fed back to the FB pin. The voltage on the FB pin will be
compared with the REFIN Voltage. For voltage related UVP
protection functions, including over voltage protection and Threshold

under voltage protection. If the FB voltage is higher than

FB
the OVP threshold during operation, OVP will be triggered.
When OVP is triggered, UGATE will go low and LGATE
UGATE
will go high to discharge the output capacitor. Once OVP
is triggered, controller will be latched unless VCC POR is
LGATE
detected again or EN pin is reset.
Comp Delay Time OCP VIN
FB + OVP (36µs typ.) Programming Detection
125% - Latch
VREF Figure 5. UVP Operation

MOSFET Drivers
OVP
Threshold The RT8125E integrates high current gate drivers for the
two N-MOSFETs to obtain high efficiency power conversion
FB
in synchronous Buck topology. A dead time is used to
prevent crossover conduction for the high side and low
UGATE Latch
side MOSFETs. Because both gate signals are off during
dead time, the inductor current freewheels through the
LGATE
body diode of the low side MOSFET. The freewheeling
Delay Time current and the forward voltage of the body diode contribute
(36µs typ.) to power loss. The RT8125E employs constant dead time
Figure 4. OVP Operation control scheme to ensure safe operation without
sacrificing efficiency. Furthermore, elaborate logic circuit
is implemented to prevent cross conduction.
Under Voltage Protection (UVP)
The voltage on the FB pin is monitored for under voltage For high output current applications, two or more power
protection. Controller begins to detect UVP after soft-start MOSFETs are usually paralleled to reduce RDS(ON). The
finish. If the FB voltage is lower than the UVP threshold gate driver needs to provide more current to switch on/off
during normal operation, UVP will be triggered. When the these paralleled MOSFETs. Gate driver with lower source/
UVP is triggered, both UGATE and LGATE will go low the sink current capability result in longer rising/falling time
RT8125E will enter hiccup mode and continuously try to in gate signals, and therefore higher switching loss.
restart until the UVP situation is removed. The RT8125E embeds high current gate drivers to obtain
high efficiency power conversion. The embedded drivers
contribute to the majority of the power dissipation of the
controller. Therefore, WDFN package is chosen for its
power dissipation rating. If no gate resistor is used, the
power dissipation of the controller can be approximately
calculated using the following equation :
PDRIVER
= fSW   QG  VBOOT  QG_Low Side  VDRIVER_Low Side 

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RT8125E
where VBOOT represents the voltage across the bootstrap The next step is to select a proper capacitor for the RMS
capacitor and fSW is the switching frequency. It is important current rating. Using more than one capacitor with low
to ensure the package can dissipate the switching loss Equivalent Series Resistance (ESR) in parallel to form a
and have enough room for safe operation. capacitor bank is a good design. Placing a ceramic
capacitor close to the drain of the high side MOSFET can
Inductor Selection also be helpful in reducing the input voltage ripple at heavy
The inductor plays an important role in step-down load.
converters because it stores the energy from the input
power rail and then releases the energy to the load. From Output Capacitor Selection
the viewpoint of efficiency, the DC Resistance (DCR) of The output capacitor and the inductor form a low-pass filter
the inductor should be as small as possible to minimize in the Buck topology. In steady state condition, the ripple
the conduction loss. In addition, the inductor covers a current flowing into/out of the capacitor results in voltage
significant proportion of the board space, so its size is ripple. The output voltage ripples contains two
also important. Low profile inductors can save board space components, ΔVOUT_ESR and ΔVOUT_C.
especially when the height has a limitation. However, low VOUT_ESR = IL  ESR
DCR and low profile inductors are usually not cost effective. 1
VOUT_C = IL 
8  COUT  fSW
Additionally, larger inductance results in lower ripple
When load transient occurs, the output capacitor supplies
current, which translates into the lower power loss. The
the load current before controller can respond. Therefore,
inductor current rising time increases with inductance value.
the ESR will dominate the output voltage sag during load
This means the transient response will be slower. Therefore,
transient. The output voltage sag can be calculated using
the inductor design is a trade-off among performance, size
the following equation :
and cost.
VOUT_SAG = ESR  IOUT
In general, inductance is chosen such that the ripple
current ranges between 20% to 40% of the full load current. For a given output voltage sag specification, the ESR value
The inductance can be calculated using the following can be determined.
equation : Another parameter that has influence on the output voltage
VIN  VOUT V sag is the equivalent series inductance (ESL). The rapid
L(MIN) =  OUT
fSW  k  IOUT_Full Load VIN change in load current results in di/dt during transient.
where k is the ratio between inductor ripple current and
Therefore ESL contributes to part of the voltage sag. Using
rated output current.
a capacitor with low ESL will obtain better transient
Input Capacitor Selection performance. Generally, using several capacitors
connected in parallel will also have better transient
Voltage rating and current rating are the key parameters
performance than just one single capacitor with the same
when selecting an input capacitor. Conservatively speaking,
total ESR.
an input capacitor should have a voltage rating 1.5 times
greater than the maximum input voltage to be considered Unlike electrolytic capacitors, the ceramic capacitor has
a safe design. The input capacitor is used to supply the relatively low ESR and can reduce the voltage deviation
input RMS current, which can be approximately calculated during load transient. However, the ceramic capacitor can
using the following equation : only provide low capacitance value. Therefore, it is
suggested to use a mixed combination of electrolytic
VOUT  VOUT 
IRMS = IOUT   1 capacitor and ceramic capacitor for achieving better
VIN  VIN 
transient performance.

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 RT8125E
MOSFET Selection 4.0

Maximum Power Dissipation (W)1

Four-Layer PCB
The majority of power loss in the step-down power
conversion is due to the loss in the power MOSFETs. For 3.2

low voltage high current applications, the duty cycle of

the high side MOSFET is small. Therefore, the switching 2.4

loss of the high side MOSFET is of concern. Power

MOSFETs with lower total gate charge are preferred in 1.6

such kind of application. However, the small duty cycle

0.8
means the low side MOSFET is on for most of the switching
cycle. Therefore, the conduction loss tends to dominate
the total power loss of the converter. To improve the overall 0.0
0 25 50 75 100 125
efficiency, MOSFETs with low RDS(ON) are preferred in the
Ambient Temperature (°C)
circuit design. In some cases, more than one MOSFET
Figure 6. Derating Curve of Maximum Power Dissipation
are connected in parallel to further decrease the on-state
resistance. However, this depends on the low side
MOSFET driver capability and the budget. Layout Considerations
PCB layout is critical to high current high frequency
Thermal Considerations switching converter designs. A good layout can help the
For continuous operation, do not exceed absolute controller to function properly and achieve expected
maximum junction temperature. The maximum power performance. On the other hand, PCB without a carefully
dissipation depends on the thermal resistance of the IC layout can radiate excessive noise, having more power
package, PCB layout, rate of surrounding airflow, and loss and even malfunction in the controller. In order to
difference between junction and ambient temperature. The avoid the above condition, the general guidelines can be
maximum power dissipation can be calculated by the followed in PCB layout.
following formula :
 Power stage components should be placed first. Place
PD(MAX) = (TJ(MAX) − TA) / θJA the input bulk capacitors close to the high side power
where TJ(MAX) is the maximum junction temperature, TA is MOSFETs, and then locate the output inductor and finally
the ambient temperature, and θJA is the junction to ambient the output capacitors.
thermal resistance.  Placing the ceramic capacitor physically close to the
For recommended operating condition specifications, the drain of the high side MOSFET. This can reduce the
maximum junction temperature is 125°C. The junction to input voltage drop when high side MOSFET is turned
ambient thermal resistance, θJA, is layout dependent. For on. If more than one MOSFET is paralleled, each should
WDFN-10L 3x3 package, the thermal resistance, θJA, is have its own individual ceramic capacitor.
30.5°C/W on a standard JEDEC 51-7 four-layer thermal  Keep the high current loops as short as possible. During
test board. The maximum power dissipation at TA = 25°C high speed switching, the current transition between
can be calculated by the following formulas : MOSFETs usually causes di/dt voltage spike due to
PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 3.27W for the parasitic components on PCB trace. Therefore,
WDFN-10L 3x3 package making the trace length between power MOSFETs and
inductors wide and short can reduce the voltage spike
The maximum power dissipation depends on the operating
and EMI.
ambient temperature for fixed T J(MAX) and thermal
resistance. The derating curve in Figure 6 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
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DS8125E-00 July 2015 www.richtek.com

15
RT8125E
 Make MOSFET gate driver path as short as possible.
Since the gate driver uses narrow-width high current
pulses to switch on/off power MOSFET, the driver path
must be short to reduce the trace inductance. This is
especially important for low side MOSFET, because this
can reduce the possibility of shoot-through.
 Providing enough copper area around power MOSFETs
to help heat dissipation. Using thick copper also
reduces the trace resistance and inductance to have
better performance.
 The output capacitors should be placed physically close
to the load. This can minimize the trace parasitic
components and improve transient response.
 All small signal components should be located close
to the controller. The small signal components include
the feedback voltage divider resistors, function setting
components and high frequency bypass capacitors. The
feedback voltage divider resistor must be placed close
to FB pin, because the FB pin is inherently noise-
sensitive.
 Voltage feedback path must be away from switching
nodes. The noisy switching node is, for example, the
interconnection between high side MOSFET, low side
MOSFET and inductor. Feedback path must be away
from this kind of noisy node to avoid noise pick-up.
 A multi-layer PCB design is recommended. Make use
of one single layer as the ground and have separate
layers for power rail, or signal is suitable for PCB design.

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www.richtek.com DS8125E-00 July 2015

16
 RT8125E
Outline Dimension

D2
D

E E2

SEE DETAIL A
1

e
b 2 1 2 1
A
A3
A1 DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.300 2.650 0.091 0.104
E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069
e 0.500 0.020
L 0.350 0.450 0.014 0.018

W-Type 10L DFN 3x3 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS8125E-00 July 2015 www.richtek.com
17