RT8816A

Dual-Phase PWM Controller with PWM-VID Reference

1 General Description 2 Features
The RT8816A is a 2/1 dual-phase synchronous buck ⚫ Dual-Phase PWM Controller
PWM controller optimized for high-performance ⚫ Power-State Indicator
graphic microprocessors and supports the nVidia ⚫ 1P-CCM/2P-CCM/1P-DEM/2P-DEM
OVR2 specification with a PWM-VID interface. The IC ⚫ Two Embedded MOSFET Drivers and Embedded
integrates a Constant On-Time (COT) PWM controller, Switching Boot Diode
two MOSFET drivers with internal bootstrap diodes, ⚫ Support a 1.8V PWM-VID Interface
and channel current balance. It also includes ⚫ External Reference Input Control
comprehensive protection functions, including ⚫ PWM-VID Dynamic Voltage Control
overvoltage protection (OVP), undervoltage protection ⚫ Dynamic Phase Number Control
(UVP), current limit, and over-temperature protection, ⚫ Lossless RDS(ON) Current Sensing for Current
all within a WQFN-20L 3x3 package. Balance
The RT8816A adopts an RDS(ON) current sensing ⚫ Internal/External Soft-Start
technique for current limit, which is accomplished ⚫ Adjustable Current-Limit Threshold

through continuous inductor current sensing, while ⚫ Adjustable Switching Frequency

RDS(ON) current sensing is used for accurate channel ⚫ UVP/OVP Protection

current balance. This method of current sampling ⚫ Shoot Through Protection and Short Pulse Free

utilizes the best advantages of each technique. Technology

⚫ Support an Ultra-Low Output Voltage as Standby
Features of the RT8816A include an external
Voltage
reference input and PWM-VID dynamic output voltage
⚫ Over-Temperature Protection
control, where the feedback voltage is regulated to
⚫ Power-Good Indicator (EN to PGOOD High =
track an external input reference voltage. Other
500s)
features include an adjustable switching frequency,
dynamic phase number control, internal soft-start, 3 Applications
power-good indicator, and enable functions. The ⚫ CPU/GPU Core Power Supply
recommended junction temperature range is −10C to ⚫ Desktop PC Memory, VTT Power
105C. ⚫ Chipset/RAM Power Supply
⚫ Generic DC-DC Power Regulator

4 Simplified Application Circuit

RT8816A
VIN
VPVCC PVCC BOOT1
UGATE1
PHASE1 VOUT
VIN TON
OCSET/SS

PGOOD PGOOD
VIN
BOOT2
UGATE2
VPSI PSI
PHASE2

Enable EN

RGND VGND_SNS
GND
VSNS VOUT_SNS

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RT8816A
5 Ordering Information 6 Marking Information
RT8816A 7J=: Product Code
(1) YMDNN: Date Code
Package Type 7J=YM
QW: WQFN-20L 3x3 (W-Type) DNN
Lead Plating System
(2)
G: Richtek Green Policy Compliant
Note 1.
(1)
⚫ Marked with indicated: Compatible with the current
requirements of IPC/JEDEC J-STD-020.
(2)
⚫ Marked with indicated: Richtek products are Richtek
Green Policy compliant.

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 RT8816A
Table of Contents

1 General Description ................................................ 1 16.9 Power On Reset (POR) and UVLO .......... 17
2 Features ................................................................... 1 16.10 Soft-Start .............................................. 18
3 Applications ............................................................ 1 16.11 Power Good Output (PGOOD) ................ 19
4 Simplified Application Circuit ................................ 1 16.12 PWM VID and Dynamic Output Voltage
5 Ordering Information .............................................. 2 Control ................................................. 20
6 Marking Information................................................ 2 16.13 Boot Mode ............................................ 20
7 Pin Configuration .................................................... 4 16.14 Standby Mode ....................................... 21
8 Functional Pin Description..................................... 4 16.15 Normal Mode ........................................ 21
9 Functional Block Diagram ...................................... 6 16.16 VID Slew Rate Control ........................... 22
10 Absolute Maximum Ratings ................................... 7 16.17 Current Limit ......................................... 22
11 Recommended Operating Conditions ................... 8 16.18 Current Limit Setting .............................. 23
12 Electrical Characteristics ....................................... 8 16.19 Negative Current Limit ........................... 23
13 Typical Application Circuit ................................... 10 16.20 Current Balance .................................... 24
14 Typical Operating Characteristics ....................... 11 16.21 Output Overvoltage Protection (OVP) ...... 24
15 Operation ............................................................... 14 16.22 Output Undervoltage Protection (UVP) .... 24
15.1 Soft-Start (SS) ...................................... 14 16.23 MOSFET Gate Driver ............................. 24
15.2 PGOOD ............................................... 14 16.24 MOSFET Selection ................................ 24
15.3 Current Balance .................................... 14 16.25 Inductor Selection .................................. 25
15.4 Current Limit ......................................... 14 16.26 Input Capacitor Selection ....................... 25
15.5 Overvoltage Protection (OVP) 16.27 Output Capacitor Selection ..................... 25
and Undervoltage Protection (UVP) ......... 14 16.28 Thermal Considerations ......................... 25
16 Application Information ........................................ 15 16.29 Layout Considerations ........................... 26
16.1 Remote Sense ...................................... 15 17 Outline Dimension ................................................. 27
16.2 PWM Operation .................................... 15 18 Footprint Information ............................................ 28
16.3 On-Time Control ................................... 16 19 Packing Information .............................................. 29
16.4 Active Phase Circuit Setting ................... 16 19.1 Tape and Reel Data ............................... 29
16.5 Mode Selection ..................................... 16 19.2 Tape and Reel Packing .......................... 30
16.6 Diode-Emulation Mode .......................... 17 19.3 Packing Material Anti-ESD Property ........ 31
16.7 Forced-CCM Mode................................ 17 20 Datasheet Revision History .................................. 32
16.8 Enable and Disable ............................... 17

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RT8816A
7 Pin Configuration
(TOP VIEW)

PHASE1

PHASE2
LGATE1

LGATE2
PVCC
20 19 18 17 16
BOOT1 1 15 BOOT2
UGATE1 2 14 UGATE2
EN 3 GND 13 PGOOD
PSI 4 21 12 OCSET/SS
VID 5 11 VSNS
6 7 8 9 10

RGND
TON
VREF
REFADJ
REFIN
WQFN-20L 3x3

8 Functional Pin Description

Pin No. Pin Name Pin Function

1 BOOT1 Bootstrap supply for PWM1. This pin powers the high-side MOSFET driver.

High-side gate driver of PWM1. This pin provides the gate drive for the
2 UGATE1 converter's high-side MOSFET. Connect this pin to the gate of the high-side
MOSFET.
Enable control input. Active high input. When PVCC is under Power-On Reset
3 EN
(POR), the input voltage must not exceed PVCC.
Power saving interface. When the voltage is pulled below 0.4V, the device
operates into 1-phase DEM. When the voltage is between 0.7V to 0.88V, the
4 PSI device operates into 1-phase forced CCM. When the voltage is between 1.08V
to 1.35V, the device operates into 2-phase DEM. When the voltage is between
1.6V to 5.5V, the device operates into 2-phase forced CCM.
Programming output voltage control input. Refer to PWM VID and Dynamic
5 VID
Output Voltage Control.
Reference adjustment output. Refer to PWM VID and Dynamic Output Voltage
6 REFADJ
Control.
7 REFIN External reference input.
Reference voltage output. Connect a 0.1F/0603 decoupling capacitor
8 VREF
between VREF and GND. The reference voltage is 2V.
On-time/switching frequency adjustment input. Connecting a 100pF ceramic
9 TON capacitor between CTON and ground is optional for noise immunity
enhancement.
10 RGND Negative remote sense input. Connect this pin to the ground of the output load.
Positive remote sense input. Connect this pin to the positive terminal of the
11 VSNS
output load.
Current limit setting. Connect a resistor from OCSET/SS to GND to set the
12 OCSET/SS current- limit threshold. The external soft-start time also can be set by
connecting a capacitor from the OCSET/SS pin to GND.
13 PGOOD Power-good indicator output. Active high open-drain output.

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 RT8816A
Pin No. Pin Name Pin Function
High-side gate driver of PWM2. This pin provides the gate drive for the
14 UGATE2 converter's high-side MOSFET. Connect this pin to the gate of the high-side
MOSFET.
15 BOOT2 Bootstrap supply for PWM2. This pin powers the high-side MOSFET driver.
Switch node for PWM2. This pin is the return node of the high-side driver of
16 PHASE2 PWM 2. Connect this pin to the source of the high-side MOSFET, along with
the drain of the low-side MOSFET and the inductor.
Low-side gate driver of PWM2. This pin provides the gate drive for the
17 LGATE2 converter's low-side MOSFET. Connect this pin to the gate of the low-side
MOSFET.
Supply voltage input. Connect this pin to a 5V bias supply. Place a high- quality
18 PVCC
bypass capacitor from this pin to GND.
Low-side gate driver of PWM1. This pin provides the gate drive for the
19 LGATE1 converter's low-side MOSFET. Connect this pin to the gate of the low-side
MOSFET.
Switch node for PWM1. This pin is the return node of the high-side driver of
20 PHASE1 PWM 1. Connect this pin to the source of the high-side MOSFET, along with
the drain of the low-side MOSFET and the inductor.
21 Ground. The exposed pad should be soldered to a large PCB and connected
GND
(Exposed Pad) to GND for maximum thermal dissipation.

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RT8816A
9 Functional Block Diagram
VREF

Reference
Output Gen.
VID
PVCC
RGND
REFADJ Power On Reset
PSI Mode Select & Central Logic
OV PGOOD
REFIN 150% REFIN -
or 2V +
UV Control & Protection Logic
40% REFIN +
Boot-Phase
- Detection 1

Soft-Start PWM Boot-Phase

& Slew Rate CMP Detection 2
Control + BOOT1
TON
VSNS - Gen. 1 UGATE1
PHASE1
PWM1
Enable To Driver Logic LGATE1
EN
Logic To Power On Reset Driver
Logic BOOT2
TON PWM2
Gen. 2 UGATE2
PHASE2
LGATE2
To Power On Reset

VIN -
Detection S/H GM
+ VB
Current
TON Balance -
S/H GM
+ VB
-
ICS 40µ +
Current
To Protection Logic
ICS Limit -
To SSOK
10µ X(-1/12) +
OCSET/SS

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 RT8816A
10 Absolute Maximum Ratings
(Note 2)
⚫ TON to GND ---------------------------------------------------------------------------------------------------------- −0.3V to 30V
⚫ RGND to GND -------------------------------------------------------------------------------------------------------- −0.7V to 0.7V
⚫ BOOTx to PHASEx
DC ----------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
<100ns ----------------------------------------------------------------------------------------------------------------- −5V to 7.5V
⚫ BOOTx to GND
DC ----------------------------------------------------------------------------------------------------------------------- −0.3V to 36V
<100ns ----------------------------------------------------------------------------------------------------------------- −5V to 42V
⚫ PHASEx to GND
DC ----------------------------------------------------------------------------------------------------------------------- −5V to 30V
<100ns ----------------------------------------------------------------------------------------------------------------- −10V to 42V
⚫ UGATEx to GND
DC ----------------------------------------------------------------------------------------------------------------------- −5V to 36V
<100ns ----------------------------------------------------------------------------------------------------------------- −10V to 42V
⚫ UGATEx to PHASEx
DC ----------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
<100ns ----------------------------------------------------------------------------------------------------------------- −5V to 7.5V
⚫ LGATEx to GND
DC ----------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
<100ns ----------------------------------------------------------------------------------------------------------------- −5V to 7.5V
⚫ Other Pins ------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
⚫ Power Dissipation, PD @ TA = 25C
WQFN-20L 3x3------------------------------------------------------------------------------------------------------- 2.67W
⚫ Package Thermal Resistance (Note 3)
WQFN-20L 3x3, JA------------------------------------------------------------------------------------------------- 30C/W
WQFN-20L 3x3, JC ------------------------------------------------------------------------------------------------ 7.5C/W
⚫ Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------ 260C
⚫ Junction Temperature ---------------------------------------------------------------------------------------------- 150C
⚫ Storage Temperature Range ------------------------------------------------------------------------------------- −65C to 150C
⚫ ESD Susceptibility (Note 4)
HBM (Human Body Model) ---------------------------------------------------------------------------------------- 2kV

Note 2. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 3. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. JC is measured at the
exposed pad of the package.
Note 4. Devices are ESD sensitive. Handling precautions are recommended.

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RT8816A
11 Recommended Operating Conditions
(Note 5)
⚫ Input Voltage, VIN --------------------------------------------------------------------------------------------------- 2.5V to 26V
⚫ Supply Voltage, PVCC --------------------------------------------------------------------------------------------- 4.5V to 5.5V
⚫ Junction Temperature Range ------------------------------------------------------------------------------------- −10C to 105C
Note 5. The device is not guaranteed to function outside its operating conditions.

12 Electrical Characteristics
(VPVCC = 5V, typical values are referenced to TA = TJ = 25°C, Min and Max values are referenced to TA = TJ from −10°C to
105°C, unless other noted.)
Parameter Symbol Test Conditions Min Typ Max Unit
PWM Controller
PVCC Supply Input
VPVCC 4.5 -- 5.5 V
Voltage
VEN = 3.3V, 1-phase DEM
PVCC Supply Input
IPVCC mode, not switching, -- 0.4 -- mA
Current
VREF external R = 40k
PVCC Shutdown Current ISHDN VEN = 0V -- -- 10 A
PVCC POR Threshold VPOR 3.8 4.1 4.4 V
POR Hysteresis VPOR_HYS -- 0.3 -- V
Switching Frequency fSW RTON = 500k (Note 6) 270 300 330 kHz
Minimum On-Time tON_MIN -- 70 -- ns
Minimum Off-Time tOFF_MIN -- 300 -- ns
EN Input Voltage
EN Input Voltage
VEN_R 1.2 -- 5.5 V
Rising Threshold
EN Input Voltage
VEN_F -- -- 0.55 V
Falling Threshold
Mode Decision
2-Phase CCM VPSI 1.6 1.8 5.5 V
2-Phase DEM VPSI 1.08 1.2 1.35 V
1-Phase CCM VPSI 0.7 0.8 0.88 V
1-Phase DEM VPSI -- 0 0.4 V
PWM-VID Input Voltage for 1.8V GPIO Setting
PWM-VID Input Voltage
VPWM-VID_H 1.2 -- -- V
Logic H
PWM-VID Input Voltage
VPWM-VID_L -- -- 0.6 V
Logic L
PWM-VID Tri-State
VPWM-VID_Tr 0.8 -- 1.05 V
Voltage
Protection Function
Zero Current Crossing
VZC −8 -- 8 mV
Threshold

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 RT8816A
Parameter Symbol Test Conditions Min Typ Max Unit
Current-Limit Setting
IOCSET TA = TJ = 25C 9 10 11 A
Current
Current-Limit Setting
Current Temperature IOCSET_TC -- 4700 -- ppm/C
Coefficient
Current-Limit Threshold VOCSET ROCSET = 120k -- 100 -- mV
Absolute Overvoltage
VOVP_Absolute VREFIN  1.33V 1.9 2 2.1 V
Protection Threshold
Relative Overvoltage
VOVP_Relative VREFIN > 1.33V 145 150 155 %
Protection Threshold
Overvoltage Fault Delay tDLY_OV FB forced above OV threshold -- 5 -- s
Relative Undervoltage
VUVP UVP 35 40 45 %
Protection Threshold
Undervoltage Fault Delay tDLY_UV FB forced above UV threshold -- 3 -- s
Over-Temperature
TOTP -- 150 -- C
Threshold
VOUT Soft-Start From VEN = high to VOUT
tPGOODB -- 0.5 -- ms
(PGOOD Blanking Time) regulation point, VREFIN = 1V
PWM Comparator
VSNS Comparator Offset
VCMP_OFFSET VREFIN = 1V −11 −6 −1 mV
Voltage (Valley)
Reference
Sourcing current = 1mA, VID no
Reference Voltage VREF 1.98 2 2.02 V
switching
Driver On-Resistance
UGATE Driver Source
RSRC_UGATE BOOTx − PHASEx forced to 5V -- 2 4 
Impedance
UGATE Driver Sink
RSNK_UGATE BOOTx − PHASEx forced to 5V -- 1 2 
Impedance
LGATE Driver Source
RSRC_LGATE LGATEx, high state -- 1.5 3 
Impedance
LGATE Driver Sink
RSNK_LGATE LGATEx, low state -- 0.7 1.5 
Impedance
UGATE Propagation From LGATE falling to UGATE
tDLY_UG -- 30 -- ns
Delay Time rising
LGATE Propagation From UGATE falling to LGATE
tDLY_LG -- 20 -- ns
Delay Time rising
Internal Boost Diode
RBOOT PVCC to BOOTx, IBOOT = 10mA -- 80 -- 
Resistance
Note 6. Not production tested. Test condition is VIN = 8V, VOUT = 1V, IOUT = 20A using application circuit.

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RT8816A
13 Typical Application Circuit

VIN
1 0 0.1μF
18
VPVCC PVCC BOOT1
2.2μF RT8816A 0 10μF x 2 470μF/50V
RTON UGATE1
2.2 500k 9 0.36μH/1.05m 
VIN TON PHASE1 20 VOUT
1μF CTON LGATE1 19 NC
22μF x 15
Optional
100k OCSET/SS NC 330μF/2V x 4
PGOOD 13 PGOOD CSS
4 PSI ROCSET
PSI NC
5 VID VIN
VID
0 0.1μF
Enable 3 EN BOOT2 10μF x 2 470μF/50V
14 0
VREF UGATE2
CREF 0.1μF 0.36μH/1.05m 
16
RREF1 20k PHASE2
RGND 20k LGATE2 NC
REFADJ
CREFADJ RREFADJ NC 10 10
RBOOT 2k 2.7nF 10
RGND VGND_SNS
RGND 7 REFIN 11
VSNS VOUT_SNS
RSTANDBY CREFIN
RREF2 GND
5.1k 18k 4.7nF
(Optional) 21 (Exposed pad)
0
VSTANDBY
RGND RGND
NC
RGND

Figure 1. Two Active Phase Configuration

VIN
1 18 0 0.1μF
VPVCC PVCC BOOT1
2.2μF RT8816A 10μF x 2 470μF/50V
RTON 0
UGATE1
2.2 500k 9 0.36μH/1.05m 
VIN TON PHASE1 20 VOUT
1μF CTON
LGATE1 19 NC 22μF x 15
Optional
100k 13 PGOOD NC 330μF/2V x 4
PGOOD OCSET/SS 12
4 PSI CSS
PSI ROCSET
NC
VID 5 VID
10 10
Enable 3 EN 10
RGND VGND_SNS
VREF 11
VSNS VOUT_SNS
CREF 0.1μF
RREF1 20k
RGND 20k BOOT2
REFADJ 14
CREFADJ RREFADJ UGATE2
2k 2.7nF 16 Floating
RBOOT PHASE2
RGND 7 REFIN LGATE2
RSTANDBY RREF2 CREFIN GND
5.1k 18k 4.7nF
21 (Exposed pad)
0 (Optional)
VSTANDBY
RGND RGND
NC
RGND

Figure 2. One Active Phase Configuration

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 RT8816A
14 Typical Operating Characteristics

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RT8816A

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 RT8816A

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RT8816A
15 Operation
The RT8816A is a dual-phase synchronous buck PWM controller with integrated drivers, optimized for high-
performance graphics microprocessors and computer applications. The IC integrates a Constant On-Time (COT)
PWM controller, two MOSFET drivers, as well as output current monitoring and protection functions. According to
Functional Block Diagram of the TON Genx, the synchronous UGATE driver is activated at the beginning of each
cycle. Once the internal one-shot timer expires, the UGATE driver is deactivated. The duration of this one-shot
pulse is determined by the converter's input voltage and the output voltage to maintain a relatively constant
frequency across the input voltage range and the output voltage. Another one-shot timer establishes a minimum
off-time.
Additionally, the RT8816A features a PWM-VID dynamic voltage control circuit, which utilizes the pulse width
modulation method. This circuit reduces the number of device pins required and supports a wide dynamic voltage
range.

15.1 Soft-Start Function

For the soft-start (SS) function, an internal current source charges an internal capacitor to build the soft-start ramp
voltage. The output voltage will track the internal ramp voltage during soft-start interval.

15.2 Power-Good Indicator

The power-good output is an open-drain architecture.
When the soft-start is finished, the PGOOD open-drain output is high impedance.

15.3 Current Balance

The RT8816A implements an internal current balance mechanism in the current loop. The RT8816A senses per-
phase current and compares it with the average current. If the sensed current of any particular phase is higher
than the average current, the on-time of this phase is adjusted to be shorter.

15.4 Current Limit

The current-limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense
signal at PHASE is above the current-limit threshold, the PWM is not allowed to initiate a new cycle. Thus, if the
current to the load exceeds the average output inductor current, the output voltage falls and eventually crosses
the undervoltage protection threshold, inducing IC shutdown.

15.5 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)

The output voltage is continuously monitored for overvoltage and undervoltage protections. When the output
voltage exceeds its set voltage threshold (if VREFIN  1.33V, OV = 2V; or if VREFIN > 1.33V, OV = 1.5 x VREFIN),
UGATE goes low and LGATE is forced high. When it is less than 40% of its set voltage, the undervoltage protection
is triggered and then both UGATE and LGATE gate drivers are forced low. The controller is latched until PVCC is
re-supplied and exceeds the POR rising threshold voltage, or EN is reset.

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 RT8816A
16 Application Information
(Note 7)
The RT8816A is a dual-phase synchronous buck PWM controller with integrated drivers, optimized for high
performance graphics microprocessors and computer applications. A COT (Constant On-Time) PWM controller
and two MOSFET drivers with internal bootstrap diodes are integrated to simplify the external circuit and reduce
the component count.
The topology solves the poor load transient response timing problems associated with fixed-frequency mode PWM
and avoids the problems caused by widely varying switching frequencies in conventional constant on-time and
constant off-time PWM schemes. The IC supports a dynamic mode transition function with various operating states,
which include single phase with CCM, dual-phase with CCM, single phase with diode emulation mode, and dual-
phase with diode emulation mode operations. These different operating states enhance the system efficiency.
The RT8816A provides a PWM-VID dynamic control operation, where the feedback voltage is regulated to track
an external input reference voltage. It also features comprehensive fault protection functions, including overvoltage,
undervoltage, and current limit protections.

16.1 Remote Sense

The RT8816A uses the remote sense path (VSNS and RGND) to overcome voltage drops in the power lines by
sensing the voltage directly at the end of GPU. Normally, to protect remote sense path disconnecting, there are
two resistors (RLocal) connecting between local sense path and remote sense path. That is, in applications with
remote sensing, it is recommended that the RLocal be between 10 to 100. If remote sensing is not required,
RLocal is recommended to be 0.

VIN
BOOT

UGATE Local Sense Path

PHASE VOUT
LGATE

RLocal+ RLocal-
-
RGND GPU
+
VSNS GPU
Remote Sense Path

Figure 3. Output Voltage Sensing

16.2 PWM Operation

The RT8816A integrates a Constant On-Time (COT) PWM controller, and the controller provides the PWM signal based
on the comparison of the output ripple voltage with an internal reference voltage, as shown in Figure 4. According to
Functional Block Diagram of the TON Genx, the synchronous UGATE driver is turned on at the beginning of each
cycle. After the internal one-shot timer expires, the UGATE driver is turned off. The duration of this one-shot pulse width
is determined by the converter input voltage and the output voltage to keep a relatively constant frequency across the
input and output voltage range. Another one-shot mechanism sets a minimum off-time.

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RT8816A
VOUT

VPEAK

VOUT

VVALLEY
VREF
t
0 tON

Figure 4. Constant On-Time PWM Control

16.3 On-Time Control

The on-time one-shot comparator has two inputs. One input monitors the output voltage, while the other input
samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an
internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero
volts to VOUT, thereby making the on-time of the high-side switch directly proportional to the output voltage and
inversely proportional to the input voltage. The implementation results in a nearly constant switching frequency
without the need for a clock generator.
2  VOUT  3.2p
TON =  RTON
VIN − 0.5

and then the switching frequency fS is:

fS = VOUT / (VIN  TON)
RTON is a resistor connected from the VIN to the TON pin.
The recommended operation frequency range is from 250kHz to 750kHz.

16.4 Active Phase Circuit Setting

The RT8816A can be set for 2-phase or 1-phase operation by hardware circuit. For 1-phase operation, the
UGATE2, BOOT2, PHASE2, and LGATE2 pins are floating, and the voltage of the PSI pin must be set to the 1-
phase operation threshold. Refer to Table 1 for details.

16.5 Mode Selection

The RT8816A can operate into 2-phase with forced CCM, 1-phase with forced CCM, 1-phase with DEM and 2-
phase with DEM, depending on the PSI voltage setting. If the PSI voltage is pulled below 0.4V, the controller
operates into 1-phase with DEM. In DEM operation, the RT8816A automatically reduces the operation frequency
at light load conditions for saving power loss. If the PSI voltage is pulled between 0.7V to 0.88V, the controller
switches to 1-phase with forced CCM. If the PSI voltage is pulled between 1.08V to 1.35V, the controller switches
to 2-phase with DEM. If the PSI voltage is pulled between 1.6V to 5.5V, the controller switches to 2-phase with
forced CCM. The operation modes are summarized in Table 1. Moreover, the PSI pin is valid after POR of VR.

Table 1
Operation Phase Number PSI Voltage Setting
1-phase with DEM 0V to 0.4V
1-phase with CCM 0.7V to 0.88V
2-phase with DEM 1.08V to 1.35V
2-phase with DEM 1.6V to 5.5V

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 RT8816A
16.6 Diode-Emulation Mode
In diode-emulation mode, the RT8816A automatically reduces the switching frequency at light-load conditions to
maintain high efficiency. As the output current decreases from a heavy-load condition, the inductor current also
reduces. This reduction continues until the inductor current's valley reaches zero, making the boundary between
continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low-side
MOSFET allows only partial of the negative current when the inductor freewheeling current reaches a negative
value. As the load current further decreases, it takes longer to discharge the output capacitor to the level that
requires the next “ON” cycle. In reverse, when the output current increases from light load to heavy load, the
switching frequency increases to the preset value as the inductor current reaches the continuous conduction
condition. The transition load point to the light load operation is shown in Figure 5 and can be calculated as follows:
(VIN − VOUT )
ILOAD(SKIP)   tON
2L

where tON is on-time.

IL
Slope = (VIN - VOUT) / L
IPEAK

ILOAD = IPEAK/2

t
0 tON

Figure 5. Boundary Condition of CCM/DEM

The switching waveforms may be noisy and asynchronous in light loading diode-emulation operation conditions,
but this is a normal operating condition that results in high light-load efficiency. A trade-off between DEM noise
and light-load efficiency is made by varying the inductor value. Generally, lower inductor values produce a broad
high efficiency range versus load curve, while higher values result in higher full load efficiency (assuming that the
coil resistance remains fixed) and less output voltage ripple. The disadvantages for using higher inductor values
include a larger physical size and degraded load-transient response (especially at low input voltage levels).

16.7 Forced-CCM Mode

The low noise, forced-CCM mode disables the zero-crossing comparator, which controls the low-side switch on-
time. This causes the low-side gate drive waveform to be the complement of the high-side gate drive waveform,
which in turn causes the inductor current to reverse at light loads as the PWM loop maintains a duty ratio of
VOUT/VIN. The benefit of forced-CCM mode is to keep the switching frequency fairly constant.

16.8 Enable and Disable

The EN pin is a high-impedance input that allows power sequencing between the controller bias voltage and
another voltage rail. The RT8816A remains in shutdown if the EN pin is lower than 550mV. When the EN voltage
rises above the 1.2V high-level threshold, the RT8816A begins a new initialization and soft-start cycle.

16.9 Power On Reset (POR) and UVLO

A Power On Reset (POR) occurs when VPVCC rises above approximately 4.1V (typical), the RT8816A resets the
fault latch circuit and prepares for PWM operation. When the VPVCC is lower than 3.8V (typical), the undervoltage-
lockout (UVLO) circuitry inhibits switching by keeping UGATE and LGATE low.

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RT8816A
16.10 Soft-Start Function
The RT8816A provides both internal and external soft-start functions. The soft-start function is used to prevent
large inrush current and output voltage overshoot during power-up. The soft-start function automatically begins
once the IC is enabled. There is a delay time around 200s from when EN goes high to when VOUT begins to
ramp-up.
If the external capacitor from the OCSET/SS pin to GND is removed, the internal soft-start function is chosen. An
internal current source charges the internal soft-start capacitor so that the internal soft-start voltage ramps up
linearly. The output voltage will track the internal soft-start voltage during the soft-start interval. After the internal
soft-start voltage exceeds the REFIN voltage, the output voltage no longer tracks the internal soft-start voltage but
follows the REFIN voltage. Therefore, the duty cycle of the UGATE signal, as well as the input current at power-
up are limited.
The soft-start process is finished when the internal SSOK goes high, and no protection is triggered.
Furthermore, it is important to pay attention to the CREF, as the value of the CREF will affect the ramp-up speed
of the VREF voltage. It is recommended to place a 0.1F capacitor on the RT8816A to avoid unexpected soft-start
behavior.
Figure 6 shows the internal soft-start sequence.

PVCC

EN

VOUT

VREFIN

Internal SS

Internal SSOK

UGATE

LGATE

PGOOD

Enable Soft
Soft-start Normal
delay time Discharged

Figure 6. Internal Soft-Start Sequence

The RT8816A also provides an external soft-start function, and the external soft-start sequence is shown in Figure
7, by connecting an additional capacitor from the OCSET/SS pin to GND. The external capacitor is charged by an
internal current source to build the soft-start voltage ramp. If the external soft-start function is chosen, the external
soft-start time should be set longer than the internal soft-start time to avoid output voltage tracking the internal
soft-start ramp. The external soft-start time setting is shown in Figure 8 and the recommended external soft-start
slew rate is from 0.1V/ms to 0.4V/ms.

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 RT8816A

PVCC

EN

VOUT
120% VREFIN

External SS

External SSOK

UGATE

LGATE

PGOOD

Enable Soft
Soft-start Normal
delay time Discharged

Figure 7. External Soft-Start Sequence

The soft-start time can be calculated as:

 
tSS = − (CSS  ROCSET )  ln 1− 
VREFIN

  ISS  ROCSET  
where ISS = 50A (typical), VREFIN is the voltage of the REFIN pin, ROCSET is the current limit setting resistor, and
CSS is the external capacitor connected from the OCSET/SS pin to GND.

VCC
VREFIN
ISS
SS
OCSET/SS SS
CSS ROCSET

VOUT
tSS

Figure 8. External Soft-Start Setting

For ensuring the soft-start function works normally, the following setting limitation must be followed:
ROCSET x 50A > 1.2 x VREFIN

16.11 Power Good Output (PGOOD)

The PGOOD pin is an open-drain output, and it requires a pull-up resistor. During soft-start, the PGOOD pin is
held low and is allowed to be pulled high after VOUT exceeds the UVP threshold and is under OVP threshold. In
addition, if any protection is triggered during operation, the PGOOD pin is pulled low immediately.

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RT8816A
16.12 PWM VID and Dynamic Output Voltage Control
The RT8816A features a PWM VID input for dynamic output voltage control, as shown in Figure 9, which reduces
the number of device pins and enables a wide dynamic voltage range. The output voltage is determined by the
applied voltage on the REFIN pin. The PWM duty cycle determines the variable output voltage at REFIN.

VID
PWM IN
VREF

RREF1
RREFADJ REFADJ
Buffer
CREFADJ
RBOOT RGND
RGND
REFIN

RSTANDBY RREF2 CREFIN

RGND RGND
Standby Q1
Mode Control
RGND

Figure 9. PWM VID Analog Circuit Diagram

With the external circuit and VID control signal, the controller provides three operation modes, shown as Figure
10.

NORMAL
VREF MODE
BOOT BOOT
MODE MODE STANDBY
MODE
REFIN
PWM VID

STANDBY
CONTROL

Figure 10. PWM VID Time Diagram

16.13 Boot Mode

When VID is not driven, the buffer output is in a tri-state condition. At this time, turn off the switch Q1 and connect
a resistor divider, as shown in Figure 9, that can set the REFIN voltage to be VBOOT using the following equation:

VBOOT = VVREF   
RREF2

 RREF1 + RREF2 + RBOOT 

where VVREF = 2V (typical)

Choose RREF2 to be approximately 10k, and the RREF1 and RBOOT can be calculated using the following
equations:

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 RT8816A
RREF2  ( VVREF − VBOOT )
RREF1 + RBOOT =
VBOOT

RREF2  ( VVREF − VBOOT )

RREF1 = − RBOOT
VBOOT

RREF2  ( VVREF − VBOOT )

RBOOT = − RREF1
VBOOT

16.14 Standby Mode

An external control can provide a very low voltage to meet VOUT operating in standby mode. If the VID pin is
floating and switch Q1 is enabled, as shown in Figure 9, the REFIN pin can be set for standby voltage according
to the calculation below:
RREF2 // RSTANDBY
VSTANDBY = VVREF 
RREF1 + RBOOT + (RREF2 // RSTANDBY )

By choosing RREF1, RREF2, and RBOOT, the RSTANDBY can be calculated using the following equation:

RREF2  (RREF1 + RBOOT )  VSTANDBY

RSTANDBY =
RREF2  VVREF − VSTANDBY  (RREF1 + RREF2 + RBOOT )

16.15 Normal Mode

If the VID pin is driven by a PWM signal and switch Q1 is disabled, as shown in Figure 9, the VREFIN can be
adjusted from Vmin to Vmax, where Vmin is the voltage at zero percent PWM duty cycle and V max is the voltage at
one hundred percent PWM duty cycle. The Vmin and Vmax can be set using the following equations:

RREF2 RREFADJ // (RBOOT + RREF2 )

Vmin = VVREF  
RREF2 + RBOOT RREF1 + RREFADJ // (RBOOT + RREF2 )

RREF2
Vmax = VVREF 
(RREF1 // RREFADJ ) + RBOOT + RREF2

By choosing RREF1, RREF2, and RBOOT, the RREFADJ can be calculated using the following equation:
R V
RREFADJ = REF1 min
Vmax − Vmin

The relationship between VID duty and VREFIN is shown in Figure 11, and VOUT can be set according to the
calculation below:
VOUT = Vmin + N VSTEP

where VSTEP is the resolution of each voltage step 1:

(Vmax − Vmin )
VSTEP =
Nmax

where Nmax is the number of total available voltage steps and N is the number of steps at a specific VOUT. The
dynamic voltage VID period (Tvid = Tu x Nmax) is determined by the unit pulse width (Tu) and the available step
number (Nmax). The recommended Tu is 27ns.

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RT8816A
VREFIN
N = Nmax
Vmax

N=2
N=1
Vmin
VID Duty
0 0.5 1

N=1
VID Input
Tu

N=2
VID Input
Tvid = Nmax x Tu

Figure 11. PWM VID Analog Output

16.16 VID Slew Rate Control

In the RT8816A, the VREFIN slew rate is proportional to the PWM VID duty, and the rising time and falling time are
the same. In normal mode, the VREFIN slew rate SR can be estimated by CREFADJ or CREFIN using the following
equation:
When choosing CREFADJ:
(VREFIN_Final − VREFIN_initial )  80%
SR =
2.2RSRCREFADJ
RSR = (RREF1 // RREFADJ ) // (RBOOT +RREF2 )

When choosing CREFIN:

(VREFIN_Final − VREFIN_initial )  80%
SR =
2.2RSR CREFIN
RSR = (RREF1 // RREFADJ ) + RBOOT  // RREF2

The recommended SR is estimated by CREFADJ.

16.17 Current Limit

The RT8816A provides cycle-by-cycle current-limit control by detecting the PHASE voltage drop across the low-
side MOSFET when it is turned on. The current-limit circuit employs a unique “valley“ current sensing algorithm,
as shown in Figure 12. If the magnitude of the current sense signal at PHASE is above the current-limit threshold,
the PWM is not allowed to initiate a new cycle.
In order to provide both good accuracy and a cost-effective solution, the RT8816A supports temperature
compensated MOSFET RDS(ON) sensing.

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 RT8816A
IL

IL,PEAK

ILOAD

IL,VALLEY

t
0

Figure 12. “Valley” Current Limit

In an overcurrent condition, the current to the load exceeds the average output inductor current. Thus, the output
voltage falls and eventually crosses the undervoltage protection threshold, inducing IC shutdown.

16.18 Current Limit Setting

The RT8816A adopts per-phase current-limit protection. The current-limit threshold can be set by a resistor
(ROCSET) between the OCSET/SS pin and GND. Once PVCC exceeds the POR threshold and the IC is enabled,
an internal current source IOCSET flows through ROCSET. After the soft-start ends, IOCSET is 10A. The voltage
across ROCSET is stored as the current-limit protection threshold VOCSET. The threshold range of VOCSET is 20mV
to 200mV. It can be calculated according to the following equation:
IOCSET x ROCSET
VOCSET =
12
ROCSET can be determined using the following equation:
IVALLEY x RDS_ON x 12
ROCSET =
IOCSET

where IVALLEY represents the desired per-phase inductor limit current (valley inductor current) and IOCSET is the
current-limit setting current, which has a temperature coefficient to compensate the temperature dependency of
the RDS(ON).
If ROCSET is not present, there is no current path for IOCSET to build the current-limit threshold. In this situation, the
current-limit threshold is internally preset to 200mV.

16.19 Negative Current Limit

The RT8816A supports cycle-by-cycle negative current limit. The absolute value of the negative current-limit
threshold is the same as the positive current-limit threshold. If negative inductor current is rising to trigger
negative current limit, the low-side MOSFET is turned off, and the current flows to the input side through the
body diode of the high-side MOSFET. At this time, the output voltage tends to rise because this protection
limits current to discharge the output capacitor. In order to prevent shutdown because of the overvoltage
protection, the low-side MOSFET is turned on again 400ns after it is turned off. If the device hits the negative
current-limit threshold again before the output voltage is discharged to the target level, the low-side MOSFET is
turned off, and the process repeats. It ensures the maximum allowable discharge capability when the output
voltage continues to rise. Conversely, if the output is discharged to the target level before the negative current-
limit threshold is reached, the low-side MOSFET is turned off, the high-side MOSFET is then turned on, and the
device keeps normal operation.

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RT8816A
16.20 Current Balance
The RT8816A implements a current balance mechanism in the current loop. The RT8816A senses per-phase
current signal and compares it with the average current. If the sensed current of any particular phase is higher
than the average current, the on-time of this phase is decreased.
The current balance accuracy is mainly related to the on-resistance of the low-side MOSFET (RLG,DS(ON)). That
is, in practical application, using lower RLG,DS(ON) will reduce the current balance accuracy.

16.21 Output Overvoltage Protection (OVP)

The output voltage can be continuously monitored for overvoltage protection. If the REFIN voltage is lower than
1.33V. The overvoltage threshold follows the absolute overvoltage of 2V. If the REFIN voltage is higher than 1.33V,
the overvoltage threshold follows the relative overvoltage of 1.5 x VREFIN. When OVP is triggered, UGATE goes
low and LGATE is forced high. The RT8816A is latched once OVP is triggered and can only be released by a
PVCC or EN power on reset. A 5s delay is used in the OVP detection circuit to prevent false trigger.

16.22 Output Undervoltage Protection (UVP)

The output voltage can be continuously monitored for undervoltage protection. When the output voltage is less
than 40% of its set voltage, undervoltage protection is triggered and then all UGATE and LGATE gate drivers are
forced low. There is a 3s delay built in the UVP circuit to prevent false transitions. During soft-start, the UVP
blanking time is equal to the PGOOD blanking time.

16.23 MOSFET Gate Driver

The RT8816A integrates high current gate drivers for the MOSFETs to obtain high-efficiency power conversion in a
synchronous buck topology. A dead-time is used to prevent the cross conduction for the high-side and low-side
MOSFETs. Because both two gate signals are off during the dead-time, the inductor current freewheels through
the body diode of the low-side MOSFET. The freewheeling current and the forward voltage of the body diode
contribute to power losses in the converter. The RT8816A employs an adaptive dead time control scheme to
ensure safe operation without sacrificing efficiency. Furthermore, an elaborate logic circuit is implemented to
prevent cross conduction. For high output current applications, two power MOSFETs are usually paralleled to
reduce RDS(ON). The gate driver needs to provide more current to switch on/off these paralleled MOSFETs. A gate
driver with a lower source/sink current capability results in longer rising/falling times in gate signals and higher
switching losses. The RT8816A embeds high current gate drivers to obtain high efficiency power conversion.

16.24 MOSFET Selection

The majority of power loss in the buck power conversion is due to the loss in the power MOSFETs. For low-
voltage high-current applications, the duty cycle of the high-side MOSFET is low, making its switching loss a
primary concern. Power MOSFETs with a lower total gate charge are preferred in such applications.
However, the small duty cycle means the low-side MOSFET is on for most of the switching cycle. Therefore,
the conduction loss tends to dominate the total power loss of the converter. To improve the overall efficiency,
the MOSFETs with low R DS(ON) are preferred in the circuit design. In some cases, more than one MOSFET is
connected in parallel to further decrease the on-state resistance. However, this depends on the low-side
MOSFET driver capability and the budget.

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 RT8816A
16.25 Inductor Selection
The inductor plays an important role in buck converters because the energy from the input power rail is stored in
it and then released to the load. For efficiency, the DC Resistance (DCR) of the inductor should be as small as
possible to minimize the copper loss. In addition, the inductor occupies most of the board space, so its size is
important. Low profile inductors can save board space, especially when the height is limited. However, low DCR
and low-profile inductors are usually not cost effective.
Additionally, the higher inductance results in lower ripple current, which means the lower power loss. However,
the inductor current rising time increases with the inductance value. This means the transient response will be
slower. Therefore, the inductor design is a trade-off between performance, size, and cost.
In general, inductance is designed to let the ripple current ranges between 20% to 40% of the full load current.
The inductance can be calculated using the following equation:
VIN − VOUT V
Lmin =  OUT
fSW  k  IOUT_rated VIN

where k is the ratio between the inductor ripple current and the rated output current.

16.26 Input Capacitor Selection

The voltage rating and current rating are the key parameters in selecting an input capacitor. Generally, the input
capacitor voltage rating should be 1.5 times greater than the maximum input voltage for a conservatively safe
design.
The input capacitor is used to supply the input RMS current, which can be approximately calculated using the
following equation:

 1− OUT 
VOUT V
IRMS = IOUT 
VIN  VIN 

The next step is to select a proper capacitor for the RMS current rating. Using more than one capacitor with low
Equivalent Series Resistance (ESR) in parallel to form a capacitor bank is a good design. Besides, placing a
ceramic capacitor close to the drain of the high-side MOSFET is helpful in reducing the input voltage ripple at
heavy load.

16.27 Output Capacitor Selection

The output filter capacitor must have an ESR low enough to meet the output ripple and load transient requirements,
yet have a high enough ESR to satisfy stability requirements. Also, the capacitance must be high enough to absorb
the inductor energy going from a full load to no load condition without triggering the OVP circuit. Organic
semiconductor capacitor(s) or special polymer capacitor(s) are recommended.

16.28 Thermal Considerations

The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under
Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation
depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the
difference between the junction and ambient temperatures. The maximum power dissipation can be calculated
using the following formula:
PD(MAX) = (TJ(MAX) - TA) / JA
where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient
thermal resistance.

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RT8816A
For continuous operation, the maximum operating junction temperature indicated under Recommended Operating
Conditions is 105C. The junction-to-ambient thermal resistance, JA, is highly package dependent. For a WQFN-
20L 3x3 package, the thermal resistance, JA, is 30C/W on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board.
The maximum power dissipation at TA = 25C can be calculated as below:
PD(MAX) = (105°C - 25°C) / (30°C/W) = 2.67W for a WQFN-20L 3x3 package.
The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal
resistance, JA. The derating curve in Figure 13 allows the designer to see the effect of rising ambient temperature on
the maximum power dissipation.

Figure 13. Derating Curve of Maximum Power Dissipation

16.29 Layout Considerations

Layout is very important in high-frequency switching converter design. If designed improperly, the PCB can radiate
excessive noise and contribute to the converter instability. The following layout guidelines must be considered
before starting a layout for the RT8816A.
 Place the RC filter as close as possible to the PVCC pin.
 Keep the current-limit setting network as close as possible to the IC. The routing of the network should avoid
coupling to the high voltage switching node.
 Connections from the drivers to the respective gates of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance.
 All sensitive analog traces and components such as VSNS, RGND, EN, PSI, VID, PGOOD, VREF, TON,
REFADJ, and REFIN should be placed away from high voltage switching nodes such as PHASE, LGATE,
UGATE, or BOOT nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback
trace from power traces and components.
 Power sections should connect directly to ground plane(s) using multiple vias as required for current handling
(including the IC power ground connections). Power components should be placed to minimize loops and
reduce losses.

Note 7. The information provided in this section is for reference only. The customer is solely responsible for the designing,
validating, and testing your product incorporating Richtek’s product and ensure such product meets applicable
standards and any safety, security, or other requirements.
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 RT8816A
17 Outline Dimension

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.150 0.250 0.006 0.010
D 2.900 3.100 0.114 0.122
D2 1.650 1.750 0.065 0.069
E 2.900 3.100 0.114 0.122
E2 1.650 1.750 0.065 0.069
e 0.400 0.016
L 0.350 0.450 0.014 0.018

W-Type 20L QFN 3x3 Package

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RT8816A
18 Footprint Information

Number of Footprint Dimension (mm)

Package Tolerance
Pin P Ax Ay Bx By C D Sx Sy
V/W/U/XQFN3*3-20 20 0.40 3.80 3.80 2.10 2.10 0.85 0.20 1.70 1.70 ±0.05

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 RT8816A
19 Packing Information
19.1 Tape and Reel Data

Tape Size Pocket Pitch Reel Size (A) Units Reel Width (W2)
Trailer Leader
Package Type (W1) (mm) (P) (mm) per Reel Min/Max (mm)
(mm) (in) (mm) (mm)
(V, W)
QFN/DFN 12 8 180 7 1,500 160 600 12.4/14.4
3x3

C, D, and K are determined by component size.

The clearance between the components and

the cavity is as follows:

- For 12mm carrier tape: 0.5mm max.

W1 P B F ØJ K H
Tape Size
Max Min Max Min Max Min Max Min Max Min Max Max
12mm 12.3mm 7.9mm 8.1mm 1.65mm 1.85mm 3.9mm 4.1mm 1.5mm 1.6mm 1.0mm 1.3mm 0.6mm

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RT8816A
19.2 Tape and Reel Packing
Step Photo/Description Step Photo/Description

1 4

Reel 7” 3 reels per inner box Box A

2 5

HIC & Desiccant (1 Unit) inside 12 inner boxes per outer box

3 6

Caution label is on backside of Al bag Outer box Carton A

Container Reel Box Carton

Package
Size Units Item Reels Units Item Boxes Unit

Box A 3 4,500 Carton A 12 54,000

(V, W) 7” 1,500
QFN & DFN 3x3 Box E 1 1,500 For Combined or Partial Reel.

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 RT8816A
19.3 Packing Material Anti-ESD Property

Surface
Aluminum Bag Reel Cover tape Carrier tape Tube Protection Band
Resistance
/cm2 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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RT8816A
20 Datasheet Revision History
Version Date Description Item
General Description on page 1
Ordering Information on page 2
Electrical Characteristics on page 9, 10
00 2024/2/23 Modify
Application Information on page 16
Footprint Information on page 29
Packing Information on page 30, 31, 32
Ordering Information on page 2
Functional Pin Description on page 4
01 2024/5/7 Modify Typical Application Circuit on page 10
Application Information on page 18, 26
Packing Information on page 30
Application Information on page 19
02 2025/1/3 Modify
Packing Information on page 29, 30

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