®

RT2568A

DDR Termination Regulator

General Description Features
The RT2568A is a sink/source tracking termination  VIN Input Voltage Range : 1.1V to 3.5V
regulator. It is specifically designed for low-cost and low-  VCNTL Input Voltage Range : 2.9V to 5.5V
external component count systems. The RT2568A  Support Ceramic Capacitors
possesses a high speed operating amplifier that provides  Power Good Indicator
fast load transient response and only requires a minimum  10mA Source/Sink Reference Output
10μF x 3 ceramic output capacitors. The RT2568A supports  Meet DDRI, DDRII JEDEC Spec
remote sensing functions and all features required to power  Supports DDR, DDR2, DDR3, DDR3L, Low-Power
the DDRIII and Low Power DDRIII / DDRIV VTT bus DDR3, and DDR4 VTT Applications
termination according to the JEDEC specification. In  Soft-Start Function
addition, the RT2568A provides an open-drain PGOOD  UVLO and OCP Protection
signal to monitor the output regulation and an EN signal  Thermal Shutdown
that can be used to discharge VTT during S3 (suspend to
RAM) for DDR applications. Applications
The RT2568A is available in the thermal efficient package,  Notebook/Desktop/Server
WDFN-10L 3x3.  Telecom/Datacom, GSM Base Station, LCD-TV/PDP-
TV, Copier/Printer, Set-Top Box

Simplified Application Circuit

RT2568A
VIN VIN VCNTL VCNTL
R1 C5
REFIN R3
C1 C2
C3 PGOOD Power Good Indicator
R2
VOUT VOUT
SENSE C6 C7 C8
REFOUT REFOUT
PGND
C4
Chip Enable GND
EN

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RT2568A
Ordering Information Pin Configuration
RT2568A (TOP VIEW)
Pin 1 Orientation*** REFIN 1 10 VCNTL
(2) : Quadrant 2, Follow EIA-481-D VIN 2 9 PGOOD

PAD
VOUT 3 8 GND
Package Type PGND 4 7 EN
SENSE 5 11 6 REFOUT
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System WDFN-10L 3x3
G : Green (Halogen Free and Pb Free)
Note :
Marking Information
***Empty means Pin1 orientation is Quadrant 1
8K= : Product Code
Richtek products are :
8K=YM YMDNN : Date Code
 RoHS compliant and compatible with the current require-
DNN
ments of IPC/JEDEC J-STD-020.
 Suitable for use in SnPb or Pb-free soldering processes.

Functional Pin Description

Pin No. Pin Name Pin Function
1 REFIN Reference input.
2 VIN Power input of the regulator.
3 VOUT Power output of the regulator.
4 PGND Power ground of the regulator.
Voltage sense input for the regulator. Connect to positive terminal of the output
5 SENSE
capacitor or the load.
6 REFOUT Reference output. Connect to GND through a 0.1F ceramic capacitor.
7 EN Enable control input. Control the device ON/OFF function.
Power good open-drain output. Connect a pull-up resistor between this pin and
9 PGOOD
VCNTL pin.
Control voltage input. Connect this pin to the 3.3V or 5V power supply. A
10 VCNTL
ceramic decoupling capacitor with value range from 1F to 4.7F is suggested.
8 GND Analog ground. Connect to negative terminal of the output capacitor.
Exposed pad. The exposed pad is internally unconnected and must be soldered
11 (Exposed Pad) PAD to a large PGND plane. Connect this PGND plane to other layers with thermal
vias to help dissipate heat from the device.

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 RT2568A
Functional Block Diagram
EN VCNTL

Control Thermal VIN

REFIN
Logic Protection

Buffer
+
OCP
-
REFOUT

VOUT
SENSE -
OP Driver
+ DcgREF
PGOOD
+
Power OCP
-
Good
GND PGND
DcgREF

Operation
The RT2568A is a linear sink/source DDR termination Over-Current Protection
regulator with current capability up to 3A. The RT2568A The device continuously monitors the output current to
builds in a high-side N-MOSFET which provides current protect the pass transistor against abnormal operations.
sourcing and a low-side N-MOSFET which provides current Both the source and sink currents are detected by the
sinking. All the control circuits are supplied by the power internal sensing resistor, and the OCP function will work
VCNTL. In normal operation, the error amplifier OP adjusts to limit the current to a designed value when overload
the gate driving voltage of the power MOSFET to achieve happens.
SENSE voltage well tracking the REFIN voltage.
Control Logic
Buffer
This block includes VCNTL UVLO, REFIN UVLO and
This function provides REFOUT output which is equal to Enable/Disable functions, and provides logic control to
VREFIN with 10mA source/sink current capability. the whole chip.

Power Good Thermal Protection

When the SENSE voltage is in the power good window Both the high-side and low-side power MOSFETs will be
and lasts for a certain delay time, then the PGOOD pin turned off when the junction temperature is higher than
will be high impedance and the PGOOD voltage will be typically 160°C.
pulled high by the external resistor.

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RT2568A
Absolute Maximum Ratings (Note 1)
 Supply Voltage, VIN, VCNTL ------------------------------------------------------------------------------------------ −0.3V to 6V
 Input Voltage, EN, REFIN, SENSE ---------------------------------------------------------------------------------- −0.3V to 6V
 Output Voltage, VOUT, REFOUT, PGOOD ------------------------------------------------------------------------- −0.3V to 6V
 Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 ----------------------------------------------------------------------------------------------------------- 3.27W
 Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------ 30.5°C/W
WDFN-10L 3x3, θJC ----------------------------------------------------------------------------------------------------- 7.5°C/W
 Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------------- 260°C
 Junction Temperature --------------------------------------------------------------------------------------------------- 150°C
 Storage Temperature Range ------------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) -------------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 Control Input Voltage, VCNTL ----------------------------------------------------------------------------------------- 2.9V to 5.5V
 Supply Input Voltage, VIN ---------------------------------------------------------------------------------------------- 1.1V to 3.5V
 Junction Temperature Range ------------------------------------------------------------------------------------------ −40°C to 125°C

Electrical Characteristics
(VIN = 1.5V, VEN = VCNTL = 3.3V, VREFIN = VSENSE = 0.75V, COUT = 10μF x 3, TA = −40°C to 85°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Supply Current
VCNTL Supply Current IVCNTL VEN = VCNTL, no load -- 0.7 1 mA
VEN = 0V, VREFIN = 0V, no load -- 65 80
VCNTL Shutdown Current ISHDN_VCNTL A
VEN = 0V, VREFIN > 0.4V, no load -- 200 400
VIN Supply Current IVIN VEN = VCNTL, no load -- 1 50 A
VIN Shutdown Current ISHDN_VIN VEN = 0V, no load -- 0.1 50 A
Output
VIN = 1.5V, VREFIN = 0.75V,
-- 0.75 --
IOUT = 0A
VIN = 1.35V, VREFIN = 0.675V,
VTT Output Voltage VOUTO -- 0.675 -- V
IOUT = 0A
VIN = 1.2V, VREFIN = 0.6V,
-- 0.6 --
IOUT = 0A
IOUT < ±2A, VLDOIN = 1.5V,
25 -- 25
VOUT_OS = VOUT  VOUTO
IOUT < ±2A, VLDOIN = 1.35V,
VTT Output Voltage Offset VOUT_OS 25 -- 25 mV
VOUT_OS = VOUT  VOUTO
IOUT < ±2A, VLDOIN = 1.2V,
25 -- 25
VOUT_OS = VOUT  VOUTO

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 RT2568A
Parameter Symbol Test Conditions Min Typ Max Unit
VOUT Source Current Limit ILIM_VOUT_SR VOUT in PGOOD window 3 4.5 -- A
VOUT Sink Current Limit ILIM_VOUT_SK VOUT in PGOOD window 3 4.5 -- A
VOUT Discharge VREFIN = 0V, VOUT = 0.3V,
RDISCHARGE -- 18 25 
Resistance VEN = 0V
Power Good Comparator
VSENSE lower threshold with
-- 20 --
respect to REFOUT
PGOOD Threshold VTH_PGOOD VSENSE upper threshold with %
-- 20 --
respect to REFOUT
PGOOD hysteresis -- 5 --
Start-up rising delay, VSENSE
PGOOD Start-Up Delay TPGDELAY1 -- 2 -- ms
within PGOOD range
Output Low Voltage VLOW_PGOOD IPGOOD = 4mA -- -- 0.4 V
Falling delay, VSENSE is out of
PGOOD Falling Delay TPGDELAY2 -- 10 -- s
PGOOD range
VSENSE = VREFIN (PGOOD high
Leakage Current ILEAKAGE _PGOOD impedance), -- -- 1 A
VPGOOD = VCNTL + 0.2V
REFIN and REFOUT
REFIN Input Current IREFIN VEN = VCNTL -- -- 1 A
REFIN Voltage Range VREFIN 0.5 -- 1.8 V
REFIN Under-Voltage REFIN rising 360 390 420
VUVLO_REFIN mV
Lockout Hysteresis -- 20 --
10mA < IREFOUT < 10mA,
15 -- 15
VREFIN = 0.75V
REFOUT Voltage Tolerance 10mA < IREFOUT < 10mA,
VTOL_REFOUT 13.5 -- 13.5 mV
to VREFIN VREFIN = 0.675V
10mA < IREFOUT < 10mA,
12 -- 12
VREFIN = 0.6V
REFOUT Source Current
ILIM_REFOUT_SR VREFOUT = 0V 10 40 -- mA
Limit
REFOUT Sink Current Limit ILIM_REFOUT_SK VREFOUT = REFIN + 1V 10 40 -- mA
UVLO/EN
Rising 2.5 2.7 2.85 V
UVLO Threshold VUVLO_VCNTL
Hysteresis -- 120 -- mV
EN Input Logic-High VIN_H 1.7 -- --
V
Voltage Logic-Low VIN_L -- -- 0.3
EN is turned on to VOUT rising
EN Turn On Delay tDELAY -- -- 7 s
TA = 25°C (reference Note 5)
Thermal Shutdown
Thermal Shutdown Shutdown temperature (Note 5) -- 160 --
TSD °C
Threshold Hysteresis (Note 6) -- 15 --

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RT2568A
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precautions are recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. tDELAY is the maximum period form EN turn on to VOUT rising period as follows diagram. While TSS is the rising period
of VOUT, the formula used to calculated this rising period is TSS = (VOUT x COUT)/ILIM, it's base on the value of output
capacitor COUT, the settled output voltage VOUT and the output current limit ILIM.
Note 6. Guarantee by design.

VCNTL

REFOUT

EN TSS

VOUT TSS = (VOUT x COUT) / ILIM

tDELAY

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 RT2568A
Typical Application Circuit

RT2568A
VIN 2 10
VIN VCNTL VCNTL
R1 C5
10k 1 R3 4.7µF
C1 C2 REFIN
10µF 10µF 100k
9
R2 C3 PGOOD Power Good Indicator
10k 1nF 3
VOUT VOUT
5
SENSE C6 C7 C8
6 10µF 10µF 10µF
REFOUT REFOUT 4
C4 PGND
0.1µF
Chip Enable 7
EN GND 8

Table 1. Recommended External Components

Component Description Vendor P/N
GRM21BR70J106KE76L (Murata)
C1, C2, C6, C7, C8 10F, 6.3V, X7R, 0805
CGA4J1X7R0J106K125AC (TDK)
GCD188R71H102KA01D (Murata)
C3 1nF, 50V, X7R, 0603
CGA3E2X7R1H102K080AA (TDK)
C4 0.1F, 16V, X7R, 0603 GCJ188R71C104KA01D (Murata)
GRT188R60J475ME01D (Murata)
C5 4.7F, 6.3V, X5R, 0603
CGB3B3X5R0J475M055AB(TDK)

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RT2568A
Typical Operating Characteristics
Load Regulation Load Regulation
0.65 0.65
0.63 0.63 85°C
0.61 0.61 25°C
−40°C
Output Voltage (V)

Output Voltage (V)

0.59 0.59
0.57 0.57
0.55 85°C
0.55
25°C
0.53 −40°C 0.53
0.51 0.51
0.49 0.49
0.47 VIN = VDDQSNS = 1.1V, VOUT = 0.55V,
VIN = VDDQSNS = 1.1V, VOUT = 0.55V, VCNTL = 5V 0.47
VCNTL = 3.3V
0.45 0.45
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
Output Current (A) Output Current (A)

Load Regulation Load Regulation

0.70 0.70
0.68 0.68
85°C
0.66 0.66 25°C
Output Voltage (V)

Output Voltage (V)

−40°C
0.64 0.64
0.62 0.62

0.60 85°C 0.60

25°C
0.58 −40°C 0.58
0.56 0.56
0.54 0.54
0.52 0.52
VIN = VDDQSNS = 1.2V, VOUT = 0.6V, VCNTL = 5V VIN = VDDQSNS = 1.2V, VOUT = 0.6V, VCNTL = 3.3V
0.50 0.50
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
Output Current (A) Output Current (A)

Load Regulation Load Regulation

0.775 0.775
0.755 0.755 85°C
0.735 0.735 25°C
−40°C
Output Voltage (V)

Output Voltage (V)

0.715 0.715
0.695 0.695
85°C
0.675 25°C 0.675
0.655 −40°C 0.655
0.635 0.635
0.615 0.615
0.595 0.595 VIN = VDDQSNS = 1.35V, VOUT = 0.675V,
VIN = VDDQSNS = 1.35V, VOUT = 0.675V, VCNTL = 5V VCNTL = 3.3V
0.575 0.575
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
Output Current (A) Output Current (A)

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 RT2568A

Load Regulation Load Regulation

0.85 0.85
0.83 0.83
85°C
0.81 0.81 25°C
Output Voltage (V)

Output Voltage (V)

0.79 0.79 −40°C

0.77 0.77
0.75 85°C 0.75
25°C
0.73 −40°C 0.73
0.71 0.71
0.69 0.69
0.67 0.67
VIN = VDDQSNS = 1.5V, VOUT = 0.75V, VCNTL = 5V VIN = VDDQSNS = 1.5V, VOUT = 0.75V, VCNTL = 3.3V
0.65 0.65
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
Output Current (A) Output Current (A)

Load Regulation Load Regulation

1.00 1.00
0.98 0.98
0.96 0.96 85°C
25°C
Output Voltage (V)

Output Voltage (V)

0.94 0.94 −40°C

0.92 0.92
0.90 85°C 0.90
25°C
0.88 −40°C 0.88
0.86 0.86
0.84 0.84
0.82 0.82
VIN = VDDQSNS = 1.8V, VOUT = 0.9V, VCNTL = 5V VIN = VDDQSNS = 1.8V, VOUT = 0.9V, VCNTL = 3.3V
0.80 0.80
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
Output Current (A) Output Current (A)

Load Regulation Load Regulation

1.35 1.35
VIN = VDDQSNS = 2.5V, VOUT = 1.25V, VCNTL = 3.3V
1.33 1.33
1.31 1.31
Output Voltage (V)

Output Voltage (V)

1.29 1.29
1.27 1.27
85°C
1.25 1.25 85°C
25°C
25°C
1.23 −40°C 1.23 −40°C
1.21 1.21
1.19 1.19
1.17 1.17
VIN = VDDQSNS = 2.5V, VOUT = 1.25V, VCNTL = 5V
1.15 1.15
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
Output Current (A) Output Current (A)

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RT2568A

Output Voltage vs. Temperature REFOUT Voltage vs. Temperature

1.0 1.0

0.9 0.9

REFOUT Voltage (V)

Output Voltage (V)

0.8 0.8

0.7 0.7

0.6 0.6
VIN = VDDQSNS = 1.5V, VOUT = 0.75V, VIN = VDDQSNS = 1.5V, VOUT = 0.75V,
VCNTL = 3.3V VCNTL = 3.3V
0.5 0.5
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

VCNTL Supply Current vs. Temperature VCNTL Shutdown Current vs. Temperature
500.0 350
VCNTL Shutdown Current (μA)1

480.0
VCNTL Supply Current (μA)1

300
460.0
440.0
VCNTL = 5V 250
420.0 VCNTL = 5V
400.0 200
380.0
150 VCNTL = 3.3V
360.0 VCNTL = 3.3V
340.0
100
320.0
VIN = VDDQSNS = 1.5V, VOUT = 0.75V VIN = VDDQSNS = 1.5V, VOUT = 0.75V
300.0 50
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

UVLO vs. Temperature Sourcing Current Limit vs. Temperature

3.0 4.0
2.9
3.5
2.8
2.7 Rising
Current Limit (A)

3.0
UVLO (V)

2.6
2.5 Falling 2.5
2.4
2.0
2.3
2.2
1.5
2.1 VIN = VDDQSNS = 1.5V, VIN = VDDQSNS = 1.5V, VOUT = 0.75V,
VEN = 2V, VOUT = 0.75V VCNTL = 3.3V
2.0 1.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

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 RT2568A

Sinking Current Limit vs. Temperature Power On from EN

4.0

3.5
VEN
Current Limit (A)

3.0 (2V/Div)

VOUT
2.5 (0.5V/Div)
V REFOUT
2.0
(0.5V/Div)

1.5 VCNTL = 3.3V, VIN = 1.5V

VCNTL = 3.3V, IOUT VOUT = 0.75V, IOUT = 1.5A
VIN = VDDQSNS = 1.5V, VOUT = 0.75V (1A/Div) COUT = 50μF
1.0
-50 -25 0 25 50 75 100 125 Time (20μs/Div)
Temperature (°C)

Power Off from EN 0.75VOUT @ 1.5A Transient Response

VCNTL = 3.3V, VIN = 1.5V
VEN VOUT = 0.75V, IOUT = 1.5A
(2V/Div) COUT = 50μF

VOUT VOUT
(0.5V/Div) (10mV/Div)

VREFOUT
(0.5V/Div)
IOUT
(1A/Div) IOUT
(1A/Div)
Source, VIN = 1.5V

Time (40μs/Div) Time (500μs/Div)

0.75VOUT @ 1.5A Transient Response

VOUT
(10mV/Div)

IOUT
(1A/Div)
Sink, VIN = 1.5V

Time (500μs/Div)

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RT2568A
Application Information

Richtek’s component specification does not include the following information in the Application Information section.
Thereby no warranty is given regarding its validity and accuracy. Customers should take responsibility to verify their
own designs and reserve suitable design margin to ensure the functional suitability of their components and systems.

The RT2568A is a 3A sink/source tracking termination the ambient temperature, and θJA is the junction-to-ambient
regulator. It is specifically designed for low-cost and low- thermal resistance.
external component count system such as notebook PC For continuous operation, the maximum operating junction
applications. The RT2568A possesses a high speed temperature indicated under Recommended Operating
operating amplifier that provides fast load transient response Conditions is 125°C. The junction-to-ambient thermal
and only requires two 10μF ceramic input capacitors and resistance, θJA, is highly package dependent. For a
three 10μF ceramic output capacitors. WDFN-10L 3x3 package, the thermal resistance, θJA, is
30.5°C/W on a standard JEDEC 51-7 high effective-thermal-
Capacitor Selection
conductivity four-layer test board. The maximum power
Good bypassing is recommended from VIN to GND to help
dissipation at TA = 25°C can be calculated as below :
improve AC performance. A 10μF or greater input capacitor
located as close as possible to the IC is recommended. PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 3.27W for a
The input capacitor must be located at a distance of less WDFN-10L 3x3 package.
than 0.5 inches from the VIN pin of the IC. The maximum power dissipation depends on the operating
The 1μF ceramic capacitor added close to the VCNTL pin ambient temperature for the fixed TJ(MAX) and the thermal
should be kept away from any parasitic impedance from resistance, θJA. The derating curves in Figure 1 allows
the supply power. For stable operation, the total the designer to see the effect of rising ambient temperature
capacitance of the ceramic capacitor at the VTT output on the maximum power dissipation.
terminal must be larger than 30μF. The RT2568A is 3.5
designed specifically to work with low ESR ceramic output Four-Layer PCB
Maximum Power Dissipation (W)1

capacitor in space saving and performance consideration. 3.0

Larger output capacitance can reduce the noise and 2.5

improve load transient response, stability and PSRR. The
2.0
output capacitor should be located near the VTT output
terminal pin as close as possible. 1.5

Thermal Considerations 1.0

The junction temperature should never exceed the 0.5

absolute maximum junction temperature TJ(MAX), listed
0.0
under Absolute Maximum Ratings, to avoid permanent 0 25 50 75 100 125
damage to the device. The maximum allowable power Ambient Temperature (°C)
dissipation depends on the thermal resistance of the IC
Figure 1. Derating Curve of Maximum Power Dissipation
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is

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 RT2568A
Layout Considerations  Since the output voltage VOUT setting follows the REFIN
For best performance of the RT2568A, the PCB layout pin input voltage level VREFIN (VOUT = VREFIN), the REFIN
suggestions below are highly recommend : pin can connected with independent voltage source for
stable input signal and good VOUT target accuracy. For
 With wide and short connection plane between
the application which VREFIN sinks the voltage source
capacitors and pins for trace impedance minimization.
divided from VIN power trace, with separate connection
 The ground plane connected by a wide copper surface trace between R1 and VIN terminal side not only makes
for good thermal dissipation, add via connection also sure the VREFIN signal stability, but also avoids the
helps reduce the GND loop trace. reference voltage level shrink down caused by VIN trace
 Connect the SENSE pin to the positive node of output loss at high load operation.
capacitor at VOUT terminal for output target level remote Figure 2 shows an example for the layout reference that
sensing. reduces conduction trace loop, helping minimize inductive
parasitic minimize reduce, load transient, and increase
circuit stability.

VIN source
terminal GND Plane
VIN Plane

R1
C1
R2

C3 C5 PGOOD reference
C2
source input
REFIN 1 10 VCNTL R3
VIN 9 PGOOD
PAD

2
VOUT 3 8 GND
EN Enable
C6 PGND
4 7
11
SENSE 5 6 REFOUT signal input

C7 C4 GND Plane

C8
Add via for thermal consideration and
reduce the loop impedance of ground
GND Plane VOUT Plane plane

Figure 2. PCB Layout Guide

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RT2568A
Outline Dimension

D2
D

E E2

SEE DETAIL A
1

e
b 2 1 2 1
A
A3
A1 DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.300 2.650 0.091 0.104
E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069
e 0.500 0.020
L 0.350 0.450 0.014 0.018

W-Type 10L DFN 3x3 Package

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

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Footprint Information

Number of Footprint Dimension (mm)

Package Tolerance
Pin P A B C D Sx Sy M
V/W/U/X/ZDFN3*3-10 10 0.50 3.80 2.10 0.85 0.30 2.55 1.70 2.30 ±0.05

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS2568A-02 May 2023 www.richtek.com

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RT2568A
Datasheet Revision History
Version Date Description Item

Features on P1
02 2023/5/23 Modify Electrical Characteristics on P5
Application Information on P12

Copyright © 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS2568A-02 May 2023

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